1 /***************************************************************************
2 * Copyright (C) 2015 Paul Fertser <fercerpav@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
22 #include <target/target.h>
23 #include <target/armv7m.h>
24 #include <target/cortex_m.h>
25 #include <target/armv7m_trace.h>
26 #include <jtag/interface.h>
27 #include <helper/time_support.h>
29 int armv7m_trace_itm_config(struct target
*target
)
31 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
32 struct armv7m_trace_config
*trace_config
= &armv7m
->trace_config
;
35 retval
= target_write_u32(target
, ITM_LAR
, ITM_LAR_KEY
);
36 if (retval
!= ERROR_OK
)
39 /* pg315 of CoreSight Components
40 * It is recommended that the ITMEn bit is cleared and waits for the
41 * ITMBusy bit to be cleared, before changing any fields in the
42 * Control Register, otherwise the behavior can be unpredictable.
45 retval
= target_read_u32(target
, ITM_TCR
, &itm_tcr
);
46 if (retval
!= ERROR_OK
)
48 retval
= target_write_u32(target
,
50 itm_tcr
& ~ITM_TCR_ITMENA_BIT
52 if (retval
!= ERROR_OK
)
55 int64_t then
= timeval_ms() + 1000;
57 retval
= target_read_u32(target
, ITM_TCR
, &itm_tcr
);
58 if (retval
!= ERROR_OK
)
60 if (timeval_ms() > then
) {
61 LOG_ERROR("timeout waiting for ITM_TCR_BUSY_BIT");
64 } while (itm_tcr
& ITM_TCR_BUSY_BIT
);
66 /* Enable ITM, TXENA, set TraceBusID and other parameters */
67 retval
= target_write_u32(target
, ITM_TCR
, (1 << 0) | (1 << 3) |
68 (trace_config
->itm_diff_timestamps
<< 1) |
69 (trace_config
->itm_synchro_packets
<< 2) |
70 (trace_config
->itm_async_timestamps
<< 4) |
71 (trace_config
->itm_ts_prescale
<< 8) |
72 (trace_config
->trace_bus_id
<< 16));
73 if (retval
!= ERROR_OK
)
76 for (unsigned int i
= 0; i
< 8; i
++) {
77 retval
= target_write_u32(target
, ITM_TER0
+ i
* 4,
78 trace_config
->itm_ter
[i
]);
79 if (retval
!= ERROR_OK
)
86 COMMAND_HANDLER(handle_itm_port_command
)
88 struct target
*target
= get_current_target(CMD_CTX
);
89 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
95 return ERROR_COMMAND_SYNTAX_ERROR
;
97 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[0], port
);
98 COMMAND_PARSE_ON_OFF(CMD_ARGV
[1], enable
);
102 armv7m
->trace_config
.itm_ter
[reg_idx
] |= (1 << port
);
104 armv7m
->trace_config
.itm_ter
[reg_idx
] &= ~(1 << port
);
106 if (CMD_CTX
->mode
== COMMAND_EXEC
)
107 return armv7m_trace_itm_config(target
);
109 armv7m
->trace_config
.itm_deferred_config
= true;
113 COMMAND_HANDLER(handle_itm_ports_command
)
115 struct target
*target
= get_current_target(CMD_CTX
);
116 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
120 return ERROR_COMMAND_SYNTAX_ERROR
;
122 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], enable
);
123 memset(armv7m
->trace_config
.itm_ter
, enable
? 0xff : 0,
124 sizeof(armv7m
->trace_config
.itm_ter
));
126 if (CMD_CTX
->mode
== COMMAND_EXEC
)
127 return armv7m_trace_itm_config(target
);
129 armv7m
->trace_config
.itm_deferred_config
= true;
133 static const struct command_registration itm_command_handlers
[] = {
136 .handler
= handle_itm_port_command
,
138 .help
= "Enable or disable ITM stimulus port",
139 .usage
= "<port> (0|1|on|off)",
143 .handler
= handle_itm_ports_command
,
145 .help
= "Enable or disable all ITM stimulus ports",
146 .usage
= "(0|1|on|off)",
148 COMMAND_REGISTRATION_DONE
151 const struct command_registration armv7m_trace_command_handlers
[] = {
155 .help
= "itm command group",
157 .chain
= itm_command_handlers
,
159 COMMAND_REGISTRATION_DONE
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)