src/target/armv8.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2015 by David Ung                                       *
   5  ***************************************************************************/
   6
   7 #ifndef OPENOCD_TARGET_ARMV8_H
   8 #define OPENOCD_TARGET_ARMV8_H
   9
  10 #include "arm_adi_v5.h"
  11 #include "arm.h"
  12 #include "armv4_5_mmu.h"
  13 #include "armv4_5_cache.h"
  14 #include "armv8_dpm.h"
  15 #include "arm_cti.h"
  16
  17 enum {
  18         ARMV8_R0 = 0,
  19         ARMV8_R1,
  20         ARMV8_R2,
  21         ARMV8_R3,
  22         ARMV8_R4,
  23         ARMV8_R5,
  24         ARMV8_R6,
  25         ARMV8_R7,
  26         ARMV8_R8,
  27         ARMV8_R9,
  28         ARMV8_R10,
  29         ARMV8_R11,
  30         ARMV8_R12,
  31         ARMV8_R13,
  32         ARMV8_R14,
  33         ARMV8_R15,
  34         ARMV8_R16,
  35         ARMV8_R17,
  36         ARMV8_R18,
  37         ARMV8_R19,
  38         ARMV8_R20,
  39         ARMV8_R21,
  40         ARMV8_R22,
  41         ARMV8_R23,
  42         ARMV8_R24,
  43         ARMV8_R25,
  44         ARMV8_R26,
  45         ARMV8_R27,
  46         ARMV8_R28,
  47         ARMV8_R29,
  48         ARMV8_R30,
  49
  50         ARMV8_SP = 31,
  51         ARMV8_PC = 32,
  52         ARMV8_XPSR = 33,
  53
  54         ARMV8_V0 = 34,
  55         ARMV8_V1,
  56         ARMV8_V2,
  57         ARMV8_V3,
  58         ARMV8_V4,
  59         ARMV8_V5,
  60         ARMV8_V6,
  61         ARMV8_V7,
  62         ARMV8_V8,
  63         ARMV8_V9,
  64         ARMV8_V10,
  65         ARMV8_V11,
  66         ARMV8_V12,
  67         ARMV8_V13,
  68         ARMV8_V14,
  69         ARMV8_V15,
  70         ARMV8_V16,
  71         ARMV8_V17,
  72         ARMV8_V18,
  73         ARMV8_V19,
  74         ARMV8_V20,
  75         ARMV8_V21,
  76         ARMV8_V22,
  77         ARMV8_V23,
  78         ARMV8_V24,
  79         ARMV8_V25,
  80         ARMV8_V26,
  81         ARMV8_V27,
  82         ARMV8_V28,
  83         ARMV8_V29,
  84         ARMV8_V30,
  85         ARMV8_V31,
  86         ARMV8_FPSR,
  87         ARMV8_FPCR,
  88
  89         ARMV8_ELR_EL1 = 68,
  90         ARMV8_ESR_EL1 = 69,
  91         ARMV8_SPSR_EL1 = 70,
  92
  93         ARMV8_ELR_EL2 = 71,
  94         ARMV8_ESR_EL2 = 72,
  95         ARMV8_SPSR_EL2 = 73,
  96
  97         ARMV8_ELR_EL3 = 74,
  98         ARMV8_ESR_EL3 = 75,
  99         ARMV8_SPSR_EL3 = 76,
 100
 101         /* Pseudo registers defined by GDB to remove the pauth signature. */
 102         ARMV8_PAUTH_DMASK = 77,
 103         ARMV8_PAUTH_CMASK = 78,
 104
 105         ARMV8_LAST_REG,
 106 };
 107
 108 enum run_control_op {
 109         ARMV8_RUNCONTROL_UNKNOWN = 0,
 110         ARMV8_RUNCONTROL_RESUME = 1,
 111         ARMV8_RUNCONTROL_HALT = 2,
 112         ARMV8_RUNCONTROL_STEP = 3,
 113 };
 114
 115 #define ARMV8_COMMON_MAGIC 0x0A450AAAU
 116
 117 /* VA to PA translation operations opc2 values*/
 118 #define V2PCWPR  0
 119 #define V2PCWPW  1
 120 #define V2PCWUR  2
 121 #define V2PCWUW  3
 122 #define V2POWPR  4
 123 #define V2POWPW  5
 124 #define V2POWUR  6
 125 #define V2POWUW  7
 126 /*   L210/L220 cache controller support */
 127 struct armv8_l2x_cache {
 128         uint32_t base;
 129         uint32_t way;
 130 };
 131
 132 struct armv8_cachesize {
 133         uint32_t level_num;
 134         /*  cache dimensioning */
 135         uint32_t linelen;
 136         uint32_t associativity;
 137         uint32_t nsets;
 138         uint32_t cachesize;
 139         /* info for set way operation on cache */
 140         uint32_t index;
 141         uint32_t index_shift;
 142         uint32_t way;
 143         uint32_t way_shift;
 144 };
 145
 146 /* information about one architecture cache at any level */
 147 struct armv8_arch_cache {
 148         int ctype;                              /* cache type, CLIDR encoding */
 149         struct armv8_cachesize d_u_size;        /* data cache */
 150         struct armv8_cachesize i_size;          /* instruction cache */
 151 };
 152
 153 struct armv8_cache_common {
 154         int info;
 155         int loc;
 156         uint32_t iminline;
 157         uint32_t dminline;
 158         struct armv8_arch_cache arch[6];        /* cache info, L1 - L7 */
 159         int i_cache_enabled;
 160         int d_u_cache_enabled;
 161
 162         /* l2 external unified cache if some */
 163         void *l2_cache;
 164         int (*flush_all_data_cache)(struct target *target);
 165         int (*display_cache_info)(struct command_invocation *cmd,
 166                         struct armv8_cache_common *armv8_cache);
 167 };
 168
 169 struct armv8_mmu_common {
 170         /* following field mmu working way */
 171         int32_t ttbr1_used; /*  -1 not initialized, 0 no ttbr1 1 ttbr1 used and  */
 172         uint64_t ttbr0_mask;/*  masked to be used  */
 173
 174         uint32_t ttbcr;     /* cache for ttbcr register */
 175         uint32_t ttbr_mask[2];
 176         uint32_t ttbr_range[2];
 177
 178         int (*read_physical_memory)(struct target *target, target_addr_t address,
 179                         uint32_t size, uint32_t count, uint8_t *buffer);
 180         struct armv8_cache_common armv8_cache;
 181         uint32_t mmu_enabled;
 182 };
 183
 184 struct armv8_common {
 185         unsigned int common_magic;
 186
 187         struct arm arm;
 188         struct reg_cache *core_cache;
 189
 190         /* Core Debug Unit */
 191         struct arm_dpm dpm;
 192         target_addr_t debug_base;
 193         struct adiv5_ap *debug_ap;
 194
 195         const uint32_t *opcodes;
 196
 197         /* mdir */
 198         uint8_t multi_processor_system;
 199         uint8_t cluster_id;
 200         uint8_t cpu_id;
 201
 202         /* armv8 aarch64 need below information for page translation */
 203         uint8_t va_size;
 204         uint8_t pa_size;
 205         uint32_t page_size;
 206         uint64_t ttbr_base;
 207
 208         struct armv8_mmu_common armv8_mmu;
 209
 210         struct arm_cti *cti;
 211
 212         /* True if OpenOCD provides pointer auth related info to GDB */
 213         bool enable_pauth;
 214
 215         /* last run-control command issued to this target (resume, halt, step) */
 216         enum run_control_op last_run_control_op;
 217
 218         /* Direct processor core register read and writes */
 219         int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
 220         int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
 221
 222         /* SIMD/FPU registers read/write interface */
 223         int (*read_reg_u128)(struct armv8_common *armv8, int num,
 224                         uint64_t *lvalue, uint64_t *hvalue);
 225         int (*write_reg_u128)(struct armv8_common *armv8, int num,
 226                         uint64_t lvalue, uint64_t hvalue);
 227
 228         int (*examine_debug_reason)(struct target *target);
 229         int (*post_debug_entry)(struct target *target);
 230
 231         void (*pre_restore_context)(struct target *target);
 232 };
 233
 234 static inline struct armv8_common *
 235 target_to_armv8(struct target *target)
 236 {
 237         return container_of(target->arch_info, struct armv8_common, arm);
 238 }
 239
 240 static inline bool is_armv8(struct armv8_common *armv8)
 241 {
 242         return armv8->common_magic == ARMV8_COMMON_MAGIC;
 243 }
 244
 245 /* register offsets from armv8.debug_base */
 246 #define CPUV8_DBG_MAINID0               0xD00
 247 #define CPUV8_DBG_CPUFEATURE0   0xD20
 248 #define CPUV8_DBG_DBGFEATURE0   0xD28
 249 #define CPUV8_DBG_MEMFEATURE0   0xD38
 250
 251 #define CPUV8_DBG_LOCKACCESS 0xFB0
 252 #define CPUV8_DBG_LOCKSTATUS 0xFB4
 253
 254 #define CPUV8_DBG_EDESR         0x20
 255 #define CPUV8_DBG_EDECR         0x24
 256 #define CPUV8_DBG_EDWAR0        0x30
 257 #define CPUV8_DBG_EDWAR1        0x34
 258 #define CPUV8_DBG_DSCR          0x088
 259 #define CPUV8_DBG_DRCR          0x090
 260 #define CPUV8_DBG_ECCR          0x098
 261 #define CPUV8_DBG_PRCR          0x310
 262 #define CPUV8_DBG_PRSR          0x314
 263
 264 #define CPUV8_DBG_DTRRX         0x080
 265 #define CPUV8_DBG_ITR           0x084
 266 #define CPUV8_DBG_SCR           0x088
 267 #define CPUV8_DBG_DTRTX         0x08c
 268
 269 #define CPUV8_DBG_BVR_BASE      0x400
 270 #define CPUV8_DBG_BCR_BASE      0x408
 271 #define CPUV8_DBG_WVR_BASE      0x800
 272 #define CPUV8_DBG_WCR_BASE      0x808
 273 #define CPUV8_DBG_VCR           0x01C
 274
 275 #define CPUV8_DBG_OSLAR         0x300
 276
 277 #define CPUV8_DBG_AUTHSTATUS    0xFB8
 278
 279 #define PAGE_SIZE_4KB                           0x1000
 280 #define PAGE_SIZE_4KB_LEVEL0_BITS       39
 281 #define PAGE_SIZE_4KB_LEVEL1_BITS       30
 282 #define PAGE_SIZE_4KB_LEVEL2_BITS       21
 283 #define PAGE_SIZE_4KB_LEVEL3_BITS       12
 284
 285 #define PAGE_SIZE_4KB_LEVEL0_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
 286 #define PAGE_SIZE_4KB_LEVEL1_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
 287 #define PAGE_SIZE_4KB_LEVEL2_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
 288 #define PAGE_SIZE_4KB_LEVEL3_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
 289
 290 #define PAGE_SIZE_4KB_TRBBASE_MASK      0xFFFFFFFFF000
 291
 292 int armv8_arch_state(struct target *target);
 293 int armv8_read_mpidr(struct armv8_common *armv8);
 294 int armv8_identify_cache(struct armv8_common *armv8);
 295 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
 296 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
 297                 target_addr_t *val, int meminfo);
 298 int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val);
 299
 300 int armv8_handle_cache_info_command(struct command_invocation *cmd,
 301                 struct armv8_cache_common *armv8_cache);
 302
 303 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
 304
 305 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
 306 {
 307         switch (core_mode) {
 308         /* Aarch32 modes */
 309         case ARM_MODE_USR:
 310                 return 0;
 311         case ARM_MODE_SVC:
 312         case ARM_MODE_ABT: /* FIXME: EL3? */
 313         case ARM_MODE_IRQ: /* FIXME: EL3? */
 314         case ARM_MODE_FIQ: /* FIXME: EL3? */
 315         case ARM_MODE_UND: /* FIXME: EL3? */
 316         case ARM_MODE_SYS: /* FIXME: EL3? */
 317                 return 1;
 318         /* case ARM_MODE_HYP:
 319          *     return 2;
 320          */
 321         case ARM_MODE_MON:
 322                 return 3;
 323         /* all Aarch64 modes */
 324         default:
 325                 return (core_mode >> 2) & 3;
 326         }
 327 }
 328
 329 const char *armv8_mode_name(unsigned psr_mode);
 330 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
 331 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 332
 333 extern void armv8_free_reg_cache(struct target *target);
 334
 335 extern const struct command_registration armv8_command_handlers[];
 336
 337 #endif /* OPENOCD_TARGET_ARMV8_H */