1 /***************************************************************************
2 * Copyright (C) 2016 by Matthias Welwarsky *
3 * matthias.welwarsky@sysgo.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include "armv8_cache.h"
24 #include "armv8_dpm.h"
25 #include "armv8_opcodes.h"
28 /* CLIDR cache types */
29 #define CACHE_LEVEL_HAS_UNIFIED_CACHE 0x4
30 #define CACHE_LEVEL_HAS_D_CACHE 0x2
31 #define CACHE_LEVEL_HAS_I_CACHE 0x1
33 static int armv8_d_cache_sanity_check(struct armv8_common
*armv8
)
35 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
37 if (armv8_cache
->d_u_cache_enabled
)
40 return ERROR_TARGET_INVALID
;
43 static int armv8_i_cache_sanity_check(struct armv8_common
*armv8
)
45 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
47 if (armv8_cache
->i_cache_enabled
)
50 return ERROR_TARGET_INVALID
;
53 static int armv8_cache_d_inner_flush_level(struct armv8_common
*armv8
, struct armv8_cachesize
*size
, int cl
)
55 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
56 int retval
= ERROR_OK
;
57 int32_t c_way
, c_index
= size
->index
;
59 LOG_DEBUG("cl %" PRId32
, cl
);
63 uint32_t value
= (c_index
<< size
->index_shift
)
64 | (c_way
<< size
->way_shift
) | (cl
<< 1);
66 * DC CISW - Clean and invalidate data cache
69 retval
= dpm
->instr_write_data_r0(dpm
,
70 armv8_opcode(armv8
, ARMV8_OPC_DCCISW
), value
);
71 if (retval
!= ERROR_OK
)
76 } while (c_index
>= 0);
82 static int armv8_cache_d_inner_clean_inval_all(struct armv8_common
*armv8
)
84 struct armv8_cache_common
*cache
= &(armv8
->armv8_mmu
.armv8_cache
);
85 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
89 retval
= armv8_d_cache_sanity_check(armv8
);
90 if (retval
!= ERROR_OK
)
93 retval
= dpm
->prepare(dpm
);
94 if (retval
!= ERROR_OK
)
97 for (cl
= 0; cl
< cache
->loc
; cl
++) {
98 /* skip i-only caches */
99 if (cache
->arch
[cl
].ctype
< CACHE_LEVEL_HAS_D_CACHE
)
102 armv8_cache_d_inner_flush_level(armv8
, &cache
->arch
[cl
].d_u_size
, cl
);
105 retval
= dpm
->finish(dpm
);
109 LOG_ERROR("clean invalidate failed");
115 int armv8_cache_d_inner_flush_virt(struct armv8_common
*armv8
, target_addr_t va
, size_t size
)
117 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
118 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
119 uint64_t linelen
= armv8_cache
->dminline
;
120 target_addr_t va_line
, va_end
;
123 retval
= armv8_d_cache_sanity_check(armv8
);
124 if (retval
!= ERROR_OK
)
127 retval
= dpm
->prepare(dpm
);
128 if (retval
!= ERROR_OK
)
131 va_line
= va
& (-linelen
);
134 while (va_line
< va_end
) {
136 /* Aarch32: DCCIMVAC: ARMV4_5_MCR(15, 0, 0, 7, 14, 1) */
137 retval
= dpm
->instr_write_data_r0_64(dpm
,
138 armv8_opcode(armv8
, ARMV8_OPC_DCCIVAC
), va_line
);
139 if (retval
!= ERROR_OK
)
148 LOG_ERROR("d-cache invalidate failed");
154 int armv8_cache_i_inner_inval_virt(struct armv8_common
*armv8
, target_addr_t va
, size_t size
)
156 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
157 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
158 uint64_t linelen
= armv8_cache
->iminline
;
159 target_addr_t va_line
, va_end
;
162 retval
= armv8_i_cache_sanity_check(armv8
);
163 if (retval
!= ERROR_OK
)
166 retval
= dpm
->prepare(dpm
);
167 if (retval
!= ERROR_OK
)
170 va_line
= va
& (-linelen
);
173 while (va_line
< va_end
) {
174 /* IC IVAU - Invalidate instruction cache by VA to PoU. */
175 retval
= dpm
->instr_write_data_r0_64(dpm
,
176 armv8_opcode(armv8
, ARMV8_OPC_ICIVAU
), va_line
);
177 if (retval
!= ERROR_OK
)
186 LOG_ERROR("d-cache invalidate failed");
192 static int armv8_handle_inner_cache_info_command(struct command_invocation
*cmd
,
193 struct armv8_cache_common
*armv8_cache
)
197 if (armv8_cache
->info
== -1) {
198 command_print(cmd
, "cache not yet identified");
202 for (cl
= 0; cl
< armv8_cache
->loc
; cl
++) {
203 struct armv8_arch_cache
*arch
= &(armv8_cache
->arch
[cl
]);
205 if (arch
->ctype
& 1) {
207 "L%d I-Cache: linelen %" PRIu32
208 ", associativity %" PRIu32
210 ", cachesize %" PRIu32
" KBytes",
212 arch
->i_size
.linelen
,
213 arch
->i_size
.associativity
,
215 arch
->i_size
.cachesize
);
218 if (arch
->ctype
>= 2) {
220 "L%d D-Cache: linelen %" PRIu32
221 ", associativity %" PRIu32
223 ", cachesize %" PRIu32
" KBytes",
225 arch
->d_u_size
.linelen
,
226 arch
->d_u_size
.associativity
,
227 arch
->d_u_size
.nsets
,
228 arch
->d_u_size
.cachesize
);
235 static int _armv8_flush_all_data(struct target
*target
)
237 return armv8_cache_d_inner_clean_inval_all(target_to_armv8(target
));
240 static int armv8_flush_all_data(struct target
*target
)
242 int retval
= ERROR_FAIL
;
243 /* check that armv8_cache is correctly identify */
244 struct armv8_common
*armv8
= target_to_armv8(target
);
245 if (armv8
->armv8_mmu
.armv8_cache
.info
== -1) {
246 LOG_ERROR("trying to flush un-identified cache");
251 /* look if all the other target have been flushed in order to flush level
253 struct target_list
*head
;
254 foreach_smp_target(head
, target
->smp_targets
) {
255 struct target
*curr
= head
->target
;
256 if (curr
->state
== TARGET_HALTED
) {
257 LOG_INFO("Wait flushing data l1 on core %" PRId32
, curr
->coreid
);
258 retval
= _armv8_flush_all_data(curr
);
262 retval
= _armv8_flush_all_data(target
);
266 static int get_cache_info(struct arm_dpm
*dpm
, int cl
, int ct
, uint32_t *cache_reg
)
268 struct armv8_common
*armv8
= dpm
->arm
->arch_info
;
269 int retval
= ERROR_OK
;
271 /* select cache level */
272 retval
= dpm
->instr_write_data_r0(dpm
,
273 armv8_opcode(armv8
, WRITE_REG_CSSELR
),
274 (cl
<< 1) | (ct
== 1 ? 1 : 0));
275 if (retval
!= ERROR_OK
)
278 retval
= dpm
->instr_read_data_r0(dpm
,
279 armv8_opcode(armv8
, READ_REG_CCSIDR
),
285 static struct armv8_cachesize
decode_cache_reg(uint32_t cache_reg
)
287 struct armv8_cachesize size
;
290 size
.linelen
= 16 << (cache_reg
& 0x7);
291 size
.associativity
= ((cache_reg
>> 3) & 0x3ff) + 1;
292 size
.nsets
= ((cache_reg
>> 13) & 0x7fff) + 1;
293 size
.cachesize
= size
.linelen
* size
.associativity
* size
.nsets
/ 1024;
295 /* compute info for set way operation on cache */
296 size
.index_shift
= (cache_reg
& 0x7) + 4;
297 size
.index
= (cache_reg
>> 13) & 0x7fff;
298 size
.way
= ((cache_reg
>> 3) & 0x3ff);
300 while (((size
.way
<< i
) & 0x80000000) == 0)
307 int armv8_identify_cache(struct armv8_common
*armv8
)
309 /* read cache descriptor */
310 int retval
= ERROR_FAIL
;
311 struct arm
*arm
= &armv8
->arm
;
312 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
313 uint32_t csselr
, clidr
, ctr
;
316 struct armv8_cache_common
*cache
= &(armv8
->armv8_mmu
.armv8_cache
);
318 retval
= dpm
->prepare(dpm
);
319 if (retval
!= ERROR_OK
)
322 /* check if we're in an unprivileged mode */
323 if (armv8_curel_from_core_mode(arm
->core_mode
) < SYSTEM_CUREL_EL1
) {
324 retval
= armv8_dpm_modeswitch(dpm
, ARMV8_64_EL1H
);
325 if (retval
!= ERROR_OK
)
330 retval
= dpm
->instr_read_data_r0(dpm
,
331 armv8_opcode(armv8
, READ_REG_CTR
), &ctr
);
332 if (retval
!= ERROR_OK
)
335 cache
->iminline
= 4UL << (ctr
& 0xf);
336 cache
->dminline
= 4UL << ((ctr
& 0xf0000) >> 16);
337 LOG_DEBUG("ctr %" PRIx32
" ctr.iminline %" PRIu32
" ctr.dminline %" PRIu32
,
338 ctr
, cache
->iminline
, cache
->dminline
);
341 retval
= dpm
->instr_read_data_r0(dpm
,
342 armv8_opcode(armv8
, READ_REG_CLIDR
), &clidr
);
343 if (retval
!= ERROR_OK
)
346 cache
->loc
= (clidr
& 0x7000000) >> 24;
347 LOG_DEBUG("Number of cache levels to PoC %" PRId32
, cache
->loc
);
349 /* retrieve selected cache for later restore
350 * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
351 retval
= dpm
->instr_read_data_r0(dpm
,
352 armv8_opcode(armv8
, READ_REG_CSSELR
), &csselr
);
353 if (retval
!= ERROR_OK
)
356 /* retrieve all available inner caches */
357 for (cl
= 0; cl
< cache
->loc
; clidr
>>= 3, cl
++) {
359 /* isolate cache type at current level */
362 /* skip reserved values */
363 if (ctype
> CACHE_LEVEL_HAS_UNIFIED_CACHE
)
366 /* separate d or unified d/i cache at this level ? */
367 if (ctype
& (CACHE_LEVEL_HAS_UNIFIED_CACHE
| CACHE_LEVEL_HAS_D_CACHE
)) {
368 /* retrieve d-cache info */
369 retval
= get_cache_info(dpm
, cl
, 0, &cache_reg
);
370 if (retval
!= ERROR_OK
)
372 cache
->arch
[cl
].d_u_size
= decode_cache_reg(cache_reg
);
374 LOG_DEBUG("data/unified cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32
,
375 cache
->arch
[cl
].d_u_size
.index
,
376 cache
->arch
[cl
].d_u_size
.index_shift
,
377 cache
->arch
[cl
].d_u_size
.way
,
378 cache
->arch
[cl
].d_u_size
.way_shift
);
380 LOG_DEBUG("cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
381 cache
->arch
[cl
].d_u_size
.linelen
,
382 cache
->arch
[cl
].d_u_size
.cachesize
,
383 cache
->arch
[cl
].d_u_size
.associativity
);
386 /* separate i-cache at this level ? */
387 if (ctype
& CACHE_LEVEL_HAS_I_CACHE
) {
388 /* retrieve i-cache info */
389 retval
= get_cache_info(dpm
, cl
, 1, &cache_reg
);
390 if (retval
!= ERROR_OK
)
392 cache
->arch
[cl
].i_size
= decode_cache_reg(cache_reg
);
394 LOG_DEBUG("instruction cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32
,
395 cache
->arch
[cl
].i_size
.index
,
396 cache
->arch
[cl
].i_size
.index_shift
,
397 cache
->arch
[cl
].i_size
.way
,
398 cache
->arch
[cl
].i_size
.way_shift
);
400 LOG_DEBUG("cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
401 cache
->arch
[cl
].i_size
.linelen
,
402 cache
->arch
[cl
].i_size
.cachesize
,
403 cache
->arch
[cl
].i_size
.associativity
);
406 cache
->arch
[cl
].ctype
= ctype
;
409 /* restore selected cache */
410 dpm
->instr_write_data_r0(dpm
,
411 armv8_opcode(armv8
, WRITE_REG_CSSELR
), csselr
);
412 if (retval
!= ERROR_OK
)
415 armv8
->armv8_mmu
.armv8_cache
.info
= 1;
417 /* if no l2 cache initialize l1 data cache flush function function */
418 if (!armv8
->armv8_mmu
.armv8_cache
.flush_all_data_cache
) {
419 armv8
->armv8_mmu
.armv8_cache
.display_cache_info
=
420 armv8_handle_inner_cache_info_command
;
421 armv8
->armv8_mmu
.armv8_cache
.flush_all_data_cache
=
422 armv8_flush_all_data
;
426 armv8_dpm_modeswitch(dpm
, ARM_MODE_ANY
);
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