1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program; if not, write to the *
38 * Free Software Foundation, Inc., *
39 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
41 * Cortex-A8(tm) TRM, ARM DDI 0344H *
42 * Cortex-A9(tm) TRM, ARM DDI 0407F *
43 * Cortex-A4(tm) TRM, ARM DDI 0363E *
44 * Cortex-A15(tm)TRM, ARM DDI 0438C *
46 ***************************************************************************/
52 #include "breakpoints.h"
55 #include "target_request.h"
56 #include "target_type.h"
57 #include "arm_opcodes.h"
58 #include <helper/time_support.h>
60 static int cortex_a_poll(struct target
*target
);
61 static int cortex_a_debug_entry(struct target
*target
);
62 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
63 static int cortex_a_set_breakpoint(struct target
*target
,
64 struct breakpoint
*breakpoint
, uint8_t matchmode
);
65 static int cortex_a_set_context_breakpoint(struct target
*target
,
66 struct breakpoint
*breakpoint
, uint8_t matchmode
);
67 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
68 struct breakpoint
*breakpoint
);
69 static int cortex_a_unset_breakpoint(struct target
*target
,
70 struct breakpoint
*breakpoint
);
71 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
72 uint32_t *value
, int regnum
);
73 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
74 uint32_t value
, int regnum
);
75 static int cortex_a_mmu(struct target
*target
, int *enabled
);
76 static int cortex_a_virt2phys(struct target
*target
,
77 uint32_t virt
, uint32_t *phys
);
78 static int cortex_a_read_apb_ab_memory(struct target
*target
,
79 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
82 /* restore cp15_control_reg at resume */
83 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
85 int retval
= ERROR_OK
;
86 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
87 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
89 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
90 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
91 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
92 retval
= armv7a
->arm
.mcr(target
, 15,
95 cortex_a
->cp15_control_reg
);
100 /* check address before cortex_a_apb read write access with mmu on
101 * remove apb predictible data abort */
102 static int cortex_a_check_address(struct target
*target
, uint32_t address
)
104 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
105 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
106 uint32_t os_border
= armv7a
->armv7a_mmu
.os_border
;
107 if ((address
< os_border
) &&
108 (armv7a
->arm
.core_mode
== ARM_MODE_SVC
)) {
109 LOG_ERROR("%" PRIx32
" access in userspace and target in supervisor", address
);
112 if ((address
>= os_border
) &&
113 (cortex_a
->curr_mode
!= ARM_MODE_SVC
)) {
114 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
115 cortex_a
->curr_mode
= ARM_MODE_SVC
;
116 LOG_INFO("%" PRIx32
" access in kernel space and target not in supervisor",
120 if ((address
< os_border
) &&
121 (cortex_a
->curr_mode
== ARM_MODE_SVC
)) {
122 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
123 cortex_a
->curr_mode
= ARM_MODE_ANY
;
127 /* modify cp15_control_reg in order to enable or disable mmu for :
128 * - virt2phys address conversion
129 * - read or write memory in phys or virt address */
130 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
132 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
133 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
134 int retval
= ERROR_OK
;
136 /* if mmu enabled at target stop and mmu not enable */
137 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
138 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
141 if (!(cortex_a
->cp15_control_reg_curr
& 0x1U
)) {
142 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
143 retval
= armv7a
->arm
.mcr(target
, 15,
146 cortex_a
->cp15_control_reg_curr
);
149 if (cortex_a
->cp15_control_reg_curr
& 0x4U
) {
150 /* data cache is active */
151 cortex_a
->cp15_control_reg_curr
&= ~0x4U
;
152 /* flush data cache armv7 function to be called */
153 if (armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache
)
154 armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache(target
);
156 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
)) {
157 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
158 retval
= armv7a
->arm
.mcr(target
, 15,
161 cortex_a
->cp15_control_reg_curr
);
168 * Cortex-A Basic debug access, very low level assumes state is saved
170 static int cortex_a8_init_debug_access(struct target
*target
)
172 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
173 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
178 /* Unlocking the debug registers for modification
179 * The debugport might be uninitialised so try twice */
180 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
181 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
182 if (retval
!= ERROR_OK
) {
184 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
185 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
186 if (retval
== ERROR_OK
)
188 "Locking debug access failed on first, but succeeded on second try.");
195 * Cortex-A Basic debug access, very low level assumes state is saved
197 static int cortex_a_init_debug_access(struct target
*target
)
199 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
200 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
203 uint32_t cortex_part_num
;
204 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
207 cortex_part_num
= (cortex_a
->cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >>
208 CORTEX_A_MIDR_PARTNUM_SHIFT
;
210 switch (cortex_part_num
) {
211 case CORTEX_A7_PARTNUM
:
212 case CORTEX_A15_PARTNUM
:
213 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
214 armv7a
->debug_base
+ CPUDBG_OSLSR
,
216 if (retval
!= ERROR_OK
)
219 LOG_DEBUG("DBGOSLSR 0x%" PRIx32
, dbg_osreg
);
221 if (dbg_osreg
& CPUDBG_OSLAR_LK_MASK
)
222 /* Unlocking the DEBUG OS registers for modification */
223 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
224 armv7a
->debug_base
+ CPUDBG_OSLAR
,
228 case CORTEX_A5_PARTNUM
:
229 case CORTEX_A8_PARTNUM
:
230 case CORTEX_A9_PARTNUM
:
232 retval
= cortex_a8_init_debug_access(target
);
235 if (retval
!= ERROR_OK
)
237 /* Clear Sticky Power Down status Bit in PRSR to enable access to
238 the registers in the Core Power Domain */
239 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
240 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
241 LOG_DEBUG("target->coreid %d DBGPRSR 0x%x ", target
->coreid
, dbg_osreg
);
243 if (retval
!= ERROR_OK
)
246 /* Enabling of instruction execution in debug mode is done in debug_entry code */
248 /* Resync breakpoint registers */
250 /* Since this is likely called from init or reset, update target state information*/
251 return cortex_a_poll(target
);
254 /* To reduce needless round-trips, pass in a pointer to the current
255 * DSCR value. Initialize it to zero if you just need to know the
256 * value on return from this function; or DSCR_INSTR_COMP if you
257 * happen to know that no instruction is pending.
259 static int cortex_a_exec_opcode(struct target
*target
,
260 uint32_t opcode
, uint32_t *dscr_p
)
264 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
265 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
267 dscr
= dscr_p
? *dscr_p
: 0;
269 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
271 /* Wait for InstrCompl bit to be set */
272 long long then
= timeval_ms();
273 while ((dscr
& DSCR_INSTR_COMP
) == 0) {
274 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
275 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
276 if (retval
!= ERROR_OK
) {
277 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32
, opcode
);
280 if (timeval_ms() > then
+ 1000) {
281 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
286 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
287 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
288 if (retval
!= ERROR_OK
)
293 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
294 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
295 if (retval
!= ERROR_OK
) {
296 LOG_ERROR("Could not read DSCR register");
299 if (timeval_ms() > then
+ 1000) {
300 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
303 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
311 /**************************************************************************
312 Read core register with very few exec_opcode, fast but needs work_area.
313 This can cause problems with MMU active.
314 **************************************************************************/
315 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
318 int retval
= ERROR_OK
;
319 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
320 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
322 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
323 if (retval
!= ERROR_OK
)
325 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
326 if (retval
!= ERROR_OK
)
328 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
329 if (retval
!= ERROR_OK
)
332 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
,
333 (uint8_t *)(®file
[1]), 4, 15, address
);
338 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
339 uint32_t *value
, int regnum
)
341 int retval
= ERROR_OK
;
342 uint8_t reg
= regnum
&0xFF;
344 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
345 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
351 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
352 retval
= cortex_a_exec_opcode(target
,
353 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
355 if (retval
!= ERROR_OK
)
357 } else if (reg
== 15) {
358 /* "MOV r0, r15"; then move r0 to DCCTX */
359 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
360 if (retval
!= ERROR_OK
)
362 retval
= cortex_a_exec_opcode(target
,
363 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
365 if (retval
!= ERROR_OK
)
368 /* "MRS r0, CPSR" or "MRS r0, SPSR"
369 * then move r0 to DCCTX
371 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
372 if (retval
!= ERROR_OK
)
374 retval
= cortex_a_exec_opcode(target
,
375 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
377 if (retval
!= ERROR_OK
)
381 /* Wait for DTRRXfull then read DTRRTX */
382 long long then
= timeval_ms();
383 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
384 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
385 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
386 if (retval
!= ERROR_OK
)
388 if (timeval_ms() > then
+ 1000) {
389 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
394 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
395 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
396 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
401 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
402 uint32_t value
, int regnum
)
404 int retval
= ERROR_OK
;
405 uint8_t Rd
= regnum
&0xFF;
407 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
408 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
410 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
412 /* Check that DCCRX is not full */
413 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
414 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
415 if (retval
!= ERROR_OK
)
417 if (dscr
& DSCR_DTR_RX_FULL
) {
418 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
419 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
420 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
422 if (retval
!= ERROR_OK
)
429 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
430 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
431 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
432 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
433 if (retval
!= ERROR_OK
)
437 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
438 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
441 if (retval
!= ERROR_OK
)
443 } else if (Rd
== 15) {
444 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
447 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
449 if (retval
!= ERROR_OK
)
451 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
452 if (retval
!= ERROR_OK
)
455 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
456 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
458 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
460 if (retval
!= ERROR_OK
)
462 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
464 if (retval
!= ERROR_OK
)
467 /* "Prefetch flush" after modifying execution status in CPSR */
469 retval
= cortex_a_exec_opcode(target
,
470 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
472 if (retval
!= ERROR_OK
)
480 /* Write to memory mapped registers directly with no cache or mmu handling */
481 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
486 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
487 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
489 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, address
, value
);
495 * Cortex-A implementation of Debug Programmer's Model
497 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
498 * so there's no need to poll for it before executing an instruction.
500 * NOTE that in several of these cases the "stall" mode might be useful.
501 * It'd let us queue a few operations together... prepare/finish might
502 * be the places to enable/disable that mode.
505 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
507 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
510 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
512 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
513 return mem_ap_sel_write_u32(a
->armv7a_common
.arm
.dap
,
514 a
->armv7a_common
.debug_ap
, a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
517 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
520 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
521 uint32_t dscr
= DSCR_INSTR_COMP
;
527 /* Wait for DTRRXfull */
528 long long then
= timeval_ms();
529 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
530 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
531 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
533 if (retval
!= ERROR_OK
)
535 if (timeval_ms() > then
+ 1000) {
536 LOG_ERROR("Timeout waiting for read dcc");
541 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
542 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
543 if (retval
!= ERROR_OK
)
545 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
553 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
555 struct cortex_a_common
*a
= dpm_to_a(dpm
);
556 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
560 /* set up invariant: INSTR_COMP is set after ever DPM operation */
561 long long then
= timeval_ms();
563 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
564 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
566 if (retval
!= ERROR_OK
)
568 if ((dscr
& DSCR_INSTR_COMP
) != 0)
570 if (timeval_ms() > then
+ 1000) {
571 LOG_ERROR("Timeout waiting for dpm prepare");
576 /* this "should never happen" ... */
577 if (dscr
& DSCR_DTR_RX_FULL
) {
578 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
580 retval
= cortex_a_exec_opcode(
581 a
->armv7a_common
.arm
.target
,
582 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
584 if (retval
!= ERROR_OK
)
591 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
593 /* REVISIT what could be done here? */
597 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
598 uint32_t opcode
, uint32_t data
)
600 struct cortex_a_common
*a
= dpm_to_a(dpm
);
602 uint32_t dscr
= DSCR_INSTR_COMP
;
604 retval
= cortex_a_write_dcc(a
, data
);
605 if (retval
!= ERROR_OK
)
608 return cortex_a_exec_opcode(
609 a
->armv7a_common
.arm
.target
,
614 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
615 uint32_t opcode
, uint32_t data
)
617 struct cortex_a_common
*a
= dpm_to_a(dpm
);
618 uint32_t dscr
= DSCR_INSTR_COMP
;
621 retval
= cortex_a_write_dcc(a
, data
);
622 if (retval
!= ERROR_OK
)
625 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
626 retval
= cortex_a_exec_opcode(
627 a
->armv7a_common
.arm
.target
,
628 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
630 if (retval
!= ERROR_OK
)
633 /* then the opcode, taking data from R0 */
634 retval
= cortex_a_exec_opcode(
635 a
->armv7a_common
.arm
.target
,
642 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
644 struct target
*target
= dpm
->arm
->target
;
645 uint32_t dscr
= DSCR_INSTR_COMP
;
647 /* "Prefetch flush" after modifying execution status in CPSR */
648 return cortex_a_exec_opcode(target
,
649 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
653 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
654 uint32_t opcode
, uint32_t *data
)
656 struct cortex_a_common
*a
= dpm_to_a(dpm
);
658 uint32_t dscr
= DSCR_INSTR_COMP
;
660 /* the opcode, writing data to DCC */
661 retval
= cortex_a_exec_opcode(
662 a
->armv7a_common
.arm
.target
,
665 if (retval
!= ERROR_OK
)
668 return cortex_a_read_dcc(a
, data
, &dscr
);
672 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
673 uint32_t opcode
, uint32_t *data
)
675 struct cortex_a_common
*a
= dpm_to_a(dpm
);
676 uint32_t dscr
= DSCR_INSTR_COMP
;
679 /* the opcode, writing data to R0 */
680 retval
= cortex_a_exec_opcode(
681 a
->armv7a_common
.arm
.target
,
684 if (retval
!= ERROR_OK
)
687 /* write R0 to DCC */
688 retval
= cortex_a_exec_opcode(
689 a
->armv7a_common
.arm
.target
,
690 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
692 if (retval
!= ERROR_OK
)
695 return cortex_a_read_dcc(a
, data
, &dscr
);
698 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
699 uint32_t addr
, uint32_t control
)
701 struct cortex_a_common
*a
= dpm_to_a(dpm
);
702 uint32_t vr
= a
->armv7a_common
.debug_base
;
703 uint32_t cr
= a
->armv7a_common
.debug_base
;
707 case 0 ... 15: /* breakpoints */
708 vr
+= CPUDBG_BVR_BASE
;
709 cr
+= CPUDBG_BCR_BASE
;
711 case 16 ... 31: /* watchpoints */
712 vr
+= CPUDBG_WVR_BASE
;
713 cr
+= CPUDBG_WCR_BASE
;
722 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
723 (unsigned) vr
, (unsigned) cr
);
725 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
727 if (retval
!= ERROR_OK
)
729 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
734 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
736 struct cortex_a_common
*a
= dpm_to_a(dpm
);
741 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
744 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
752 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
754 /* clear control register */
755 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
758 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
760 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
763 dpm
->arm
= &a
->armv7a_common
.arm
;
766 dpm
->prepare
= cortex_a_dpm_prepare
;
767 dpm
->finish
= cortex_a_dpm_finish
;
769 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
770 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
771 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
773 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
774 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
776 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
777 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
779 retval
= arm_dpm_setup(dpm
);
780 if (retval
== ERROR_OK
)
781 retval
= arm_dpm_initialize(dpm
);
785 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
787 struct target_list
*head
;
791 while (head
!= (struct target_list
*)NULL
) {
793 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
799 static int cortex_a_halt(struct target
*target
);
801 static int cortex_a_halt_smp(struct target
*target
)
804 struct target_list
*head
;
807 while (head
!= (struct target_list
*)NULL
) {
809 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
810 retval
+= cortex_a_halt(curr
);
816 static int update_halt_gdb(struct target
*target
)
819 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
820 target
->gdb_service
->target
= target
;
821 target
->gdb_service
->core
[0] = target
->coreid
;
822 retval
+= cortex_a_halt_smp(target
);
828 * Cortex-A Run control
831 static int cortex_a_poll(struct target
*target
)
833 int retval
= ERROR_OK
;
835 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
836 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
837 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
838 enum target_state prev_target_state
= target
->state
;
839 /* toggle to another core is done by gdb as follow */
840 /* maint packet J core_id */
842 /* the next polling trigger an halt event sent to gdb */
843 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
844 (target
->gdb_service
) &&
845 (target
->gdb_service
->target
== NULL
)) {
846 target
->gdb_service
->target
=
847 get_cortex_a(target
, target
->gdb_service
->core
[1]);
848 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
851 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
852 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
853 if (retval
!= ERROR_OK
)
855 cortex_a
->cpudbg_dscr
= dscr
;
857 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
858 if (prev_target_state
!= TARGET_HALTED
) {
859 /* We have a halting debug event */
860 LOG_DEBUG("Target halted");
861 target
->state
= TARGET_HALTED
;
862 if ((prev_target_state
== TARGET_RUNNING
)
863 || (prev_target_state
== TARGET_UNKNOWN
)
864 || (prev_target_state
== TARGET_RESET
)) {
865 retval
= cortex_a_debug_entry(target
);
866 if (retval
!= ERROR_OK
)
869 retval
= update_halt_gdb(target
);
870 if (retval
!= ERROR_OK
)
873 target_call_event_callbacks(target
,
874 TARGET_EVENT_HALTED
);
876 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
879 retval
= cortex_a_debug_entry(target
);
880 if (retval
!= ERROR_OK
)
883 retval
= update_halt_gdb(target
);
884 if (retval
!= ERROR_OK
)
888 target_call_event_callbacks(target
,
889 TARGET_EVENT_DEBUG_HALTED
);
892 } else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
893 target
->state
= TARGET_RUNNING
;
895 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
896 target
->state
= TARGET_UNKNOWN
;
902 static int cortex_a_halt(struct target
*target
)
904 int retval
= ERROR_OK
;
906 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
907 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
910 * Tell the core to be halted by writing DRCR with 0x1
911 * and then wait for the core to be halted.
913 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
914 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
915 if (retval
!= ERROR_OK
)
919 * enter halting debug mode
921 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
922 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
923 if (retval
!= ERROR_OK
)
926 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
927 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
928 if (retval
!= ERROR_OK
)
931 long long then
= timeval_ms();
933 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
934 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
935 if (retval
!= ERROR_OK
)
937 if ((dscr
& DSCR_CORE_HALTED
) != 0)
939 if (timeval_ms() > then
+ 1000) {
940 LOG_ERROR("Timeout waiting for halt");
945 target
->debug_reason
= DBG_REASON_DBGRQ
;
950 static int cortex_a_internal_restore(struct target
*target
, int current
,
951 uint32_t *address
, int handle_breakpoints
, int debug_execution
)
953 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
954 struct arm
*arm
= &armv7a
->arm
;
958 if (!debug_execution
)
959 target_free_all_working_areas(target
);
962 if (debug_execution
) {
963 /* Disable interrupts */
964 /* We disable interrupts in the PRIMASK register instead of
965 * masking with C_MASKINTS,
966 * This is probably the same issue as Cortex-M3 Errata 377493:
967 * C_MASKINTS in parallel with disabled interrupts can cause
968 * local faults to not be taken. */
969 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
970 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
971 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
973 /* Make sure we are in Thumb mode */
974 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
975 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
977 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
978 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
982 /* current = 1: continue on current pc, otherwise continue at <address> */
983 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
985 resume_pc
= *address
;
987 *address
= resume_pc
;
989 /* Make sure that the Armv7 gdb thumb fixups does not
990 * kill the return address
992 switch (arm
->core_state
) {
994 resume_pc
&= 0xFFFFFFFC;
996 case ARM_STATE_THUMB
:
997 case ARM_STATE_THUMB_EE
:
998 /* When the return address is loaded into PC
999 * bit 0 must be 1 to stay in Thumb state
1003 case ARM_STATE_JAZELLE
:
1004 LOG_ERROR("How do I resume into Jazelle state??");
1007 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
1008 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1011 /* restore dpm_mode at system halt */
1012 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1013 /* called it now before restoring context because it uses cpu
1014 * register r0 for restoring cp15 control register */
1015 retval
= cortex_a_restore_cp15_control_reg(target
);
1016 if (retval
!= ERROR_OK
)
1018 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1019 if (retval
!= ERROR_OK
)
1021 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1022 target
->state
= TARGET_RUNNING
;
1024 /* registers are now invalid */
1025 register_cache_invalidate(arm
->core_cache
);
1028 /* the front-end may request us not to handle breakpoints */
1029 if (handle_breakpoints
) {
1030 /* Single step past breakpoint at current address */
1031 breakpoint
= breakpoint_find(target
, resume_pc
);
1033 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1034 cortex_m3_unset_breakpoint(target
, breakpoint
);
1035 cortex_m3_single_step_core(target
);
1036 cortex_m3_set_breakpoint(target
, breakpoint
);
1044 static int cortex_a_internal_restart(struct target
*target
)
1046 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1047 struct arm
*arm
= &armv7a
->arm
;
1048 struct adiv5_dap
*swjdp
= arm
->dap
;
1052 * * Restart core and wait for it to be started. Clear ITRen and sticky
1053 * * exception flags: see ARMv7 ARM, C5.9.
1055 * REVISIT: for single stepping, we probably want to
1056 * disable IRQs by default, with optional override...
1059 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1060 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1061 if (retval
!= ERROR_OK
)
1064 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1065 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1067 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1068 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1069 if (retval
!= ERROR_OK
)
1072 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1073 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1074 DRCR_CLEAR_EXCEPTIONS
);
1075 if (retval
!= ERROR_OK
)
1078 long long then
= timeval_ms();
1080 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1081 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1082 if (retval
!= ERROR_OK
)
1084 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1086 if (timeval_ms() > then
+ 1000) {
1087 LOG_ERROR("Timeout waiting for resume");
1092 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1093 target
->state
= TARGET_RUNNING
;
1095 /* registers are now invalid */
1096 register_cache_invalidate(arm
->core_cache
);
1101 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1104 struct target_list
*head
;
1105 struct target
*curr
;
1107 head
= target
->head
;
1108 while (head
!= (struct target_list
*)NULL
) {
1109 curr
= head
->target
;
1110 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
1111 /* resume current address , not in step mode */
1112 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1113 handle_breakpoints
, 0);
1114 retval
+= cortex_a_internal_restart(curr
);
1122 static int cortex_a_resume(struct target
*target
, int current
,
1123 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1126 /* dummy resume for smp toggle in order to reduce gdb impact */
1127 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1128 /* simulate a start and halt of target */
1129 target
->gdb_service
->target
= NULL
;
1130 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1131 /* fake resume at next poll we play the target core[1], see poll*/
1132 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1135 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1137 target
->gdb_service
->core
[0] = -1;
1138 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1139 if (retval
!= ERROR_OK
)
1142 cortex_a_internal_restart(target
);
1144 if (!debug_execution
) {
1145 target
->state
= TARGET_RUNNING
;
1146 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1147 LOG_DEBUG("target resumed at 0x%" PRIx32
, address
);
1149 target
->state
= TARGET_DEBUG_RUNNING
;
1150 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1151 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, address
);
1157 static int cortex_a_debug_entry(struct target
*target
)
1160 uint32_t regfile
[16], cpsr
, dscr
;
1161 int retval
= ERROR_OK
;
1162 struct working_area
*regfile_working_area
= NULL
;
1163 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1164 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1165 struct arm
*arm
= &armv7a
->arm
;
1166 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1169 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1171 /* REVISIT surely we should not re-read DSCR !! */
1172 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1173 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1174 if (retval
!= ERROR_OK
)
1177 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1178 * imprecise data aborts get discarded by issuing a Data
1179 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1182 /* Enable the ITR execution once we are in debug mode */
1183 dscr
|= DSCR_ITR_EN
;
1184 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1185 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1186 if (retval
!= ERROR_OK
)
1189 /* Examine debug reason */
1190 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1192 /* save address of instruction that triggered the watchpoint? */
1193 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1196 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1197 armv7a
->debug_base
+ CPUDBG_WFAR
,
1199 if (retval
!= ERROR_OK
)
1201 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1204 /* REVISIT fast_reg_read is never set ... */
1206 /* Examine target state and mode */
1207 if (cortex_a
->fast_reg_read
)
1208 target_alloc_working_area(target
, 64, ®file_working_area
);
1210 /* First load register acessible through core debug port*/
1211 if (!regfile_working_area
)
1212 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1214 retval
= cortex_a_read_regs_through_mem(target
,
1215 regfile_working_area
->address
, regfile
);
1217 target_free_working_area(target
, regfile_working_area
);
1218 if (retval
!= ERROR_OK
)
1221 /* read Current PSR */
1222 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1223 /* store current cpsr */
1224 if (retval
!= ERROR_OK
)
1227 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1229 arm_set_cpsr(arm
, cpsr
);
1232 for (i
= 0; i
<= ARM_PC
; i
++) {
1233 reg
= arm_reg_current(arm
, i
);
1235 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1240 /* Fixup PC Resume Address */
1241 if (cpsr
& (1 << 5)) {
1242 /* T bit set for Thumb or ThumbEE state */
1243 regfile
[ARM_PC
] -= 4;
1246 regfile
[ARM_PC
] -= 8;
1250 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1251 reg
->dirty
= reg
->valid
;
1255 /* TODO, Move this */
1256 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1257 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1258 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1260 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1261 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1263 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1264 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1267 /* Are we in an exception handler */
1268 /* armv4_5->exception_number = 0; */
1269 if (armv7a
->post_debug_entry
) {
1270 retval
= armv7a
->post_debug_entry(target
);
1271 if (retval
!= ERROR_OK
)
1278 static int cortex_a_post_debug_entry(struct target
*target
)
1280 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1281 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1284 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1285 retval
= armv7a
->arm
.mrc(target
, 15,
1286 0, 0, /* op1, op2 */
1287 1, 0, /* CRn, CRm */
1288 &cortex_a
->cp15_control_reg
);
1289 if (retval
!= ERROR_OK
)
1291 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1292 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1294 if (armv7a
->armv7a_mmu
.armv7a_cache
.ctype
== -1)
1295 armv7a_identify_cache(target
);
1297 if (armv7a
->is_armv7r
) {
1298 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1300 armv7a
->armv7a_mmu
.mmu_enabled
=
1301 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1303 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1304 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1305 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1306 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1307 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1312 static int cortex_a_step(struct target
*target
, int current
, uint32_t address
,
1313 int handle_breakpoints
)
1315 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1316 struct arm
*arm
= &armv7a
->arm
;
1317 struct breakpoint
*breakpoint
= NULL
;
1318 struct breakpoint stepbreakpoint
;
1322 if (target
->state
!= TARGET_HALTED
) {
1323 LOG_WARNING("target not halted");
1324 return ERROR_TARGET_NOT_HALTED
;
1327 /* current = 1: continue on current pc, otherwise continue at <address> */
1330 buf_set_u32(r
->value
, 0, 32, address
);
1332 address
= buf_get_u32(r
->value
, 0, 32);
1334 /* The front-end may request us not to handle breakpoints.
1335 * But since Cortex-A uses breakpoint for single step,
1336 * we MUST handle breakpoints.
1338 handle_breakpoints
= 1;
1339 if (handle_breakpoints
) {
1340 breakpoint
= breakpoint_find(target
, address
);
1342 cortex_a_unset_breakpoint(target
, breakpoint
);
1345 /* Setup single step breakpoint */
1346 stepbreakpoint
.address
= address
;
1347 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1349 stepbreakpoint
.type
= BKPT_HARD
;
1350 stepbreakpoint
.set
= 0;
1352 /* Break on IVA mismatch */
1353 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1355 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1357 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1358 if (retval
!= ERROR_OK
)
1361 long long then
= timeval_ms();
1362 while (target
->state
!= TARGET_HALTED
) {
1363 retval
= cortex_a_poll(target
);
1364 if (retval
!= ERROR_OK
)
1366 if (timeval_ms() > then
+ 1000) {
1367 LOG_ERROR("timeout waiting for target halt");
1372 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1374 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1377 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1379 if (target
->state
!= TARGET_HALTED
)
1380 LOG_DEBUG("target stepped");
1385 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1387 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1391 if (armv7a
->pre_restore_context
)
1392 armv7a
->pre_restore_context(target
);
1394 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1398 * Cortex-A Breakpoint and watchpoint functions
1401 /* Setup hardware Breakpoint Register Pair */
1402 static int cortex_a_set_breakpoint(struct target
*target
,
1403 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1408 uint8_t byte_addr_select
= 0x0F;
1409 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1410 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1411 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1413 if (breakpoint
->set
) {
1414 LOG_WARNING("breakpoint already set");
1418 if (breakpoint
->type
== BKPT_HARD
) {
1419 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1421 if (brp_i
>= cortex_a
->brp_num
) {
1422 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1423 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1425 breakpoint
->set
= brp_i
+ 1;
1426 if (breakpoint
->length
== 2)
1427 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1428 control
= ((matchmode
& 0x7) << 20)
1429 | (byte_addr_select
<< 5)
1431 brp_list
[brp_i
].used
= 1;
1432 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1433 brp_list
[brp_i
].control
= control
;
1434 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1435 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1436 brp_list
[brp_i
].value
);
1437 if (retval
!= ERROR_OK
)
1439 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1440 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1441 brp_list
[brp_i
].control
);
1442 if (retval
!= ERROR_OK
)
1444 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1445 brp_list
[brp_i
].control
,
1446 brp_list
[brp_i
].value
);
1447 } else if (breakpoint
->type
== BKPT_SOFT
) {
1449 if (breakpoint
->length
== 2)
1450 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1452 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1453 retval
= target_read_memory(target
,
1454 breakpoint
->address
& 0xFFFFFFFE,
1455 breakpoint
->length
, 1,
1456 breakpoint
->orig_instr
);
1457 if (retval
!= ERROR_OK
)
1459 retval
= target_write_memory(target
,
1460 breakpoint
->address
& 0xFFFFFFFE,
1461 breakpoint
->length
, 1, code
);
1462 if (retval
!= ERROR_OK
)
1464 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1470 static int cortex_a_set_context_breakpoint(struct target
*target
,
1471 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1473 int retval
= ERROR_FAIL
;
1476 uint8_t byte_addr_select
= 0x0F;
1477 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1478 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1479 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1481 if (breakpoint
->set
) {
1482 LOG_WARNING("breakpoint already set");
1485 /*check available context BRPs*/
1486 while ((brp_list
[brp_i
].used
||
1487 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1490 if (brp_i
>= cortex_a
->brp_num
) {
1491 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1495 breakpoint
->set
= brp_i
+ 1;
1496 control
= ((matchmode
& 0x7) << 20)
1497 | (byte_addr_select
<< 5)
1499 brp_list
[brp_i
].used
= 1;
1500 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1501 brp_list
[brp_i
].control
= control
;
1502 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1503 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1504 brp_list
[brp_i
].value
);
1505 if (retval
!= ERROR_OK
)
1507 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1508 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1509 brp_list
[brp_i
].control
);
1510 if (retval
!= ERROR_OK
)
1512 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1513 brp_list
[brp_i
].control
,
1514 brp_list
[brp_i
].value
);
1519 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1521 int retval
= ERROR_FAIL
;
1522 int brp_1
= 0; /* holds the contextID pair */
1523 int brp_2
= 0; /* holds the IVA pair */
1524 uint32_t control_CTX
, control_IVA
;
1525 uint8_t CTX_byte_addr_select
= 0x0F;
1526 uint8_t IVA_byte_addr_select
= 0x0F;
1527 uint8_t CTX_machmode
= 0x03;
1528 uint8_t IVA_machmode
= 0x01;
1529 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1530 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1531 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1533 if (breakpoint
->set
) {
1534 LOG_WARNING("breakpoint already set");
1537 /*check available context BRPs*/
1538 while ((brp_list
[brp_1
].used
||
1539 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1542 printf("brp(CTX) found num: %d\n", brp_1
);
1543 if (brp_1
>= cortex_a
->brp_num
) {
1544 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1548 while ((brp_list
[brp_2
].used
||
1549 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1552 printf("brp(IVA) found num: %d\n", brp_2
);
1553 if (brp_2
>= cortex_a
->brp_num
) {
1554 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1558 breakpoint
->set
= brp_1
+ 1;
1559 breakpoint
->linked_BRP
= brp_2
;
1560 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1563 | (CTX_byte_addr_select
<< 5)
1565 brp_list
[brp_1
].used
= 1;
1566 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1567 brp_list
[brp_1
].control
= control_CTX
;
1568 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1569 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1570 brp_list
[brp_1
].value
);
1571 if (retval
!= ERROR_OK
)
1573 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1574 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1575 brp_list
[brp_1
].control
);
1576 if (retval
!= ERROR_OK
)
1579 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1581 | (IVA_byte_addr_select
<< 5)
1583 brp_list
[brp_2
].used
= 1;
1584 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1585 brp_list
[brp_2
].control
= control_IVA
;
1586 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1587 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1588 brp_list
[brp_2
].value
);
1589 if (retval
!= ERROR_OK
)
1591 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1592 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1593 brp_list
[brp_2
].control
);
1594 if (retval
!= ERROR_OK
)
1600 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1603 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1604 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1605 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1607 if (!breakpoint
->set
) {
1608 LOG_WARNING("breakpoint not set");
1612 if (breakpoint
->type
== BKPT_HARD
) {
1613 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1614 int brp_i
= breakpoint
->set
- 1;
1615 int brp_j
= breakpoint
->linked_BRP
;
1616 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1617 LOG_DEBUG("Invalid BRP number in breakpoint");
1620 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1621 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1622 brp_list
[brp_i
].used
= 0;
1623 brp_list
[brp_i
].value
= 0;
1624 brp_list
[brp_i
].control
= 0;
1625 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1626 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1627 brp_list
[brp_i
].control
);
1628 if (retval
!= ERROR_OK
)
1630 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1631 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1632 brp_list
[brp_i
].value
);
1633 if (retval
!= ERROR_OK
)
1635 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1636 LOG_DEBUG("Invalid BRP number in breakpoint");
1639 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1640 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1641 brp_list
[brp_j
].used
= 0;
1642 brp_list
[brp_j
].value
= 0;
1643 brp_list
[brp_j
].control
= 0;
1644 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1645 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1646 brp_list
[brp_j
].control
);
1647 if (retval
!= ERROR_OK
)
1649 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1650 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1651 brp_list
[brp_j
].value
);
1652 if (retval
!= ERROR_OK
)
1654 breakpoint
->linked_BRP
= 0;
1655 breakpoint
->set
= 0;
1659 int brp_i
= breakpoint
->set
- 1;
1660 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1661 LOG_DEBUG("Invalid BRP number in breakpoint");
1664 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1665 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1666 brp_list
[brp_i
].used
= 0;
1667 brp_list
[brp_i
].value
= 0;
1668 brp_list
[brp_i
].control
= 0;
1669 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1670 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1671 brp_list
[brp_i
].control
);
1672 if (retval
!= ERROR_OK
)
1674 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1675 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1676 brp_list
[brp_i
].value
);
1677 if (retval
!= ERROR_OK
)
1679 breakpoint
->set
= 0;
1683 /* restore original instruction (kept in target endianness) */
1684 if (breakpoint
->length
== 4) {
1685 retval
= target_write_memory(target
,
1686 breakpoint
->address
& 0xFFFFFFFE,
1687 4, 1, breakpoint
->orig_instr
);
1688 if (retval
!= ERROR_OK
)
1691 retval
= target_write_memory(target
,
1692 breakpoint
->address
& 0xFFFFFFFE,
1693 2, 1, breakpoint
->orig_instr
);
1694 if (retval
!= ERROR_OK
)
1698 breakpoint
->set
= 0;
1703 static int cortex_a_add_breakpoint(struct target
*target
,
1704 struct breakpoint
*breakpoint
)
1706 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1708 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1709 LOG_INFO("no hardware breakpoint available");
1710 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1713 if (breakpoint
->type
== BKPT_HARD
)
1714 cortex_a
->brp_num_available
--;
1716 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1719 static int cortex_a_add_context_breakpoint(struct target
*target
,
1720 struct breakpoint
*breakpoint
)
1722 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1724 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1725 LOG_INFO("no hardware breakpoint available");
1726 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1729 if (breakpoint
->type
== BKPT_HARD
)
1730 cortex_a
->brp_num_available
--;
1732 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1735 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1736 struct breakpoint
*breakpoint
)
1738 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1740 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1741 LOG_INFO("no hardware breakpoint available");
1742 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1745 if (breakpoint
->type
== BKPT_HARD
)
1746 cortex_a
->brp_num_available
--;
1748 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1752 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1754 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1757 /* It is perfectly possible to remove breakpoints while the target is running */
1758 if (target
->state
!= TARGET_HALTED
) {
1759 LOG_WARNING("target not halted");
1760 return ERROR_TARGET_NOT_HALTED
;
1764 if (breakpoint
->set
) {
1765 cortex_a_unset_breakpoint(target
, breakpoint
);
1766 if (breakpoint
->type
== BKPT_HARD
)
1767 cortex_a
->brp_num_available
++;
1775 * Cortex-A Reset functions
1778 static int cortex_a_assert_reset(struct target
*target
)
1780 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1784 /* FIXME when halt is requested, make it work somehow... */
1786 /* Issue some kind of warm reset. */
1787 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1788 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1789 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1790 /* REVISIT handle "pulls" cases, if there's
1791 * hardware that needs them to work.
1793 jtag_add_reset(0, 1);
1795 LOG_ERROR("%s: how to reset?", target_name(target
));
1799 /* registers are now invalid */
1800 register_cache_invalidate(armv7a
->arm
.core_cache
);
1802 target
->state
= TARGET_RESET
;
1807 static int cortex_a_deassert_reset(struct target
*target
)
1813 /* be certain SRST is off */
1814 jtag_add_reset(0, 0);
1816 retval
= cortex_a_poll(target
);
1817 if (retval
!= ERROR_OK
)
1820 if (target
->reset_halt
) {
1821 if (target
->state
!= TARGET_HALTED
) {
1822 LOG_WARNING("%s: ran after reset and before halt ...",
1823 target_name(target
));
1824 retval
= target_halt(target
);
1825 if (retval
!= ERROR_OK
)
1833 static int cortex_a_write_apb_ab_memory(struct target
*target
,
1834 uint32_t address
, uint32_t size
,
1835 uint32_t count
, const uint8_t *buffer
)
1837 /* write memory through APB-AP */
1839 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1840 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1841 struct arm
*arm
= &armv7a
->arm
;
1842 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1843 int total_bytes
= count
* size
;
1845 int start_byte
= address
& 0x3;
1846 int end_byte
= (address
+ total_bytes
) & 0x3;
1849 uint8_t *tmp_buff
= NULL
;
1852 LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count%" PRIu32
,
1853 address
, size
, count
);
1854 if (target
->state
!= TARGET_HALTED
) {
1855 LOG_WARNING("target not halted");
1856 return ERROR_TARGET_NOT_HALTED
;
1859 total_u32
= DIV_ROUND_UP((address
& 3) + total_bytes
, 4);
1861 /* Mark register R0 as dirty, as it will be used
1862 * for transferring the data.
1863 * It will be restored automatically when exiting
1866 reg
= arm_reg_current(arm
, 0);
1869 /* clear any abort */
1870 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
1871 if (retval
!= ERROR_OK
)
1874 /* This algorithm comes from either :
1875 * Cortex-A TRM Example 12-25
1876 * Cortex-R4 TRM Example 11-26
1877 * (slight differences)
1880 /* The algorithm only copies 32 bit words, so the buffer
1881 * should be expanded to include the words at either end.
1882 * The first and last words will be read first to avoid
1883 * corruption if needed.
1885 tmp_buff
= malloc(total_u32
* 4);
1887 if ((start_byte
!= 0) && (total_u32
> 1)) {
1888 /* First bytes not aligned - read the 32 bit word to avoid corrupting
1889 * the other bytes in the word.
1891 retval
= cortex_a_read_apb_ab_memory(target
, (address
& ~0x3), 4, 1, tmp_buff
);
1892 if (retval
!= ERROR_OK
)
1893 goto error_free_buff_w
;
1896 /* If end of write is not aligned, or the write is less than 4 bytes */
1897 if ((end_byte
!= 0) ||
1898 ((total_u32
== 1) && (total_bytes
!= 4))) {
1899 /* Read the last word to avoid corruption during 32 bit write */
1900 int mem_offset
= (total_u32
-1) * 4;
1901 retval
= cortex_a_read_apb_ab_memory(target
, (address
& ~0x3) + mem_offset
, 4, 1, &tmp_buff
[mem_offset
]);
1902 if (retval
!= ERROR_OK
)
1903 goto error_free_buff_w
;
1906 /* Copy the write buffer over the top of the temporary buffer */
1907 memcpy(&tmp_buff
[start_byte
], buffer
, total_bytes
);
1909 /* We now have a 32 bit aligned buffer that can be written */
1912 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1913 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1914 if (retval
!= ERROR_OK
)
1915 goto error_free_buff_w
;
1917 /* Set DTR mode to Fast (2) */
1918 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_FAST_MODE
;
1919 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1920 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1921 if (retval
!= ERROR_OK
)
1922 goto error_free_buff_w
;
1924 /* Copy the destination address into R0 */
1925 /* - pend an instruction MRC p14, 0, R0, c5, c0 */
1926 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1927 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
1928 if (retval
!= ERROR_OK
)
1929 goto error_unset_dtr_w
;
1930 /* Write address into DTRRX, which triggers previous instruction */
1931 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1932 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
& (~0x3));
1933 if (retval
!= ERROR_OK
)
1934 goto error_unset_dtr_w
;
1936 /* Write the data transfer instruction into the ITR
1937 * (STC p14, c5, [R0], 4)
1939 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1940 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
1941 if (retval
!= ERROR_OK
)
1942 goto error_unset_dtr_w
;
1945 retval
= mem_ap_sel_write_buf_noincr(swjdp
, armv7a
->debug_ap
,
1946 tmp_buff
, 4, total_u32
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
1947 if (retval
!= ERROR_OK
)
1948 goto error_unset_dtr_w
;
1951 /* Switch DTR mode back to non-blocking (0) */
1952 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
1953 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1954 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1955 if (retval
!= ERROR_OK
)
1956 goto error_unset_dtr_w
;
1958 /* Check for sticky abort flags in the DSCR */
1959 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1960 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1961 if (retval
!= ERROR_OK
)
1962 goto error_free_buff_w
;
1963 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
1964 /* Abort occurred - clear it and exit */
1965 LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32
, dscr
);
1966 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1967 armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
1968 goto error_free_buff_w
;
1976 /* Unset DTR mode */
1977 mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1978 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1979 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
1980 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1981 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1988 static int cortex_a_read_apb_ab_memory(struct target
*target
,
1989 uint32_t address
, uint32_t size
,
1990 uint32_t count
, uint8_t *buffer
)
1992 /* read memory through APB-AP */
1994 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1995 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1996 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1997 struct arm
*arm
= &armv7a
->arm
;
1998 int total_bytes
= count
* size
;
2000 int start_byte
= address
& 0x3;
2001 int end_byte
= (address
+ total_bytes
) & 0x3;
2004 uint8_t *tmp_buff
= NULL
;
2008 LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count%" PRIu32
,
2009 address
, size
, count
);
2010 if (target
->state
!= TARGET_HALTED
) {
2011 LOG_WARNING("target not halted");
2012 return ERROR_TARGET_NOT_HALTED
;
2015 total_u32
= DIV_ROUND_UP((address
& 3) + total_bytes
, 4);
2016 /* Mark register R0 as dirty, as it will be used
2017 * for transferring the data.
2018 * It will be restored automatically when exiting
2021 reg
= arm_reg_current(arm
, 0);
2024 /* clear any abort */
2026 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
2027 if (retval
!= ERROR_OK
)
2028 goto error_free_buff_r
;
2031 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2032 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2034 /* This algorithm comes from either :
2035 * Cortex-A TRM Example 12-24
2036 * Cortex-R4 TRM Example 11-25
2037 * (slight differences)
2040 /* Set DTR access mode to stall mode b01 */
2041 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_STALL_MODE
;
2042 retval
+= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2043 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
2045 /* Write R0 with value 'address' using write procedure for stall mode */
2046 /* - Write the address for read access into DTRRX */
2047 retval
+= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2048 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
& ~0x3);
2049 /* - Copy value from DTRRX to R0 using instruction mrc p14, 0, r0, c5, c0 */
2050 cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2052 /* Write the data transfer instruction (ldc p14, c5, [r0],4)
2053 * and the DTR mode setting to fast mode
2054 * in one combined write (since they are adjacent registers)
2057 target_buffer_set_u32(target
, u8buf_ptr
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2058 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_FAST_MODE
;
2059 target_buffer_set_u32(target
, u8buf_ptr
+ 4, dscr
);
2060 /* group the 2 access CPUDBG_ITR 0x84 and CPUDBG_DSCR 0x88 */
2061 retval
+= mem_ap_sel_write_buf(swjdp
, armv7a
->debug_ap
, u8buf_ptr
, 4, 2,
2062 armv7a
->debug_base
+ CPUDBG_ITR
);
2063 if (retval
!= ERROR_OK
)
2064 goto error_unset_dtr_r
;
2066 /* Optimize the read as much as we can, either way we read in a single pass */
2067 if ((start_byte
) || (end_byte
)) {
2068 /* The algorithm only copies 32 bit words, so the buffer
2069 * should be expanded to include the words at either end.
2070 * The first and last words will be read into a temp buffer
2071 * to avoid corruption
2073 tmp_buff
= malloc(total_u32
* 4);
2075 goto error_unset_dtr_r
;
2077 /* use the tmp buffer to read the entire data */
2078 u8buf_ptr
= tmp_buff
;
2080 /* address and read length are aligned so read directely into the passed buffer */
2083 /* Read the data - Each read of the DTRTX register causes the instruction to be reissued
2084 * Abort flags are sticky, so can be read at end of transactions
2086 * This data is read in aligned to 32 bit boundary.
2088 retval
= mem_ap_sel_read_buf_noincr(swjdp
, armv7a
->debug_ap
, u8buf_ptr
, 4, total_u32
,
2089 armv7a
->debug_base
+ CPUDBG_DTRTX
);
2090 if (retval
!= ERROR_OK
)
2091 goto error_unset_dtr_r
;
2093 /* set DTR access mode back to non blocking b00 */
2094 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
2095 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2096 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
2097 if (retval
!= ERROR_OK
)
2098 goto error_free_buff_r
;
2100 /* Wait for the final read instruction to finish */
2102 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2103 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2104 if (retval
!= ERROR_OK
)
2105 goto error_free_buff_r
;
2106 } while ((dscr
& DSCR_INSTR_COMP
) == 0);
2108 /* Check for sticky abort flags in the DSCR */
2109 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2110 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2111 if (retval
!= ERROR_OK
)
2112 goto error_free_buff_r
;
2113 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2114 /* Abort occurred - clear it and exit */
2115 LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32
, dscr
);
2116 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2117 armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
2118 goto error_free_buff_r
;
2121 /* check if we need to copy aligned data by applying any shift necessary */
2123 memcpy(buffer
, tmp_buff
+ start_byte
, total_bytes
);
2131 /* Unset DTR mode */
2132 mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2133 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2134 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
2135 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2136 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
2145 * Cortex-A Memory access
2147 * This is same Cortex M3 but we must also use the correct
2148 * ap number for every access.
2151 static int cortex_a_read_phys_memory(struct target
*target
,
2152 uint32_t address
, uint32_t size
,
2153 uint32_t count
, uint8_t *buffer
)
2155 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2156 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2157 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2158 uint8_t apsel
= swjdp
->apsel
;
2159 LOG_DEBUG("Reading memory at real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
,
2160 address
, size
, count
);
2162 if (count
&& buffer
) {
2164 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2166 /* read memory through AHB-AP */
2167 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2170 /* read memory through APB-AP */
2171 if (!armv7a
->is_armv7r
) {
2173 retval
= cortex_a_mmu_modify(target
, 0);
2174 if (retval
!= ERROR_OK
)
2177 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2183 static int cortex_a_read_memory(struct target
*target
, uint32_t address
,
2184 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2186 int mmu_enabled
= 0;
2187 uint32_t virt
, phys
;
2189 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2190 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2191 uint8_t apsel
= swjdp
->apsel
;
2193 /* cortex_a handles unaligned memory access */
2194 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2197 /* determine if MMU was enabled on target stop */
2198 if (!armv7a
->is_armv7r
) {
2199 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2200 if (retval
!= ERROR_OK
)
2204 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2207 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2208 if (retval
!= ERROR_OK
)
2211 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2215 retval
= cortex_a_read_phys_memory(target
, address
, size
,
2219 retval
= cortex_a_check_address(target
, address
);
2220 if (retval
!= ERROR_OK
)
2222 /* enable MMU as we could have disabled it for phys access */
2223 retval
= cortex_a_mmu_modify(target
, 1);
2224 if (retval
!= ERROR_OK
)
2227 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2232 static int cortex_a_write_phys_memory(struct target
*target
,
2233 uint32_t address
, uint32_t size
,
2234 uint32_t count
, const uint8_t *buffer
)
2236 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2237 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2238 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2239 uint8_t apsel
= swjdp
->apsel
;
2241 LOG_DEBUG("Writing memory to real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2244 if (count
&& buffer
) {
2246 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2248 /* write memory through AHB-AP */
2249 retval
= mem_ap_sel_write_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2252 /* write memory through APB-AP */
2253 if (!armv7a
->is_armv7r
) {
2254 retval
= cortex_a_mmu_modify(target
, 0);
2255 if (retval
!= ERROR_OK
)
2258 return cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2263 /* REVISIT this op is generic ARMv7-A/R stuff */
2264 if (retval
== ERROR_OK
&& target
->state
== TARGET_HALTED
) {
2265 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
2267 retval
= dpm
->prepare(dpm
);
2268 if (retval
!= ERROR_OK
)
2271 /* The Cache handling will NOT work with MMU active, the
2272 * wrong addresses will be invalidated!
2274 * For both ICache and DCache, walk all cache lines in the
2275 * address range. Cortex-A has fixed 64 byte line length.
2277 * REVISIT per ARMv7, these may trigger watchpoints ...
2280 /* invalidate I-Cache */
2281 if (armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
) {
2282 /* ICIMVAU - Invalidate Cache single entry
2284 * MCR p15, 0, r0, c7, c5, 1
2286 for (uint32_t cacheline
= 0;
2287 cacheline
< size
* count
;
2289 retval
= dpm
->instr_write_data_r0(dpm
,
2290 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
2291 address
+ cacheline
);
2292 if (retval
!= ERROR_OK
)
2297 /* invalidate D-Cache */
2298 if (armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
) {
2299 /* DCIMVAC - Invalidate data Cache line
2301 * MCR p15, 0, r0, c7, c6, 1
2303 for (uint32_t cacheline
= 0;
2304 cacheline
< size
* count
;
2306 retval
= dpm
->instr_write_data_r0(dpm
,
2307 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
2308 address
+ cacheline
);
2309 if (retval
!= ERROR_OK
)
2314 /* (void) */ dpm
->finish(dpm
);
2320 static int cortex_a_write_memory(struct target
*target
, uint32_t address
,
2321 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2323 int mmu_enabled
= 0;
2324 uint32_t virt
, phys
;
2326 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2327 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2328 uint8_t apsel
= swjdp
->apsel
;
2330 /* cortex_a handles unaligned memory access */
2331 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2334 /* determine if MMU was enabled on target stop */
2335 if (!armv7a
->is_armv7r
) {
2336 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2337 if (retval
!= ERROR_OK
)
2341 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2342 LOG_DEBUG("Writing memory to address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
, size
,
2346 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2347 if (retval
!= ERROR_OK
)
2350 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2355 retval
= cortex_a_write_phys_memory(target
, address
, size
,
2359 retval
= cortex_a_check_address(target
, address
);
2360 if (retval
!= ERROR_OK
)
2362 /* enable MMU as we could have disabled it for phys access */
2363 retval
= cortex_a_mmu_modify(target
, 1);
2364 if (retval
!= ERROR_OK
)
2367 retval
= cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2372 static int cortex_a_handle_target_request(void *priv
)
2374 struct target
*target
= priv
;
2375 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2376 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2379 if (!target_was_examined(target
))
2381 if (!target
->dbg_msg_enabled
)
2384 if (target
->state
== TARGET_RUNNING
) {
2387 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2388 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2390 /* check if we have data */
2391 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2392 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2393 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2394 if (retval
== ERROR_OK
) {
2395 target_request(target
, request
);
2396 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2397 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2406 * Cortex-A target information and configuration
2409 static int cortex_a_examine_first(struct target
*target
)
2411 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2412 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2413 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2415 int retval
= ERROR_OK
;
2416 uint32_t didr
, ctypr
, ttypr
, cpuid
, dbg_osreg
;
2418 /* We do one extra read to ensure DAP is configured,
2419 * we call ahbap_debugport_init(swjdp) instead
2421 retval
= ahbap_debugport_init(swjdp
);
2422 if (retval
!= ERROR_OK
)
2425 /* Search for the APB-AB - it is needed for access to debug registers */
2426 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2427 if (retval
!= ERROR_OK
) {
2428 LOG_ERROR("Could not find APB-AP for debug access");
2431 /* Search for the AHB-AB */
2432 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
2433 if (retval
!= ERROR_OK
) {
2434 /* AHB-AP not found - use APB-AP */
2435 LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access");
2436 armv7a
->memory_ap_available
= false;
2438 armv7a
->memory_ap_available
= true;
2442 if (!target
->dbgbase_set
) {
2444 /* Get ROM Table base */
2446 int32_t coreidx
= target
->coreid
;
2447 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2449 retval
= dap_get_debugbase(swjdp
, 1, &dbgbase
, &apid
);
2450 if (retval
!= ERROR_OK
)
2452 /* Lookup 0x15 -- Processor DAP */
2453 retval
= dap_lookup_cs_component(swjdp
, 1, dbgbase
, 0x15,
2454 &armv7a
->debug_base
, &coreidx
);
2455 if (retval
!= ERROR_OK
)
2457 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2458 coreidx
, armv7a
->debug_base
);
2460 armv7a
->debug_base
= target
->dbgbase
;
2462 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2463 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2464 if (retval
!= ERROR_OK
)
2467 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2468 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2469 if (retval
!= ERROR_OK
) {
2470 LOG_DEBUG("Examine %s failed", "CPUID");
2474 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2475 armv7a
->debug_base
+ CPUDBG_CTYPR
, &ctypr
);
2476 if (retval
!= ERROR_OK
) {
2477 LOG_DEBUG("Examine %s failed", "CTYPR");
2481 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2482 armv7a
->debug_base
+ CPUDBG_TTYPR
, &ttypr
);
2483 if (retval
!= ERROR_OK
) {
2484 LOG_DEBUG("Examine %s failed", "TTYPR");
2488 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2489 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2490 if (retval
!= ERROR_OK
) {
2491 LOG_DEBUG("Examine %s failed", "DIDR");
2495 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
2496 LOG_DEBUG("ctypr = 0x%08" PRIx32
, ctypr
);
2497 LOG_DEBUG("ttypr = 0x%08" PRIx32
, ttypr
);
2498 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
2500 cortex_a
->cpuid
= cpuid
;
2501 cortex_a
->ctypr
= ctypr
;
2502 cortex_a
->ttypr
= ttypr
;
2503 cortex_a
->didr
= didr
;
2505 /* Unlocking the debug registers */
2506 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
2507 CORTEX_A15_PARTNUM
) {
2509 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2510 armv7a
->debug_base
+ CPUDBG_OSLAR
,
2513 if (retval
!= ERROR_OK
)
2517 /* Unlocking the debug registers */
2518 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
2519 CORTEX_A7_PARTNUM
) {
2521 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2522 armv7a
->debug_base
+ CPUDBG_OSLAR
,
2525 if (retval
!= ERROR_OK
)
2529 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2530 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
2532 if (retval
!= ERROR_OK
)
2535 LOG_DEBUG("target->coreid %d DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
2537 armv7a
->arm
.core_type
= ARM_MODE_MON
;
2538 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
2539 if (retval
!= ERROR_OK
)
2542 /* Setup Breakpoint Register Pairs */
2543 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
2544 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
2545 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
2546 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
2547 /* cortex_a->brb_enabled = ????; */
2548 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
2549 cortex_a
->brp_list
[i
].used
= 0;
2550 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
2551 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
2553 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
2554 cortex_a
->brp_list
[i
].value
= 0;
2555 cortex_a
->brp_list
[i
].control
= 0;
2556 cortex_a
->brp_list
[i
].BRPn
= i
;
2559 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
2561 target_set_examined(target
);
2565 static int cortex_a_examine(struct target
*target
)
2567 int retval
= ERROR_OK
;
2569 /* don't re-probe hardware after each reset */
2570 if (!target_was_examined(target
))
2571 retval
= cortex_a_examine_first(target
);
2573 /* Configure core debug access */
2574 if (retval
== ERROR_OK
)
2575 retval
= cortex_a_init_debug_access(target
);
2581 * Cortex-A target creation and initialization
2584 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
2585 struct target
*target
)
2587 /* examine_first() does a bunch of this */
2591 static int cortex_a_init_arch_info(struct target
*target
,
2592 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
2594 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2595 struct adiv5_dap
*dap
= &armv7a
->dap
;
2597 armv7a
->arm
.dap
= dap
;
2599 /* Setup struct cortex_a_common */
2600 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
2601 /* tap has no dap initialized */
2603 armv7a
->arm
.dap
= dap
;
2604 /* Setup struct cortex_a_common */
2606 /* prepare JTAG information for the new target */
2607 cortex_a
->jtag_info
.tap
= tap
;
2608 cortex_a
->jtag_info
.scann_size
= 4;
2610 /* Leave (only) generic DAP stuff for debugport_init() */
2611 dap
->jtag_info
= &cortex_a
->jtag_info
;
2613 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
2614 dap
->tar_autoincr_block
= (1 << 10);
2615 dap
->memaccess_tck
= 80;
2618 armv7a
->arm
.dap
= tap
->dap
;
2620 cortex_a
->fast_reg_read
= 0;
2622 /* register arch-specific functions */
2623 armv7a
->examine_debug_reason
= NULL
;
2625 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
2627 armv7a
->pre_restore_context
= NULL
;
2629 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
2632 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
2634 /* REVISIT v7a setup should be in a v7a-specific routine */
2635 armv7a_init_arch_info(target
, armv7a
);
2636 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
2641 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
2643 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
2645 cortex_a
->armv7a_common
.is_armv7r
= false;
2647 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
2650 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
2652 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
2654 cortex_a
->armv7a_common
.is_armv7r
= true;
2656 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
2660 static int cortex_a_mmu(struct target
*target
, int *enabled
)
2662 if (target
->state
!= TARGET_HALTED
) {
2663 LOG_ERROR("%s: target not halted", __func__
);
2664 return ERROR_TARGET_INVALID
;
2667 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
2671 static int cortex_a_virt2phys(struct target
*target
,
2672 uint32_t virt
, uint32_t *phys
)
2674 int retval
= ERROR_FAIL
;
2675 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2676 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2677 uint8_t apsel
= swjdp
->apsel
;
2678 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2680 retval
= armv7a_mmu_translate_va(target
,
2682 if (retval
!= ERROR_OK
)
2685 } else {/* use this method if armv7a->memory_ap not selected
2686 * mmu must be enable in order to get a correct translation */
2687 retval
= cortex_a_mmu_modify(target
, 1);
2688 if (retval
!= ERROR_OK
)
2690 retval
= armv7a_mmu_translate_va_pa(target
, virt
, phys
, 1);
2696 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
2698 struct target
*target
= get_current_target(CMD_CTX
);
2699 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2701 return armv7a_handle_cache_info_command(CMD_CTX
,
2702 &armv7a
->armv7a_mmu
.armv7a_cache
);
2706 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
2708 struct target
*target
= get_current_target(CMD_CTX
);
2709 if (!target_was_examined(target
)) {
2710 LOG_ERROR("target not examined yet");
2714 return cortex_a_init_debug_access(target
);
2716 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
2718 struct target
*target
= get_current_target(CMD_CTX
);
2719 /* check target is an smp target */
2720 struct target_list
*head
;
2721 struct target
*curr
;
2722 head
= target
->head
;
2724 if (head
!= (struct target_list
*)NULL
) {
2725 while (head
!= (struct target_list
*)NULL
) {
2726 curr
= head
->target
;
2730 /* fixes the target display to the debugger */
2731 target
->gdb_service
->target
= target
;
2736 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
2738 struct target
*target
= get_current_target(CMD_CTX
);
2739 struct target_list
*head
;
2740 struct target
*curr
;
2741 head
= target
->head
;
2742 if (head
!= (struct target_list
*)NULL
) {
2744 while (head
!= (struct target_list
*)NULL
) {
2745 curr
= head
->target
;
2753 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
2755 struct target
*target
= get_current_target(CMD_CTX
);
2756 int retval
= ERROR_OK
;
2757 struct target_list
*head
;
2758 head
= target
->head
;
2759 if (head
!= (struct target_list
*)NULL
) {
2760 if (CMD_ARGC
== 1) {
2762 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
2763 if (ERROR_OK
!= retval
)
2765 target
->gdb_service
->core
[1] = coreid
;
2768 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
2769 , target
->gdb_service
->core
[1]);
2774 static const struct command_registration cortex_a_exec_command_handlers
[] = {
2776 .name
= "cache_info",
2777 .handler
= cortex_a_handle_cache_info_command
,
2778 .mode
= COMMAND_EXEC
,
2779 .help
= "display information about target caches",
2784 .handler
= cortex_a_handle_dbginit_command
,
2785 .mode
= COMMAND_EXEC
,
2786 .help
= "Initialize core debug",
2789 { .name
= "smp_off",
2790 .handler
= cortex_a_handle_smp_off_command
,
2791 .mode
= COMMAND_EXEC
,
2792 .help
= "Stop smp handling",
2796 .handler
= cortex_a_handle_smp_on_command
,
2797 .mode
= COMMAND_EXEC
,
2798 .help
= "Restart smp handling",
2803 .handler
= cortex_a_handle_smp_gdb_command
,
2804 .mode
= COMMAND_EXEC
,
2805 .help
= "display/fix current core played to gdb",
2810 COMMAND_REGISTRATION_DONE
2812 static const struct command_registration cortex_a_command_handlers
[] = {
2814 .chain
= arm_command_handlers
,
2817 .chain
= armv7a_command_handlers
,
2821 .mode
= COMMAND_ANY
,
2822 .help
= "Cortex-A command group",
2824 .chain
= cortex_a_exec_command_handlers
,
2826 COMMAND_REGISTRATION_DONE
2829 struct target_type cortexa_target
= {
2831 .deprecated_name
= "cortex_a8",
2833 .poll
= cortex_a_poll
,
2834 .arch_state
= armv7a_arch_state
,
2836 .halt
= cortex_a_halt
,
2837 .resume
= cortex_a_resume
,
2838 .step
= cortex_a_step
,
2840 .assert_reset
= cortex_a_assert_reset
,
2841 .deassert_reset
= cortex_a_deassert_reset
,
2843 /* REVISIT allow exporting VFP3 registers ... */
2844 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
2846 .read_memory
= cortex_a_read_memory
,
2847 .write_memory
= cortex_a_write_memory
,
2849 .checksum_memory
= arm_checksum_memory
,
2850 .blank_check_memory
= arm_blank_check_memory
,
2852 .run_algorithm
= armv4_5_run_algorithm
,
2854 .add_breakpoint
= cortex_a_add_breakpoint
,
2855 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
2856 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
2857 .remove_breakpoint
= cortex_a_remove_breakpoint
,
2858 .add_watchpoint
= NULL
,
2859 .remove_watchpoint
= NULL
,
2861 .commands
= cortex_a_command_handlers
,
2862 .target_create
= cortex_a_target_create
,
2863 .init_target
= cortex_a_init_target
,
2864 .examine
= cortex_a_examine
,
2866 .read_phys_memory
= cortex_a_read_phys_memory
,
2867 .write_phys_memory
= cortex_a_write_phys_memory
,
2868 .mmu
= cortex_a_mmu
,
2869 .virt2phys
= cortex_a_virt2phys
,
2872 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
2874 .name
= "cache_info",
2875 .handler
= cortex_a_handle_cache_info_command
,
2876 .mode
= COMMAND_EXEC
,
2877 .help
= "display information about target caches",
2882 .handler
= cortex_a_handle_dbginit_command
,
2883 .mode
= COMMAND_EXEC
,
2884 .help
= "Initialize core debug",
2888 COMMAND_REGISTRATION_DONE
2890 static const struct command_registration cortex_r4_command_handlers
[] = {
2892 .chain
= arm_command_handlers
,
2895 .chain
= armv7a_command_handlers
,
2898 .name
= "cortex_r4",
2899 .mode
= COMMAND_ANY
,
2900 .help
= "Cortex-R4 command group",
2902 .chain
= cortex_r4_exec_command_handlers
,
2904 COMMAND_REGISTRATION_DONE
2907 struct target_type cortexr4_target
= {
2908 .name
= "cortex_r4",
2910 .poll
= cortex_a_poll
,
2911 .arch_state
= armv7a_arch_state
,
2913 .halt
= cortex_a_halt
,
2914 .resume
= cortex_a_resume
,
2915 .step
= cortex_a_step
,
2917 .assert_reset
= cortex_a_assert_reset
,
2918 .deassert_reset
= cortex_a_deassert_reset
,
2920 /* REVISIT allow exporting VFP3 registers ... */
2921 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
2923 .read_memory
= cortex_a_read_memory
,
2924 .write_memory
= cortex_a_write_memory
,
2926 .checksum_memory
= arm_checksum_memory
,
2927 .blank_check_memory
= arm_blank_check_memory
,
2929 .run_algorithm
= armv4_5_run_algorithm
,
2931 .add_breakpoint
= cortex_a_add_breakpoint
,
2932 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
2933 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
2934 .remove_breakpoint
= cortex_a_remove_breakpoint
,
2935 .add_watchpoint
= NULL
,
2936 .remove_watchpoint
= NULL
,
2938 .commands
= cortex_r4_command_handlers
,
2939 .target_create
= cortex_r4_target_create
,
2940 .init_target
= cortex_a_init_target
,
2941 .examine
= cortex_a_examine
,