1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program; if not, write to the *
38 * Free Software Foundation, Inc., *
39 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
41 * Cortex-A8(tm) TRM, ARM DDI 0344H *
42 * Cortex-A9(tm) TRM, ARM DDI 0407F *
43 * Cortex-A4(tm) TRM, ARM DDI 0363E *
44 * Cortex-A15(tm)TRM, ARM DDI 0438C *
46 ***************************************************************************/
52 #include "breakpoints.h"
55 #include "target_request.h"
56 #include "target_type.h"
57 #include "arm_opcodes.h"
58 #include <helper/time_support.h>
60 static int cortex_a_poll(struct target
*target
);
61 static int cortex_a_debug_entry(struct target
*target
);
62 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
63 static int cortex_a_set_breakpoint(struct target
*target
,
64 struct breakpoint
*breakpoint
, uint8_t matchmode
);
65 static int cortex_a_set_context_breakpoint(struct target
*target
,
66 struct breakpoint
*breakpoint
, uint8_t matchmode
);
67 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
68 struct breakpoint
*breakpoint
);
69 static int cortex_a_unset_breakpoint(struct target
*target
,
70 struct breakpoint
*breakpoint
);
71 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
72 uint32_t *value
, int regnum
);
73 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
74 uint32_t value
, int regnum
);
75 static int cortex_a_mmu(struct target
*target
, int *enabled
);
76 static int cortex_a_virt2phys(struct target
*target
,
77 uint32_t virt
, uint32_t *phys
);
78 static int cortex_a_read_apb_ab_memory(struct target
*target
,
79 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
82 /* restore cp15_control_reg at resume */
83 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
85 int retval
= ERROR_OK
;
86 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
87 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
89 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
90 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
91 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
92 retval
= armv7a
->arm
.mcr(target
, 15,
95 cortex_a
->cp15_control_reg
);
100 /* check address before cortex_a_apb read write access with mmu on
101 * remove apb predictible data abort */
102 static int cortex_a_check_address(struct target
*target
, uint32_t address
)
104 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
105 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
106 uint32_t os_border
= armv7a
->armv7a_mmu
.os_border
;
107 if ((address
< os_border
) &&
108 (armv7a
->arm
.core_mode
== ARM_MODE_SVC
)) {
109 LOG_ERROR("%" PRIx32
" access in userspace and target in supervisor", address
);
112 if ((address
>= os_border
) &&
113 (cortex_a
->curr_mode
!= ARM_MODE_SVC
)) {
114 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
115 cortex_a
->curr_mode
= ARM_MODE_SVC
;
116 LOG_INFO("%" PRIx32
" access in kernel space and target not in supervisor",
120 if ((address
< os_border
) &&
121 (cortex_a
->curr_mode
== ARM_MODE_SVC
)) {
122 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
123 cortex_a
->curr_mode
= ARM_MODE_ANY
;
127 /* modify cp15_control_reg in order to enable or disable mmu for :
128 * - virt2phys address conversion
129 * - read or write memory in phys or virt address */
130 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
132 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
133 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
134 int retval
= ERROR_OK
;
136 /* if mmu enabled at target stop and mmu not enable */
137 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
138 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
141 if (!(cortex_a
->cp15_control_reg_curr
& 0x1U
)) {
142 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
143 retval
= armv7a
->arm
.mcr(target
, 15,
146 cortex_a
->cp15_control_reg_curr
);
149 if (cortex_a
->cp15_control_reg_curr
& 0x4U
) {
150 /* data cache is active */
151 cortex_a
->cp15_control_reg_curr
&= ~0x4U
;
152 /* flush data cache armv7 function to be called */
153 if (armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache
)
154 armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache(target
);
156 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
)) {
157 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
158 retval
= armv7a
->arm
.mcr(target
, 15,
161 cortex_a
->cp15_control_reg_curr
);
168 * Cortex-A Basic debug access, very low level assumes state is saved
170 static int cortex_a8_init_debug_access(struct target
*target
)
172 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
173 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
178 /* Unlocking the debug registers for modification
179 * The debugport might be uninitialised so try twice */
180 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
181 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
182 if (retval
!= ERROR_OK
) {
184 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
185 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
186 if (retval
== ERROR_OK
)
188 "Locking debug access failed on first, but succeeded on second try.");
195 * Cortex-A Basic debug access, very low level assumes state is saved
197 static int cortex_a_init_debug_access(struct target
*target
)
199 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
200 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
203 uint32_t cortex_part_num
;
204 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
207 cortex_part_num
= (cortex_a
->cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >>
208 CORTEX_A_MIDR_PARTNUM_SHIFT
;
210 switch (cortex_part_num
) {
211 case CORTEX_A7_PARTNUM
:
212 case CORTEX_A15_PARTNUM
:
213 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
214 armv7a
->debug_base
+ CPUDBG_OSLSR
,
216 if (retval
!= ERROR_OK
)
219 LOG_DEBUG("DBGOSLSR 0x%" PRIx32
, dbg_osreg
);
221 if (dbg_osreg
& CPUDBG_OSLAR_LK_MASK
)
222 /* Unlocking the DEBUG OS registers for modification */
223 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
224 armv7a
->debug_base
+ CPUDBG_OSLAR
,
228 case CORTEX_A8_PARTNUM
:
229 case CORTEX_A9_PARTNUM
:
231 retval
= cortex_a8_init_debug_access(target
);
234 if (retval
!= ERROR_OK
)
236 /* Clear Sticky Power Down status Bit in PRSR to enable access to
237 the registers in the Core Power Domain */
238 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
239 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
240 LOG_DEBUG("target->coreid %d DBGPRSR 0x%x ", target
->coreid
, dbg_osreg
);
242 if (retval
!= ERROR_OK
)
245 /* Enabling of instruction execution in debug mode is done in debug_entry code */
247 /* Resync breakpoint registers */
249 /* Since this is likely called from init or reset, update target state information*/
250 return cortex_a_poll(target
);
253 /* To reduce needless round-trips, pass in a pointer to the current
254 * DSCR value. Initialize it to zero if you just need to know the
255 * value on return from this function; or DSCR_INSTR_COMP if you
256 * happen to know that no instruction is pending.
258 static int cortex_a_exec_opcode(struct target
*target
,
259 uint32_t opcode
, uint32_t *dscr_p
)
263 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
264 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
266 dscr
= dscr_p
? *dscr_p
: 0;
268 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
270 /* Wait for InstrCompl bit to be set */
271 long long then
= timeval_ms();
272 while ((dscr
& DSCR_INSTR_COMP
) == 0) {
273 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
274 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
275 if (retval
!= ERROR_OK
) {
276 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32
, opcode
);
279 if (timeval_ms() > then
+ 1000) {
280 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
285 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
286 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
287 if (retval
!= ERROR_OK
)
292 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
293 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
294 if (retval
!= ERROR_OK
) {
295 LOG_ERROR("Could not read DSCR register");
298 if (timeval_ms() > then
+ 1000) {
299 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
302 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
310 /**************************************************************************
311 Read core register with very few exec_opcode, fast but needs work_area.
312 This can cause problems with MMU active.
313 **************************************************************************/
314 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
317 int retval
= ERROR_OK
;
318 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
319 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
321 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
322 if (retval
!= ERROR_OK
)
324 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
325 if (retval
!= ERROR_OK
)
327 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
328 if (retval
!= ERROR_OK
)
331 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
,
332 (uint8_t *)(®file
[1]), 4, 15, address
);
337 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
338 uint32_t *value
, int regnum
)
340 int retval
= ERROR_OK
;
341 uint8_t reg
= regnum
&0xFF;
343 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
344 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
350 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
351 retval
= cortex_a_exec_opcode(target
,
352 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
354 if (retval
!= ERROR_OK
)
356 } else if (reg
== 15) {
357 /* "MOV r0, r15"; then move r0 to DCCTX */
358 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
359 if (retval
!= ERROR_OK
)
361 retval
= cortex_a_exec_opcode(target
,
362 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
364 if (retval
!= ERROR_OK
)
367 /* "MRS r0, CPSR" or "MRS r0, SPSR"
368 * then move r0 to DCCTX
370 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
371 if (retval
!= ERROR_OK
)
373 retval
= cortex_a_exec_opcode(target
,
374 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
376 if (retval
!= ERROR_OK
)
380 /* Wait for DTRRXfull then read DTRRTX */
381 long long then
= timeval_ms();
382 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
383 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
384 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
385 if (retval
!= ERROR_OK
)
387 if (timeval_ms() > then
+ 1000) {
388 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
393 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
394 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
395 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
400 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
401 uint32_t value
, int regnum
)
403 int retval
= ERROR_OK
;
404 uint8_t Rd
= regnum
&0xFF;
406 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
407 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
409 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
411 /* Check that DCCRX is not full */
412 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
413 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
414 if (retval
!= ERROR_OK
)
416 if (dscr
& DSCR_DTR_RX_FULL
) {
417 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
418 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
419 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
421 if (retval
!= ERROR_OK
)
428 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
429 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
430 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
431 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
432 if (retval
!= ERROR_OK
)
436 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
437 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
440 if (retval
!= ERROR_OK
)
442 } else if (Rd
== 15) {
443 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
446 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
448 if (retval
!= ERROR_OK
)
450 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
451 if (retval
!= ERROR_OK
)
454 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
455 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
457 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
459 if (retval
!= ERROR_OK
)
461 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
463 if (retval
!= ERROR_OK
)
466 /* "Prefetch flush" after modifying execution status in CPSR */
468 retval
= cortex_a_exec_opcode(target
,
469 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
471 if (retval
!= ERROR_OK
)
479 /* Write to memory mapped registers directly with no cache or mmu handling */
480 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
485 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
486 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
488 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, address
, value
);
494 * Cortex-A implementation of Debug Programmer's Model
496 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
497 * so there's no need to poll for it before executing an instruction.
499 * NOTE that in several of these cases the "stall" mode might be useful.
500 * It'd let us queue a few operations together... prepare/finish might
501 * be the places to enable/disable that mode.
504 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
506 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
509 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
511 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
512 return mem_ap_sel_write_u32(a
->armv7a_common
.arm
.dap
,
513 a
->armv7a_common
.debug_ap
, a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
516 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
519 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
520 uint32_t dscr
= DSCR_INSTR_COMP
;
526 /* Wait for DTRRXfull */
527 long long then
= timeval_ms();
528 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
529 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
530 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
532 if (retval
!= ERROR_OK
)
534 if (timeval_ms() > then
+ 1000) {
535 LOG_ERROR("Timeout waiting for read dcc");
540 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
541 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
542 if (retval
!= ERROR_OK
)
544 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
552 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
554 struct cortex_a_common
*a
= dpm_to_a(dpm
);
555 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
559 /* set up invariant: INSTR_COMP is set after ever DPM operation */
560 long long then
= timeval_ms();
562 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
563 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
565 if (retval
!= ERROR_OK
)
567 if ((dscr
& DSCR_INSTR_COMP
) != 0)
569 if (timeval_ms() > then
+ 1000) {
570 LOG_ERROR("Timeout waiting for dpm prepare");
575 /* this "should never happen" ... */
576 if (dscr
& DSCR_DTR_RX_FULL
) {
577 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
579 retval
= cortex_a_exec_opcode(
580 a
->armv7a_common
.arm
.target
,
581 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
583 if (retval
!= ERROR_OK
)
590 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
592 /* REVISIT what could be done here? */
596 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
597 uint32_t opcode
, uint32_t data
)
599 struct cortex_a_common
*a
= dpm_to_a(dpm
);
601 uint32_t dscr
= DSCR_INSTR_COMP
;
603 retval
= cortex_a_write_dcc(a
, data
);
604 if (retval
!= ERROR_OK
)
607 return cortex_a_exec_opcode(
608 a
->armv7a_common
.arm
.target
,
613 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
614 uint32_t opcode
, uint32_t data
)
616 struct cortex_a_common
*a
= dpm_to_a(dpm
);
617 uint32_t dscr
= DSCR_INSTR_COMP
;
620 retval
= cortex_a_write_dcc(a
, data
);
621 if (retval
!= ERROR_OK
)
624 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
625 retval
= cortex_a_exec_opcode(
626 a
->armv7a_common
.arm
.target
,
627 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
629 if (retval
!= ERROR_OK
)
632 /* then the opcode, taking data from R0 */
633 retval
= cortex_a_exec_opcode(
634 a
->armv7a_common
.arm
.target
,
641 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
643 struct target
*target
= dpm
->arm
->target
;
644 uint32_t dscr
= DSCR_INSTR_COMP
;
646 /* "Prefetch flush" after modifying execution status in CPSR */
647 return cortex_a_exec_opcode(target
,
648 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
652 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
653 uint32_t opcode
, uint32_t *data
)
655 struct cortex_a_common
*a
= dpm_to_a(dpm
);
657 uint32_t dscr
= DSCR_INSTR_COMP
;
659 /* the opcode, writing data to DCC */
660 retval
= cortex_a_exec_opcode(
661 a
->armv7a_common
.arm
.target
,
664 if (retval
!= ERROR_OK
)
667 return cortex_a_read_dcc(a
, data
, &dscr
);
671 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
672 uint32_t opcode
, uint32_t *data
)
674 struct cortex_a_common
*a
= dpm_to_a(dpm
);
675 uint32_t dscr
= DSCR_INSTR_COMP
;
678 /* the opcode, writing data to R0 */
679 retval
= cortex_a_exec_opcode(
680 a
->armv7a_common
.arm
.target
,
683 if (retval
!= ERROR_OK
)
686 /* write R0 to DCC */
687 retval
= cortex_a_exec_opcode(
688 a
->armv7a_common
.arm
.target
,
689 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
691 if (retval
!= ERROR_OK
)
694 return cortex_a_read_dcc(a
, data
, &dscr
);
697 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
698 uint32_t addr
, uint32_t control
)
700 struct cortex_a_common
*a
= dpm_to_a(dpm
);
701 uint32_t vr
= a
->armv7a_common
.debug_base
;
702 uint32_t cr
= a
->armv7a_common
.debug_base
;
706 case 0 ... 15: /* breakpoints */
707 vr
+= CPUDBG_BVR_BASE
;
708 cr
+= CPUDBG_BCR_BASE
;
710 case 16 ... 31: /* watchpoints */
711 vr
+= CPUDBG_WVR_BASE
;
712 cr
+= CPUDBG_WCR_BASE
;
721 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
722 (unsigned) vr
, (unsigned) cr
);
724 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
726 if (retval
!= ERROR_OK
)
728 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
733 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
735 struct cortex_a_common
*a
= dpm_to_a(dpm
);
740 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
743 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
751 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
753 /* clear control register */
754 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
757 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
759 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
762 dpm
->arm
= &a
->armv7a_common
.arm
;
765 dpm
->prepare
= cortex_a_dpm_prepare
;
766 dpm
->finish
= cortex_a_dpm_finish
;
768 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
769 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
770 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
772 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
773 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
775 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
776 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
778 retval
= arm_dpm_setup(dpm
);
779 if (retval
== ERROR_OK
)
780 retval
= arm_dpm_initialize(dpm
);
784 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
786 struct target_list
*head
;
790 while (head
!= (struct target_list
*)NULL
) {
792 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
798 static int cortex_a_halt(struct target
*target
);
800 static int cortex_a_halt_smp(struct target
*target
)
803 struct target_list
*head
;
806 while (head
!= (struct target_list
*)NULL
) {
808 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
809 retval
+= cortex_a_halt(curr
);
815 static int update_halt_gdb(struct target
*target
)
818 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
819 target
->gdb_service
->target
= target
;
820 target
->gdb_service
->core
[0] = target
->coreid
;
821 retval
+= cortex_a_halt_smp(target
);
827 * Cortex-A Run control
830 static int cortex_a_poll(struct target
*target
)
832 int retval
= ERROR_OK
;
834 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
835 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
836 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
837 enum target_state prev_target_state
= target
->state
;
838 /* toggle to another core is done by gdb as follow */
839 /* maint packet J core_id */
841 /* the next polling trigger an halt event sent to gdb */
842 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
843 (target
->gdb_service
) &&
844 (target
->gdb_service
->target
== NULL
)) {
845 target
->gdb_service
->target
=
846 get_cortex_a(target
, target
->gdb_service
->core
[1]);
847 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
850 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
851 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
852 if (retval
!= ERROR_OK
)
854 cortex_a
->cpudbg_dscr
= dscr
;
856 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
857 if (prev_target_state
!= TARGET_HALTED
) {
858 /* We have a halting debug event */
859 LOG_DEBUG("Target halted");
860 target
->state
= TARGET_HALTED
;
861 if ((prev_target_state
== TARGET_RUNNING
)
862 || (prev_target_state
== TARGET_UNKNOWN
)
863 || (prev_target_state
== TARGET_RESET
)) {
864 retval
= cortex_a_debug_entry(target
);
865 if (retval
!= ERROR_OK
)
868 retval
= update_halt_gdb(target
);
869 if (retval
!= ERROR_OK
)
872 target_call_event_callbacks(target
,
873 TARGET_EVENT_HALTED
);
875 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
878 retval
= cortex_a_debug_entry(target
);
879 if (retval
!= ERROR_OK
)
882 retval
= update_halt_gdb(target
);
883 if (retval
!= ERROR_OK
)
887 target_call_event_callbacks(target
,
888 TARGET_EVENT_DEBUG_HALTED
);
891 } else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
892 target
->state
= TARGET_RUNNING
;
894 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
895 target
->state
= TARGET_UNKNOWN
;
901 static int cortex_a_halt(struct target
*target
)
903 int retval
= ERROR_OK
;
905 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
906 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
909 * Tell the core to be halted by writing DRCR with 0x1
910 * and then wait for the core to be halted.
912 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
913 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
914 if (retval
!= ERROR_OK
)
918 * enter halting debug mode
920 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
921 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
922 if (retval
!= ERROR_OK
)
925 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
926 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
927 if (retval
!= ERROR_OK
)
930 long long then
= timeval_ms();
932 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
933 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
934 if (retval
!= ERROR_OK
)
936 if ((dscr
& DSCR_CORE_HALTED
) != 0)
938 if (timeval_ms() > then
+ 1000) {
939 LOG_ERROR("Timeout waiting for halt");
944 target
->debug_reason
= DBG_REASON_DBGRQ
;
949 static int cortex_a_internal_restore(struct target
*target
, int current
,
950 uint32_t *address
, int handle_breakpoints
, int debug_execution
)
952 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
953 struct arm
*arm
= &armv7a
->arm
;
957 if (!debug_execution
)
958 target_free_all_working_areas(target
);
961 if (debug_execution
) {
962 /* Disable interrupts */
963 /* We disable interrupts in the PRIMASK register instead of
964 * masking with C_MASKINTS,
965 * This is probably the same issue as Cortex-M3 Errata 377493:
966 * C_MASKINTS in parallel with disabled interrupts can cause
967 * local faults to not be taken. */
968 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
969 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
970 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
972 /* Make sure we are in Thumb mode */
973 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
974 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
976 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
977 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
981 /* current = 1: continue on current pc, otherwise continue at <address> */
982 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
984 resume_pc
= *address
;
986 *address
= resume_pc
;
988 /* Make sure that the Armv7 gdb thumb fixups does not
989 * kill the return address
991 switch (arm
->core_state
) {
993 resume_pc
&= 0xFFFFFFFC;
995 case ARM_STATE_THUMB
:
996 case ARM_STATE_THUMB_EE
:
997 /* When the return address is loaded into PC
998 * bit 0 must be 1 to stay in Thumb state
1002 case ARM_STATE_JAZELLE
:
1003 LOG_ERROR("How do I resume into Jazelle state??");
1006 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
1007 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1010 /* restore dpm_mode at system halt */
1011 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1012 /* called it now before restoring context because it uses cpu
1013 * register r0 for restoring cp15 control register */
1014 retval
= cortex_a_restore_cp15_control_reg(target
);
1015 if (retval
!= ERROR_OK
)
1017 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1018 if (retval
!= ERROR_OK
)
1020 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1021 target
->state
= TARGET_RUNNING
;
1023 /* registers are now invalid */
1024 register_cache_invalidate(arm
->core_cache
);
1027 /* the front-end may request us not to handle breakpoints */
1028 if (handle_breakpoints
) {
1029 /* Single step past breakpoint at current address */
1030 breakpoint
= breakpoint_find(target
, resume_pc
);
1032 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1033 cortex_m3_unset_breakpoint(target
, breakpoint
);
1034 cortex_m3_single_step_core(target
);
1035 cortex_m3_set_breakpoint(target
, breakpoint
);
1043 static int cortex_a_internal_restart(struct target
*target
)
1045 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1046 struct arm
*arm
= &armv7a
->arm
;
1047 struct adiv5_dap
*swjdp
= arm
->dap
;
1051 * * Restart core and wait for it to be started. Clear ITRen and sticky
1052 * * exception flags: see ARMv7 ARM, C5.9.
1054 * REVISIT: for single stepping, we probably want to
1055 * disable IRQs by default, with optional override...
1058 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1059 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1060 if (retval
!= ERROR_OK
)
1063 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1064 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1066 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1067 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1068 if (retval
!= ERROR_OK
)
1071 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1072 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1073 DRCR_CLEAR_EXCEPTIONS
);
1074 if (retval
!= ERROR_OK
)
1077 long long then
= timeval_ms();
1079 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1080 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1081 if (retval
!= ERROR_OK
)
1083 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1085 if (timeval_ms() > then
+ 1000) {
1086 LOG_ERROR("Timeout waiting for resume");
1091 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1092 target
->state
= TARGET_RUNNING
;
1094 /* registers are now invalid */
1095 register_cache_invalidate(arm
->core_cache
);
1100 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1103 struct target_list
*head
;
1104 struct target
*curr
;
1106 head
= target
->head
;
1107 while (head
!= (struct target_list
*)NULL
) {
1108 curr
= head
->target
;
1109 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
1110 /* resume current address , not in step mode */
1111 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1112 handle_breakpoints
, 0);
1113 retval
+= cortex_a_internal_restart(curr
);
1121 static int cortex_a_resume(struct target
*target
, int current
,
1122 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1125 /* dummy resume for smp toggle in order to reduce gdb impact */
1126 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1127 /* simulate a start and halt of target */
1128 target
->gdb_service
->target
= NULL
;
1129 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1130 /* fake resume at next poll we play the target core[1], see poll*/
1131 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1134 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1136 target
->gdb_service
->core
[0] = -1;
1137 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1138 if (retval
!= ERROR_OK
)
1141 cortex_a_internal_restart(target
);
1143 if (!debug_execution
) {
1144 target
->state
= TARGET_RUNNING
;
1145 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1146 LOG_DEBUG("target resumed at 0x%" PRIx32
, address
);
1148 target
->state
= TARGET_DEBUG_RUNNING
;
1149 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1150 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, address
);
1156 static int cortex_a_debug_entry(struct target
*target
)
1159 uint32_t regfile
[16], cpsr
, dscr
;
1160 int retval
= ERROR_OK
;
1161 struct working_area
*regfile_working_area
= NULL
;
1162 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1163 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1164 struct arm
*arm
= &armv7a
->arm
;
1165 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1168 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1170 /* REVISIT surely we should not re-read DSCR !! */
1171 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1172 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1173 if (retval
!= ERROR_OK
)
1176 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1177 * imprecise data aborts get discarded by issuing a Data
1178 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1181 /* Enable the ITR execution once we are in debug mode */
1182 dscr
|= DSCR_ITR_EN
;
1183 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1184 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1185 if (retval
!= ERROR_OK
)
1188 /* Examine debug reason */
1189 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1191 /* save address of instruction that triggered the watchpoint? */
1192 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1195 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1196 armv7a
->debug_base
+ CPUDBG_WFAR
,
1198 if (retval
!= ERROR_OK
)
1200 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1203 /* REVISIT fast_reg_read is never set ... */
1205 /* Examine target state and mode */
1206 if (cortex_a
->fast_reg_read
)
1207 target_alloc_working_area(target
, 64, ®file_working_area
);
1209 /* First load register acessible through core debug port*/
1210 if (!regfile_working_area
)
1211 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1213 retval
= cortex_a_read_regs_through_mem(target
,
1214 regfile_working_area
->address
, regfile
);
1216 target_free_working_area(target
, regfile_working_area
);
1217 if (retval
!= ERROR_OK
)
1220 /* read Current PSR */
1221 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1222 /* store current cpsr */
1223 if (retval
!= ERROR_OK
)
1226 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1228 arm_set_cpsr(arm
, cpsr
);
1231 for (i
= 0; i
<= ARM_PC
; i
++) {
1232 reg
= arm_reg_current(arm
, i
);
1234 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1239 /* Fixup PC Resume Address */
1240 if (cpsr
& (1 << 5)) {
1241 /* T bit set for Thumb or ThumbEE state */
1242 regfile
[ARM_PC
] -= 4;
1245 regfile
[ARM_PC
] -= 8;
1249 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1250 reg
->dirty
= reg
->valid
;
1254 /* TODO, Move this */
1255 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1256 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1257 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1259 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1260 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1262 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1263 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1266 /* Are we in an exception handler */
1267 /* armv4_5->exception_number = 0; */
1268 if (armv7a
->post_debug_entry
) {
1269 retval
= armv7a
->post_debug_entry(target
);
1270 if (retval
!= ERROR_OK
)
1277 static int cortex_a_post_debug_entry(struct target
*target
)
1279 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1280 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1283 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1284 retval
= armv7a
->arm
.mrc(target
, 15,
1285 0, 0, /* op1, op2 */
1286 1, 0, /* CRn, CRm */
1287 &cortex_a
->cp15_control_reg
);
1288 if (retval
!= ERROR_OK
)
1290 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1291 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1293 if (armv7a
->armv7a_mmu
.armv7a_cache
.ctype
== -1)
1294 armv7a_identify_cache(target
);
1296 if (armv7a
->is_armv7r
) {
1297 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1299 armv7a
->armv7a_mmu
.mmu_enabled
=
1300 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1302 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1303 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1304 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1305 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1306 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1311 static int cortex_a_step(struct target
*target
, int current
, uint32_t address
,
1312 int handle_breakpoints
)
1314 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1315 struct arm
*arm
= &armv7a
->arm
;
1316 struct breakpoint
*breakpoint
= NULL
;
1317 struct breakpoint stepbreakpoint
;
1321 if (target
->state
!= TARGET_HALTED
) {
1322 LOG_WARNING("target not halted");
1323 return ERROR_TARGET_NOT_HALTED
;
1326 /* current = 1: continue on current pc, otherwise continue at <address> */
1329 buf_set_u32(r
->value
, 0, 32, address
);
1331 address
= buf_get_u32(r
->value
, 0, 32);
1333 /* The front-end may request us not to handle breakpoints.
1334 * But since Cortex-A uses breakpoint for single step,
1335 * we MUST handle breakpoints.
1337 handle_breakpoints
= 1;
1338 if (handle_breakpoints
) {
1339 breakpoint
= breakpoint_find(target
, address
);
1341 cortex_a_unset_breakpoint(target
, breakpoint
);
1344 /* Setup single step breakpoint */
1345 stepbreakpoint
.address
= address
;
1346 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1348 stepbreakpoint
.type
= BKPT_HARD
;
1349 stepbreakpoint
.set
= 0;
1351 /* Break on IVA mismatch */
1352 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1354 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1356 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1357 if (retval
!= ERROR_OK
)
1360 long long then
= timeval_ms();
1361 while (target
->state
!= TARGET_HALTED
) {
1362 retval
= cortex_a_poll(target
);
1363 if (retval
!= ERROR_OK
)
1365 if (timeval_ms() > then
+ 1000) {
1366 LOG_ERROR("timeout waiting for target halt");
1371 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1373 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1376 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1378 if (target
->state
!= TARGET_HALTED
)
1379 LOG_DEBUG("target stepped");
1384 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1386 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1390 if (armv7a
->pre_restore_context
)
1391 armv7a
->pre_restore_context(target
);
1393 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1397 * Cortex-A Breakpoint and watchpoint functions
1400 /* Setup hardware Breakpoint Register Pair */
1401 static int cortex_a_set_breakpoint(struct target
*target
,
1402 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1407 uint8_t byte_addr_select
= 0x0F;
1408 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1409 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1410 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1412 if (breakpoint
->set
) {
1413 LOG_WARNING("breakpoint already set");
1417 if (breakpoint
->type
== BKPT_HARD
) {
1418 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1420 if (brp_i
>= cortex_a
->brp_num
) {
1421 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1422 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1424 breakpoint
->set
= brp_i
+ 1;
1425 if (breakpoint
->length
== 2)
1426 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1427 control
= ((matchmode
& 0x7) << 20)
1428 | (byte_addr_select
<< 5)
1430 brp_list
[brp_i
].used
= 1;
1431 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1432 brp_list
[brp_i
].control
= control
;
1433 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1434 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1435 brp_list
[brp_i
].value
);
1436 if (retval
!= ERROR_OK
)
1438 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1439 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1440 brp_list
[brp_i
].control
);
1441 if (retval
!= ERROR_OK
)
1443 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1444 brp_list
[brp_i
].control
,
1445 brp_list
[brp_i
].value
);
1446 } else if (breakpoint
->type
== BKPT_SOFT
) {
1448 if (breakpoint
->length
== 2)
1449 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1451 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1452 retval
= target_read_memory(target
,
1453 breakpoint
->address
& 0xFFFFFFFE,
1454 breakpoint
->length
, 1,
1455 breakpoint
->orig_instr
);
1456 if (retval
!= ERROR_OK
)
1458 retval
= target_write_memory(target
,
1459 breakpoint
->address
& 0xFFFFFFFE,
1460 breakpoint
->length
, 1, code
);
1461 if (retval
!= ERROR_OK
)
1463 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1469 static int cortex_a_set_context_breakpoint(struct target
*target
,
1470 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1472 int retval
= ERROR_FAIL
;
1475 uint8_t byte_addr_select
= 0x0F;
1476 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1477 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1478 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1480 if (breakpoint
->set
) {
1481 LOG_WARNING("breakpoint already set");
1484 /*check available context BRPs*/
1485 while ((brp_list
[brp_i
].used
||
1486 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1489 if (brp_i
>= cortex_a
->brp_num
) {
1490 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1494 breakpoint
->set
= brp_i
+ 1;
1495 control
= ((matchmode
& 0x7) << 20)
1496 | (byte_addr_select
<< 5)
1498 brp_list
[brp_i
].used
= 1;
1499 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1500 brp_list
[brp_i
].control
= control
;
1501 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1502 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1503 brp_list
[brp_i
].value
);
1504 if (retval
!= ERROR_OK
)
1506 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1507 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1508 brp_list
[brp_i
].control
);
1509 if (retval
!= ERROR_OK
)
1511 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1512 brp_list
[brp_i
].control
,
1513 brp_list
[brp_i
].value
);
1518 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1520 int retval
= ERROR_FAIL
;
1521 int brp_1
= 0; /* holds the contextID pair */
1522 int brp_2
= 0; /* holds the IVA pair */
1523 uint32_t control_CTX
, control_IVA
;
1524 uint8_t CTX_byte_addr_select
= 0x0F;
1525 uint8_t IVA_byte_addr_select
= 0x0F;
1526 uint8_t CTX_machmode
= 0x03;
1527 uint8_t IVA_machmode
= 0x01;
1528 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1529 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1530 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1532 if (breakpoint
->set
) {
1533 LOG_WARNING("breakpoint already set");
1536 /*check available context BRPs*/
1537 while ((brp_list
[brp_1
].used
||
1538 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1541 printf("brp(CTX) found num: %d\n", brp_1
);
1542 if (brp_1
>= cortex_a
->brp_num
) {
1543 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1547 while ((brp_list
[brp_2
].used
||
1548 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1551 printf("brp(IVA) found num: %d\n", brp_2
);
1552 if (brp_2
>= cortex_a
->brp_num
) {
1553 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1557 breakpoint
->set
= brp_1
+ 1;
1558 breakpoint
->linked_BRP
= brp_2
;
1559 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1562 | (CTX_byte_addr_select
<< 5)
1564 brp_list
[brp_1
].used
= 1;
1565 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1566 brp_list
[brp_1
].control
= control_CTX
;
1567 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1568 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1569 brp_list
[brp_1
].value
);
1570 if (retval
!= ERROR_OK
)
1572 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1573 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1574 brp_list
[brp_1
].control
);
1575 if (retval
!= ERROR_OK
)
1578 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1580 | (IVA_byte_addr_select
<< 5)
1582 brp_list
[brp_2
].used
= 1;
1583 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1584 brp_list
[brp_2
].control
= control_IVA
;
1585 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1586 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1587 brp_list
[brp_2
].value
);
1588 if (retval
!= ERROR_OK
)
1590 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1591 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1592 brp_list
[brp_2
].control
);
1593 if (retval
!= ERROR_OK
)
1599 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1602 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1603 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1604 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1606 if (!breakpoint
->set
) {
1607 LOG_WARNING("breakpoint not set");
1611 if (breakpoint
->type
== BKPT_HARD
) {
1612 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1613 int brp_i
= breakpoint
->set
- 1;
1614 int brp_j
= breakpoint
->linked_BRP
;
1615 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1616 LOG_DEBUG("Invalid BRP number in breakpoint");
1619 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1620 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1621 brp_list
[brp_i
].used
= 0;
1622 brp_list
[brp_i
].value
= 0;
1623 brp_list
[brp_i
].control
= 0;
1624 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1625 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1626 brp_list
[brp_i
].control
);
1627 if (retval
!= ERROR_OK
)
1629 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1630 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1631 brp_list
[brp_i
].value
);
1632 if (retval
!= ERROR_OK
)
1634 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1635 LOG_DEBUG("Invalid BRP number in breakpoint");
1638 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1639 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1640 brp_list
[brp_j
].used
= 0;
1641 brp_list
[brp_j
].value
= 0;
1642 brp_list
[brp_j
].control
= 0;
1643 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1644 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1645 brp_list
[brp_j
].control
);
1646 if (retval
!= ERROR_OK
)
1648 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1649 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1650 brp_list
[brp_j
].value
);
1651 if (retval
!= ERROR_OK
)
1653 breakpoint
->linked_BRP
= 0;
1654 breakpoint
->set
= 0;
1658 int brp_i
= breakpoint
->set
- 1;
1659 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1660 LOG_DEBUG("Invalid BRP number in breakpoint");
1663 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1664 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1665 brp_list
[brp_i
].used
= 0;
1666 brp_list
[brp_i
].value
= 0;
1667 brp_list
[brp_i
].control
= 0;
1668 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1669 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1670 brp_list
[brp_i
].control
);
1671 if (retval
!= ERROR_OK
)
1673 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1674 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1675 brp_list
[brp_i
].value
);
1676 if (retval
!= ERROR_OK
)
1678 breakpoint
->set
= 0;
1682 /* restore original instruction (kept in target endianness) */
1683 if (breakpoint
->length
== 4) {
1684 retval
= target_write_memory(target
,
1685 breakpoint
->address
& 0xFFFFFFFE,
1686 4, 1, breakpoint
->orig_instr
);
1687 if (retval
!= ERROR_OK
)
1690 retval
= target_write_memory(target
,
1691 breakpoint
->address
& 0xFFFFFFFE,
1692 2, 1, breakpoint
->orig_instr
);
1693 if (retval
!= ERROR_OK
)
1697 breakpoint
->set
= 0;
1702 static int cortex_a_add_breakpoint(struct target
*target
,
1703 struct breakpoint
*breakpoint
)
1705 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1707 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1708 LOG_INFO("no hardware breakpoint available");
1709 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1712 if (breakpoint
->type
== BKPT_HARD
)
1713 cortex_a
->brp_num_available
--;
1715 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1718 static int cortex_a_add_context_breakpoint(struct target
*target
,
1719 struct breakpoint
*breakpoint
)
1721 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1723 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1724 LOG_INFO("no hardware breakpoint available");
1725 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1728 if (breakpoint
->type
== BKPT_HARD
)
1729 cortex_a
->brp_num_available
--;
1731 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1734 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1735 struct breakpoint
*breakpoint
)
1737 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1739 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1740 LOG_INFO("no hardware breakpoint available");
1741 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1744 if (breakpoint
->type
== BKPT_HARD
)
1745 cortex_a
->brp_num_available
--;
1747 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1751 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1753 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1756 /* It is perfectly possible to remove breakpoints while the target is running */
1757 if (target
->state
!= TARGET_HALTED
) {
1758 LOG_WARNING("target not halted");
1759 return ERROR_TARGET_NOT_HALTED
;
1763 if (breakpoint
->set
) {
1764 cortex_a_unset_breakpoint(target
, breakpoint
);
1765 if (breakpoint
->type
== BKPT_HARD
)
1766 cortex_a
->brp_num_available
++;
1774 * Cortex-A Reset functions
1777 static int cortex_a_assert_reset(struct target
*target
)
1779 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1783 /* FIXME when halt is requested, make it work somehow... */
1785 /* Issue some kind of warm reset. */
1786 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1787 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1788 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1789 /* REVISIT handle "pulls" cases, if there's
1790 * hardware that needs them to work.
1792 jtag_add_reset(0, 1);
1794 LOG_ERROR("%s: how to reset?", target_name(target
));
1798 /* registers are now invalid */
1799 register_cache_invalidate(armv7a
->arm
.core_cache
);
1801 target
->state
= TARGET_RESET
;
1806 static int cortex_a_deassert_reset(struct target
*target
)
1812 /* be certain SRST is off */
1813 jtag_add_reset(0, 0);
1815 retval
= cortex_a_poll(target
);
1816 if (retval
!= ERROR_OK
)
1819 if (target
->reset_halt
) {
1820 if (target
->state
!= TARGET_HALTED
) {
1821 LOG_WARNING("%s: ran after reset and before halt ...",
1822 target_name(target
));
1823 retval
= target_halt(target
);
1824 if (retval
!= ERROR_OK
)
1832 static int cortex_a_write_apb_ab_memory(struct target
*target
,
1833 uint32_t address
, uint32_t size
,
1834 uint32_t count
, const uint8_t *buffer
)
1836 /* write memory through APB-AP */
1838 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1839 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1840 struct arm
*arm
= &armv7a
->arm
;
1841 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1842 int total_bytes
= count
* size
;
1844 int start_byte
= address
& 0x3;
1845 int end_byte
= (address
+ total_bytes
) & 0x3;
1848 uint8_t *tmp_buff
= NULL
;
1851 LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count%" PRIu32
,
1852 address
, size
, count
);
1853 if (target
->state
!= TARGET_HALTED
) {
1854 LOG_WARNING("target not halted");
1855 return ERROR_TARGET_NOT_HALTED
;
1858 total_u32
= DIV_ROUND_UP((address
& 3) + total_bytes
, 4);
1860 /* Mark register R0 as dirty, as it will be used
1861 * for transferring the data.
1862 * It will be restored automatically when exiting
1865 reg
= arm_reg_current(arm
, 0);
1868 /* clear any abort */
1869 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
1870 if (retval
!= ERROR_OK
)
1873 /* This algorithm comes from either :
1874 * Cortex-A TRM Example 12-25
1875 * Cortex-R4 TRM Example 11-26
1876 * (slight differences)
1879 /* The algorithm only copies 32 bit words, so the buffer
1880 * should be expanded to include the words at either end.
1881 * The first and last words will be read first to avoid
1882 * corruption if needed.
1884 tmp_buff
= malloc(total_u32
* 4);
1886 if ((start_byte
!= 0) && (total_u32
> 1)) {
1887 /* First bytes not aligned - read the 32 bit word to avoid corrupting
1888 * the other bytes in the word.
1890 retval
= cortex_a_read_apb_ab_memory(target
, (address
& ~0x3), 4, 1, tmp_buff
);
1891 if (retval
!= ERROR_OK
)
1892 goto error_free_buff_w
;
1895 /* If end of write is not aligned, or the write is less than 4 bytes */
1896 if ((end_byte
!= 0) ||
1897 ((total_u32
== 1) && (total_bytes
!= 4))) {
1898 /* Read the last word to avoid corruption during 32 bit write */
1899 int mem_offset
= (total_u32
-1) * 4;
1900 retval
= cortex_a_read_apb_ab_memory(target
, (address
& ~0x3) + mem_offset
, 4, 1, &tmp_buff
[mem_offset
]);
1901 if (retval
!= ERROR_OK
)
1902 goto error_free_buff_w
;
1905 /* Copy the write buffer over the top of the temporary buffer */
1906 memcpy(&tmp_buff
[start_byte
], buffer
, total_bytes
);
1908 /* We now have a 32 bit aligned buffer that can be written */
1911 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1912 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1913 if (retval
!= ERROR_OK
)
1914 goto error_free_buff_w
;
1916 /* Set DTR mode to Fast (2) */
1917 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_FAST_MODE
;
1918 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1919 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1920 if (retval
!= ERROR_OK
)
1921 goto error_free_buff_w
;
1923 /* Copy the destination address into R0 */
1924 /* - pend an instruction MRC p14, 0, R0, c5, c0 */
1925 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1926 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
1927 if (retval
!= ERROR_OK
)
1928 goto error_unset_dtr_w
;
1929 /* Write address into DTRRX, which triggers previous instruction */
1930 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1931 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
& (~0x3));
1932 if (retval
!= ERROR_OK
)
1933 goto error_unset_dtr_w
;
1935 /* Write the data transfer instruction into the ITR
1936 * (STC p14, c5, [R0], 4)
1938 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1939 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
1940 if (retval
!= ERROR_OK
)
1941 goto error_unset_dtr_w
;
1944 retval
= mem_ap_sel_write_buf_noincr(swjdp
, armv7a
->debug_ap
,
1945 tmp_buff
, 4, total_u32
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
1946 if (retval
!= ERROR_OK
)
1947 goto error_unset_dtr_w
;
1950 /* Switch DTR mode back to non-blocking (0) */
1951 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
1952 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1953 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1954 if (retval
!= ERROR_OK
)
1955 goto error_unset_dtr_w
;
1957 /* Check for sticky abort flags in the DSCR */
1958 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1959 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1960 if (retval
!= ERROR_OK
)
1961 goto error_free_buff_w
;
1962 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
1963 /* Abort occurred - clear it and exit */
1964 LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32
, dscr
);
1965 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1966 armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
1967 goto error_free_buff_w
;
1975 /* Unset DTR mode */
1976 mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1977 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1978 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
1979 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1980 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1987 static int cortex_a_read_apb_ab_memory(struct target
*target
,
1988 uint32_t address
, uint32_t size
,
1989 uint32_t count
, uint8_t *buffer
)
1991 /* read memory through APB-AP */
1993 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
1994 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1995 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1996 struct arm
*arm
= &armv7a
->arm
;
1997 int total_bytes
= count
* size
;
1999 int start_byte
= address
& 0x3;
2000 int end_byte
= (address
+ total_bytes
) & 0x3;
2003 uint8_t *tmp_buff
= NULL
;
2007 LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count%" PRIu32
,
2008 address
, size
, count
);
2009 if (target
->state
!= TARGET_HALTED
) {
2010 LOG_WARNING("target not halted");
2011 return ERROR_TARGET_NOT_HALTED
;
2014 total_u32
= DIV_ROUND_UP((address
& 3) + total_bytes
, 4);
2015 /* Mark register R0 as dirty, as it will be used
2016 * for transferring the data.
2017 * It will be restored automatically when exiting
2020 reg
= arm_reg_current(arm
, 0);
2023 /* clear any abort */
2025 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
2026 if (retval
!= ERROR_OK
)
2027 goto error_free_buff_r
;
2030 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2031 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2033 /* This algorithm comes from either :
2034 * Cortex-A TRM Example 12-24
2035 * Cortex-R4 TRM Example 11-25
2036 * (slight differences)
2039 /* Set DTR access mode to stall mode b01 */
2040 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_STALL_MODE
;
2041 retval
+= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2042 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
2044 /* Write R0 with value 'address' using write procedure for stall mode */
2045 /* - Write the address for read access into DTRRX */
2046 retval
+= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2047 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
& ~0x3);
2048 /* - Copy value from DTRRX to R0 using instruction mrc p14, 0, r0, c5, c0 */
2049 cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2051 /* Write the data transfer instruction (ldc p14, c5, [r0],4)
2052 * and the DTR mode setting to fast mode
2053 * in one combined write (since they are adjacent registers)
2056 target_buffer_set_u32(target
, u8buf_ptr
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2057 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_FAST_MODE
;
2058 target_buffer_set_u32(target
, u8buf_ptr
+ 4, dscr
);
2059 /* group the 2 access CPUDBG_ITR 0x84 and CPUDBG_DSCR 0x88 */
2060 retval
+= mem_ap_sel_write_buf(swjdp
, armv7a
->debug_ap
, u8buf_ptr
, 4, 2,
2061 armv7a
->debug_base
+ CPUDBG_ITR
);
2062 if (retval
!= ERROR_OK
)
2063 goto error_unset_dtr_r
;
2065 /* Optimize the read as much as we can, either way we read in a single pass */
2066 if ((start_byte
) || (end_byte
)) {
2067 /* The algorithm only copies 32 bit words, so the buffer
2068 * should be expanded to include the words at either end.
2069 * The first and last words will be read into a temp buffer
2070 * to avoid corruption
2072 tmp_buff
= malloc(total_u32
* 4);
2074 goto error_unset_dtr_r
;
2076 /* use the tmp buffer to read the entire data */
2077 u8buf_ptr
= tmp_buff
;
2079 /* address and read length are aligned so read directely into the passed buffer */
2082 /* Read the data - Each read of the DTRTX register causes the instruction to be reissued
2083 * Abort flags are sticky, so can be read at end of transactions
2085 * This data is read in aligned to 32 bit boundary.
2087 retval
= mem_ap_sel_read_buf_noincr(swjdp
, armv7a
->debug_ap
, u8buf_ptr
, 4, total_u32
,
2088 armv7a
->debug_base
+ CPUDBG_DTRTX
);
2089 if (retval
!= ERROR_OK
)
2090 goto error_unset_dtr_r
;
2092 /* set DTR access mode back to non blocking b00 */
2093 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
2094 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2095 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
2096 if (retval
!= ERROR_OK
)
2097 goto error_free_buff_r
;
2099 /* Wait for the final read instruction to finish */
2101 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2102 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2103 if (retval
!= ERROR_OK
)
2104 goto error_free_buff_r
;
2105 } while ((dscr
& DSCR_INSTR_COMP
) == 0);
2107 /* Check for sticky abort flags in the DSCR */
2108 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2109 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2110 if (retval
!= ERROR_OK
)
2111 goto error_free_buff_r
;
2112 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2113 /* Abort occurred - clear it and exit */
2114 LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32
, dscr
);
2115 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2116 armv7a
->debug_base
+ CPUDBG_DRCR
, 1<<2);
2117 goto error_free_buff_r
;
2120 /* check if we need to copy aligned data by applying any shift necessary */
2122 memcpy(buffer
, tmp_buff
+ start_byte
, total_bytes
);
2130 /* Unset DTR mode */
2131 mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2132 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2133 dscr
= (dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_NON_BLOCKING
;
2134 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2135 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
2144 * Cortex-A Memory access
2146 * This is same Cortex M3 but we must also use the correct
2147 * ap number for every access.
2150 static int cortex_a_read_phys_memory(struct target
*target
,
2151 uint32_t address
, uint32_t size
,
2152 uint32_t count
, uint8_t *buffer
)
2154 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2155 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2156 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2157 uint8_t apsel
= swjdp
->apsel
;
2158 LOG_DEBUG("Reading memory at real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
,
2159 address
, size
, count
);
2161 if (count
&& buffer
) {
2163 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2165 /* read memory through AHB-AP */
2166 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2169 /* read memory through APB-AP */
2170 if (!armv7a
->is_armv7r
) {
2172 retval
= cortex_a_mmu_modify(target
, 0);
2173 if (retval
!= ERROR_OK
)
2176 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2182 static int cortex_a_read_memory(struct target
*target
, uint32_t address
,
2183 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2185 int mmu_enabled
= 0;
2186 uint32_t virt
, phys
;
2188 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2189 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2190 uint8_t apsel
= swjdp
->apsel
;
2192 /* cortex_a handles unaligned memory access */
2193 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2196 /* determine if MMU was enabled on target stop */
2197 if (!armv7a
->is_armv7r
) {
2198 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2199 if (retval
!= ERROR_OK
)
2203 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2206 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2207 if (retval
!= ERROR_OK
)
2210 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2214 retval
= cortex_a_read_phys_memory(target
, address
, size
,
2218 retval
= cortex_a_check_address(target
, address
);
2219 if (retval
!= ERROR_OK
)
2221 /* enable MMU as we could have disabled it for phys access */
2222 retval
= cortex_a_mmu_modify(target
, 1);
2223 if (retval
!= ERROR_OK
)
2226 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2231 static int cortex_a_write_phys_memory(struct target
*target
,
2232 uint32_t address
, uint32_t size
,
2233 uint32_t count
, const uint8_t *buffer
)
2235 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2236 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2237 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2238 uint8_t apsel
= swjdp
->apsel
;
2240 LOG_DEBUG("Writing memory to real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2243 if (count
&& buffer
) {
2245 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2247 /* write memory through AHB-AP */
2248 retval
= mem_ap_sel_write_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2251 /* write memory through APB-AP */
2252 if (!armv7a
->is_armv7r
) {
2253 retval
= cortex_a_mmu_modify(target
, 0);
2254 if (retval
!= ERROR_OK
)
2257 return cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2262 /* REVISIT this op is generic ARMv7-A/R stuff */
2263 if (retval
== ERROR_OK
&& target
->state
== TARGET_HALTED
) {
2264 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
2266 retval
= dpm
->prepare(dpm
);
2267 if (retval
!= ERROR_OK
)
2270 /* The Cache handling will NOT work with MMU active, the
2271 * wrong addresses will be invalidated!
2273 * For both ICache and DCache, walk all cache lines in the
2274 * address range. Cortex-A has fixed 64 byte line length.
2276 * REVISIT per ARMv7, these may trigger watchpoints ...
2279 /* invalidate I-Cache */
2280 if (armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
) {
2281 /* ICIMVAU - Invalidate Cache single entry
2283 * MCR p15, 0, r0, c7, c5, 1
2285 for (uint32_t cacheline
= 0;
2286 cacheline
< size
* count
;
2288 retval
= dpm
->instr_write_data_r0(dpm
,
2289 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
2290 address
+ cacheline
);
2291 if (retval
!= ERROR_OK
)
2296 /* invalidate D-Cache */
2297 if (armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
) {
2298 /* DCIMVAC - Invalidate data Cache line
2300 * MCR p15, 0, r0, c7, c6, 1
2302 for (uint32_t cacheline
= 0;
2303 cacheline
< size
* count
;
2305 retval
= dpm
->instr_write_data_r0(dpm
,
2306 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
2307 address
+ cacheline
);
2308 if (retval
!= ERROR_OK
)
2313 /* (void) */ dpm
->finish(dpm
);
2319 static int cortex_a_write_memory(struct target
*target
, uint32_t address
,
2320 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2322 int mmu_enabled
= 0;
2323 uint32_t virt
, phys
;
2325 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2326 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2327 uint8_t apsel
= swjdp
->apsel
;
2329 /* cortex_a handles unaligned memory access */
2330 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2333 /* determine if MMU was enabled on target stop */
2334 if (!armv7a
->is_armv7r
) {
2335 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2336 if (retval
!= ERROR_OK
)
2340 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2341 LOG_DEBUG("Writing memory to address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
, size
,
2345 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2346 if (retval
!= ERROR_OK
)
2349 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2354 retval
= cortex_a_write_phys_memory(target
, address
, size
,
2358 retval
= cortex_a_check_address(target
, address
);
2359 if (retval
!= ERROR_OK
)
2361 /* enable MMU as we could have disabled it for phys access */
2362 retval
= cortex_a_mmu_modify(target
, 1);
2363 if (retval
!= ERROR_OK
)
2366 retval
= cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2371 static int cortex_a_handle_target_request(void *priv
)
2373 struct target
*target
= priv
;
2374 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2375 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2378 if (!target_was_examined(target
))
2380 if (!target
->dbg_msg_enabled
)
2383 if (target
->state
== TARGET_RUNNING
) {
2386 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2387 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2389 /* check if we have data */
2390 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2391 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2392 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2393 if (retval
== ERROR_OK
) {
2394 target_request(target
, request
);
2395 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2396 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2405 * Cortex-A target information and configuration
2408 static int cortex_a_examine_first(struct target
*target
)
2410 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2411 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2412 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2414 int retval
= ERROR_OK
;
2415 uint32_t didr
, ctypr
, ttypr
, cpuid
, dbg_osreg
;
2417 /* We do one extra read to ensure DAP is configured,
2418 * we call ahbap_debugport_init(swjdp) instead
2420 retval
= ahbap_debugport_init(swjdp
);
2421 if (retval
!= ERROR_OK
)
2424 /* Search for the APB-AB - it is needed for access to debug registers */
2425 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2426 if (retval
!= ERROR_OK
) {
2427 LOG_ERROR("Could not find APB-AP for debug access");
2430 /* Search for the AHB-AB */
2431 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
2432 if (retval
!= ERROR_OK
) {
2433 /* AHB-AP not found - use APB-AP */
2434 LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access");
2435 armv7a
->memory_ap_available
= false;
2437 armv7a
->memory_ap_available
= true;
2441 if (!target
->dbgbase_set
) {
2443 /* Get ROM Table base */
2445 int32_t coreidx
= target
->coreid
;
2446 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2448 retval
= dap_get_debugbase(swjdp
, 1, &dbgbase
, &apid
);
2449 if (retval
!= ERROR_OK
)
2451 /* Lookup 0x15 -- Processor DAP */
2452 retval
= dap_lookup_cs_component(swjdp
, 1, dbgbase
, 0x15,
2453 &armv7a
->debug_base
, &coreidx
);
2454 if (retval
!= ERROR_OK
)
2456 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2457 coreidx
, armv7a
->debug_base
);
2459 armv7a
->debug_base
= target
->dbgbase
;
2461 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2462 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2463 if (retval
!= ERROR_OK
)
2466 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2467 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2468 if (retval
!= ERROR_OK
) {
2469 LOG_DEBUG("Examine %s failed", "CPUID");
2473 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2474 armv7a
->debug_base
+ CPUDBG_CTYPR
, &ctypr
);
2475 if (retval
!= ERROR_OK
) {
2476 LOG_DEBUG("Examine %s failed", "CTYPR");
2480 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2481 armv7a
->debug_base
+ CPUDBG_TTYPR
, &ttypr
);
2482 if (retval
!= ERROR_OK
) {
2483 LOG_DEBUG("Examine %s failed", "TTYPR");
2487 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2488 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2489 if (retval
!= ERROR_OK
) {
2490 LOG_DEBUG("Examine %s failed", "DIDR");
2494 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
2495 LOG_DEBUG("ctypr = 0x%08" PRIx32
, ctypr
);
2496 LOG_DEBUG("ttypr = 0x%08" PRIx32
, ttypr
);
2497 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
2499 cortex_a
->cpuid
= cpuid
;
2500 cortex_a
->ctypr
= ctypr
;
2501 cortex_a
->ttypr
= ttypr
;
2502 cortex_a
->didr
= didr
;
2504 /* Unlocking the debug registers */
2505 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
2506 CORTEX_A15_PARTNUM
) {
2508 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2509 armv7a
->debug_base
+ CPUDBG_OSLAR
,
2512 if (retval
!= ERROR_OK
)
2516 /* Unlocking the debug registers */
2517 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
2518 CORTEX_A7_PARTNUM
) {
2520 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2521 armv7a
->debug_base
+ CPUDBG_OSLAR
,
2524 if (retval
!= ERROR_OK
)
2528 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2529 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
2531 if (retval
!= ERROR_OK
)
2534 LOG_DEBUG("target->coreid %d DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
2536 armv7a
->arm
.core_type
= ARM_MODE_MON
;
2537 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
2538 if (retval
!= ERROR_OK
)
2541 /* Setup Breakpoint Register Pairs */
2542 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
2543 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
2544 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
2545 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
2546 /* cortex_a->brb_enabled = ????; */
2547 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
2548 cortex_a
->brp_list
[i
].used
= 0;
2549 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
2550 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
2552 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
2553 cortex_a
->brp_list
[i
].value
= 0;
2554 cortex_a
->brp_list
[i
].control
= 0;
2555 cortex_a
->brp_list
[i
].BRPn
= i
;
2558 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
2560 target_set_examined(target
);
2564 static int cortex_a_examine(struct target
*target
)
2566 int retval
= ERROR_OK
;
2568 /* don't re-probe hardware after each reset */
2569 if (!target_was_examined(target
))
2570 retval
= cortex_a_examine_first(target
);
2572 /* Configure core debug access */
2573 if (retval
== ERROR_OK
)
2574 retval
= cortex_a_init_debug_access(target
);
2580 * Cortex-A target creation and initialization
2583 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
2584 struct target
*target
)
2586 /* examine_first() does a bunch of this */
2590 static int cortex_a_init_arch_info(struct target
*target
,
2591 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
2593 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2594 struct adiv5_dap
*dap
= &armv7a
->dap
;
2596 armv7a
->arm
.dap
= dap
;
2598 /* Setup struct cortex_a_common */
2599 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
2600 /* tap has no dap initialized */
2602 armv7a
->arm
.dap
= dap
;
2603 /* Setup struct cortex_a_common */
2605 /* prepare JTAG information for the new target */
2606 cortex_a
->jtag_info
.tap
= tap
;
2607 cortex_a
->jtag_info
.scann_size
= 4;
2609 /* Leave (only) generic DAP stuff for debugport_init() */
2610 dap
->jtag_info
= &cortex_a
->jtag_info
;
2612 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
2613 dap
->tar_autoincr_block
= (1 << 10);
2614 dap
->memaccess_tck
= 80;
2617 armv7a
->arm
.dap
= tap
->dap
;
2619 cortex_a
->fast_reg_read
= 0;
2621 /* register arch-specific functions */
2622 armv7a
->examine_debug_reason
= NULL
;
2624 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
2626 armv7a
->pre_restore_context
= NULL
;
2628 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
2631 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
2633 /* REVISIT v7a setup should be in a v7a-specific routine */
2634 armv7a_init_arch_info(target
, armv7a
);
2635 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
2640 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
2642 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
2644 cortex_a
->armv7a_common
.is_armv7r
= false;
2646 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
2649 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
2651 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
2653 cortex_a
->armv7a_common
.is_armv7r
= true;
2655 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
2659 static int cortex_a_mmu(struct target
*target
, int *enabled
)
2661 if (target
->state
!= TARGET_HALTED
) {
2662 LOG_ERROR("%s: target not halted", __func__
);
2663 return ERROR_TARGET_INVALID
;
2666 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
2670 static int cortex_a_virt2phys(struct target
*target
,
2671 uint32_t virt
, uint32_t *phys
)
2673 int retval
= ERROR_FAIL
;
2674 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2675 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2676 uint8_t apsel
= swjdp
->apsel
;
2677 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
2679 retval
= armv7a_mmu_translate_va(target
,
2681 if (retval
!= ERROR_OK
)
2684 } else {/* use this method if armv7a->memory_ap not selected
2685 * mmu must be enable in order to get a correct translation */
2686 retval
= cortex_a_mmu_modify(target
, 1);
2687 if (retval
!= ERROR_OK
)
2689 retval
= armv7a_mmu_translate_va_pa(target
, virt
, phys
, 1);
2695 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
2697 struct target
*target
= get_current_target(CMD_CTX
);
2698 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2700 return armv7a_handle_cache_info_command(CMD_CTX
,
2701 &armv7a
->armv7a_mmu
.armv7a_cache
);
2705 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
2707 struct target
*target
= get_current_target(CMD_CTX
);
2708 if (!target_was_examined(target
)) {
2709 LOG_ERROR("target not examined yet");
2713 return cortex_a_init_debug_access(target
);
2715 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
2717 struct target
*target
= get_current_target(CMD_CTX
);
2718 /* check target is an smp target */
2719 struct target_list
*head
;
2720 struct target
*curr
;
2721 head
= target
->head
;
2723 if (head
!= (struct target_list
*)NULL
) {
2724 while (head
!= (struct target_list
*)NULL
) {
2725 curr
= head
->target
;
2729 /* fixes the target display to the debugger */
2730 target
->gdb_service
->target
= target
;
2735 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
2737 struct target
*target
= get_current_target(CMD_CTX
);
2738 struct target_list
*head
;
2739 struct target
*curr
;
2740 head
= target
->head
;
2741 if (head
!= (struct target_list
*)NULL
) {
2743 while (head
!= (struct target_list
*)NULL
) {
2744 curr
= head
->target
;
2752 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
2754 struct target
*target
= get_current_target(CMD_CTX
);
2755 int retval
= ERROR_OK
;
2756 struct target_list
*head
;
2757 head
= target
->head
;
2758 if (head
!= (struct target_list
*)NULL
) {
2759 if (CMD_ARGC
== 1) {
2761 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
2762 if (ERROR_OK
!= retval
)
2764 target
->gdb_service
->core
[1] = coreid
;
2767 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
2768 , target
->gdb_service
->core
[1]);
2773 static const struct command_registration cortex_a_exec_command_handlers
[] = {
2775 .name
= "cache_info",
2776 .handler
= cortex_a_handle_cache_info_command
,
2777 .mode
= COMMAND_EXEC
,
2778 .help
= "display information about target caches",
2783 .handler
= cortex_a_handle_dbginit_command
,
2784 .mode
= COMMAND_EXEC
,
2785 .help
= "Initialize core debug",
2788 { .name
= "smp_off",
2789 .handler
= cortex_a_handle_smp_off_command
,
2790 .mode
= COMMAND_EXEC
,
2791 .help
= "Stop smp handling",
2795 .handler
= cortex_a_handle_smp_on_command
,
2796 .mode
= COMMAND_EXEC
,
2797 .help
= "Restart smp handling",
2802 .handler
= cortex_a_handle_smp_gdb_command
,
2803 .mode
= COMMAND_EXEC
,
2804 .help
= "display/fix current core played to gdb",
2809 COMMAND_REGISTRATION_DONE
2811 static const struct command_registration cortex_a_command_handlers
[] = {
2813 .chain
= arm_command_handlers
,
2816 .chain
= armv7a_command_handlers
,
2820 .mode
= COMMAND_ANY
,
2821 .help
= "Cortex-A command group",
2823 .chain
= cortex_a_exec_command_handlers
,
2825 COMMAND_REGISTRATION_DONE
2828 struct target_type cortexa_target
= {
2830 .deprecated_name
= "cortex_a8",
2832 .poll
= cortex_a_poll
,
2833 .arch_state
= armv7a_arch_state
,
2835 .halt
= cortex_a_halt
,
2836 .resume
= cortex_a_resume
,
2837 .step
= cortex_a_step
,
2839 .assert_reset
= cortex_a_assert_reset
,
2840 .deassert_reset
= cortex_a_deassert_reset
,
2842 /* REVISIT allow exporting VFP3 registers ... */
2843 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
2845 .read_memory
= cortex_a_read_memory
,
2846 .write_memory
= cortex_a_write_memory
,
2848 .checksum_memory
= arm_checksum_memory
,
2849 .blank_check_memory
= arm_blank_check_memory
,
2851 .run_algorithm
= armv4_5_run_algorithm
,
2853 .add_breakpoint
= cortex_a_add_breakpoint
,
2854 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
2855 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
2856 .remove_breakpoint
= cortex_a_remove_breakpoint
,
2857 .add_watchpoint
= NULL
,
2858 .remove_watchpoint
= NULL
,
2860 .commands
= cortex_a_command_handlers
,
2861 .target_create
= cortex_a_target_create
,
2862 .init_target
= cortex_a_init_target
,
2863 .examine
= cortex_a_examine
,
2865 .read_phys_memory
= cortex_a_read_phys_memory
,
2866 .write_phys_memory
= cortex_a_write_phys_memory
,
2867 .mmu
= cortex_a_mmu
,
2868 .virt2phys
= cortex_a_virt2phys
,
2871 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
2873 .name
= "cache_info",
2874 .handler
= cortex_a_handle_cache_info_command
,
2875 .mode
= COMMAND_EXEC
,
2876 .help
= "display information about target caches",
2881 .handler
= cortex_a_handle_dbginit_command
,
2882 .mode
= COMMAND_EXEC
,
2883 .help
= "Initialize core debug",
2887 COMMAND_REGISTRATION_DONE
2889 static const struct command_registration cortex_r4_command_handlers
[] = {
2891 .chain
= arm_command_handlers
,
2894 .chain
= armv7a_command_handlers
,
2897 .name
= "cortex_r4",
2898 .mode
= COMMAND_ANY
,
2899 .help
= "Cortex-R4 command group",
2901 .chain
= cortex_r4_exec_command_handlers
,
2903 COMMAND_REGISTRATION_DONE
2906 struct target_type cortexr4_target
= {
2907 .name
= "cortex_r4",
2909 .poll
= cortex_a_poll
,
2910 .arch_state
= armv7a_arch_state
,
2912 .halt
= cortex_a_halt
,
2913 .resume
= cortex_a_resume
,
2914 .step
= cortex_a_step
,
2916 .assert_reset
= cortex_a_assert_reset
,
2917 .deassert_reset
= cortex_a_deassert_reset
,
2919 /* REVISIT allow exporting VFP3 registers ... */
2920 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
2922 .read_memory
= cortex_a_read_memory
,
2923 .write_memory
= cortex_a_write_memory
,
2925 .checksum_memory
= arm_checksum_memory
,
2926 .blank_check_memory
= arm_blank_check_memory
,
2928 .run_algorithm
= armv4_5_run_algorithm
,
2930 .add_breakpoint
= cortex_a_add_breakpoint
,
2931 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
2932 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
2933 .remove_breakpoint
= cortex_a_remove_breakpoint
,
2934 .add_watchpoint
= NULL
,
2935 .remove_watchpoint
= NULL
,
2937 .commands
= cortex_r4_command_handlers
,
2938 .target_create
= cortex_r4_target_create
,
2939 .init_target
= cortex_a_init_target
,
2940 .examine
= cortex_a_examine
,