1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
35 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
37 #define CPUDBG_CPUID 0xD00
38 #define CPUDBG_CTYPR 0xD04
39 #define CPUDBG_TTYPR 0xD0C
40 #define CPUDBG_LOCKACCESS 0xFB0
41 #define CPUDBG_LOCKSTATUS 0xFB4
46 #define CORTEX_A8_PADDRDBG_CPU_SHIFT 13
48 struct cortex_a8_brp
{
56 struct cortex_a8_common
{
58 struct arm_jtag jtag_info
;
60 /* Context information */
63 /* Saved cp15 registers */
64 uint32_t cp15_control_reg
;
65 /* latest cp15 register value written and cpsr processor mode */
66 uint32_t cp15_control_reg_curr
;
67 enum arm_mode curr_mode
;
70 /* Breakpoint register pairs */
73 int brp_num_available
;
74 struct cortex_a8_brp
*brp_list
;
76 /* Use cortex_a8_read_regs_through_mem for fast register reads */
79 struct armv7a_common armv7a_common
;
83 static inline struct cortex_a8_common
*
84 target_to_cortex_a8(struct target
*target
)
86 return container_of(target
->arch_info
, struct cortex_a8_common
, armv7a_common
.arm
);
89 #endif /* CORTEX_A8_H */
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