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ARM11: use shared DSCR bit names
[openocd.git] / src / target / cortex_a8.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
30 * *
31 ***************************************************************************/
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include "breakpoints.h"
37 #include "cortex_a8.h"
38 #include "register.h"
39 #include "target_request.h"
40 #include "target_type.h"
41
42 static int cortex_a8_poll(struct target *target);
43 static int cortex_a8_debug_entry(struct target *target);
44 static int cortex_a8_restore_context(struct target *target, bool bpwp);
45 static int cortex_a8_set_breakpoint(struct target *target,
46 struct breakpoint *breakpoint, uint8_t matchmode);
47 static int cortex_a8_unset_breakpoint(struct target *target,
48 struct breakpoint *breakpoint);
49 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
50 uint32_t *value, int regnum);
51 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
52 uint32_t value, int regnum);
53 /*
54 * FIXME do topology discovery using the ROM; don't
55 * assume this is an OMAP3.
56 */
57 #define swjdp_memoryap 0
58 #define swjdp_debugap 1
59 #define OMAP3530_DEBUG_BASE 0x54011000
60
61 /*
62 * Cortex-A8 Basic debug access, very low level assumes state is saved
63 */
64 static int cortex_a8_init_debug_access(struct target *target)
65 {
66 struct armv7a_common *armv7a = target_to_armv7a(target);
67 struct swjdp_common *swjdp = &armv7a->swjdp_info;
68
69 int retval;
70 uint32_t dummy;
71
72 LOG_DEBUG(" ");
73
74 /* Unlocking the debug registers for modification */
75 /* The debugport might be uninitialised so try twice */
76 retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
77 if (retval != ERROR_OK)
78 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
79 /* Clear Sticky Power Down status Bit in PRSR to enable access to
80 the registers in the Core Power Domain */
81 retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
82 /* Enabling of instruction execution in debug mode is done in debug_entry code */
83
84 /* Resync breakpoint registers */
85
86 /* Since this is likley called from init or reset, update targtet state information*/
87 cortex_a8_poll(target);
88
89 return retval;
90 }
91
92 /* To reduce needless round-trips, pass in a pointer to the current
93 * DSCR value. Initialize it to zero if you just need to know the
94 * value on return from this function; or DSCR_INSTR_COMP if you
95 * happen to know that no instruction is pending.
96 */
97 static int cortex_a8_exec_opcode(struct target *target,
98 uint32_t opcode, uint32_t *dscr_p)
99 {
100 uint32_t dscr;
101 int retval;
102 struct armv7a_common *armv7a = target_to_armv7a(target);
103 struct swjdp_common *swjdp = &armv7a->swjdp_info;
104
105 dscr = dscr_p ? *dscr_p : 0;
106
107 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
108
109 /* Wait for InstrCompl bit to be set */
110 while ((dscr & DSCR_INSTR_COMP) == 0)
111 {
112 retval = mem_ap_read_atomic_u32(swjdp,
113 armv7a->debug_base + CPUDBG_DSCR, &dscr);
114 if (retval != ERROR_OK)
115 {
116 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
117 return retval;
118 }
119 }
120
121 mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
122
123 do
124 {
125 retval = mem_ap_read_atomic_u32(swjdp,
126 armv7a->debug_base + CPUDBG_DSCR, &dscr);
127 if (retval != ERROR_OK)
128 {
129 LOG_ERROR("Could not read DSCR register");
130 return retval;
131 }
132 }
133 while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
134
135 if (dscr_p)
136 *dscr_p = dscr;
137
138 return retval;
139 }
140
141 /**************************************************************************
142 Read core register with very few exec_opcode, fast but needs work_area.
143 This can cause problems with MMU active.
144 **************************************************************************/
145 static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
146 uint32_t * regfile)
147 {
148 int retval = ERROR_OK;
149 struct armv7a_common *armv7a = target_to_armv7a(target);
150 struct swjdp_common *swjdp = &armv7a->swjdp_info;
151
152 cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
153 cortex_a8_dap_write_coreregister_u32(target, address, 0);
154 cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
155 dap_ap_select(swjdp, swjdp_memoryap);
156 mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
157 dap_ap_select(swjdp, swjdp_debugap);
158
159 return retval;
160 }
161
162 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
163 uint32_t *value, int regnum)
164 {
165 int retval = ERROR_OK;
166 uint8_t reg = regnum&0xFF;
167 uint32_t dscr = 0;
168 struct armv7a_common *armv7a = target_to_armv7a(target);
169 struct swjdp_common *swjdp = &armv7a->swjdp_info;
170
171 if (reg > 17)
172 return retval;
173
174 if (reg < 15)
175 {
176 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
177 cortex_a8_exec_opcode(target,
178 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
179 &dscr);
180 }
181 else if (reg == 15)
182 {
183 /* "MOV r0, r15"; then move r0 to DCCTX */
184 cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
185 cortex_a8_exec_opcode(target,
186 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
187 &dscr);
188 }
189 else
190 {
191 /* "MRS r0, CPSR" or "MRS r0, SPSR"
192 * then move r0 to DCCTX
193 */
194 cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
195 cortex_a8_exec_opcode(target,
196 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
197 &dscr);
198 }
199
200 /* Wait for DTRRXfull then read DTRRTX */
201 while ((dscr & DSCR_DTR_TX_FULL) == 0)
202 {
203 retval = mem_ap_read_atomic_u32(swjdp,
204 armv7a->debug_base + CPUDBG_DSCR, &dscr);
205 }
206
207 retval = mem_ap_read_atomic_u32(swjdp,
208 armv7a->debug_base + CPUDBG_DTRTX, value);
209 LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
210
211 return retval;
212 }
213
214 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
215 uint32_t value, int regnum)
216 {
217 int retval = ERROR_OK;
218 uint8_t Rd = regnum&0xFF;
219 uint32_t dscr;
220 struct armv7a_common *armv7a = target_to_armv7a(target);
221 struct swjdp_common *swjdp = &armv7a->swjdp_info;
222
223 LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
224
225 /* Check that DCCRX is not full */
226 retval = mem_ap_read_atomic_u32(swjdp,
227 armv7a->debug_base + CPUDBG_DSCR, &dscr);
228 if (dscr & DSCR_DTR_RX_FULL)
229 {
230 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
231 /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
232 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
233 &dscr);
234 }
235
236 if (Rd > 17)
237 return retval;
238
239 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
240 LOG_DEBUG("write DCC 0x%08" PRIx32, value);
241 retval = mem_ap_write_u32(swjdp,
242 armv7a->debug_base + CPUDBG_DTRRX, value);
243
244 if (Rd < 15)
245 {
246 /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
247 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
248 &dscr);
249 }
250 else if (Rd == 15)
251 {
252 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
253 * then "mov r15, r0"
254 */
255 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
256 &dscr);
257 cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
258 }
259 else
260 {
261 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
262 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
263 */
264 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
265 &dscr);
266 cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
267 &dscr);
268
269 /* "Prefetch flush" after modifying execution status in CPSR */
270 if (Rd == 16)
271 cortex_a8_exec_opcode(target,
272 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
273 &dscr);
274 }
275
276 return retval;
277 }
278
279 /* Write to memory mapped registers directly with no cache or mmu handling */
280 static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
281 {
282 int retval;
283 struct armv7a_common *armv7a = target_to_armv7a(target);
284 struct swjdp_common *swjdp = &armv7a->swjdp_info;
285
286 retval = mem_ap_write_atomic_u32(swjdp, address, value);
287
288 return retval;
289 }
290
291 /*
292 * Cortex-A8 implementation of Debug Programmer's Model
293 *
294 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
295 * so there's no need to poll for it before executing an instruction.
296 *
297 * NOTE that in several of these cases the "stall" mode might be useful.
298 * It'd let us queue a few operations together... prepare/finish might
299 * be the places to enable/disable that mode.
300 */
301
302 static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
303 {
304 return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
305 }
306
307 static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
308 {
309 LOG_DEBUG("write DCC 0x%08" PRIx32, data);
310 return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
311 a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
312 }
313
314 static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
315 uint32_t *dscr_p)
316 {
317 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
318 uint32_t dscr = DSCR_INSTR_COMP;
319 int retval;
320
321 if (dscr_p)
322 dscr = *dscr_p;
323
324 /* Wait for DTRRXfull */
325 while ((dscr & DSCR_DTR_TX_FULL) == 0) {
326 retval = mem_ap_read_atomic_u32(swjdp,
327 a8->armv7a_common.debug_base + CPUDBG_DSCR,
328 &dscr);
329 }
330
331 retval = mem_ap_read_atomic_u32(swjdp,
332 a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
333 //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
334
335 if (dscr_p)
336 *dscr_p = dscr;
337
338 return retval;
339 }
340
341 static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
342 {
343 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
344 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
345 uint32_t dscr;
346 int retval;
347
348 /* set up invariant: INSTR_COMP is set after ever DPM operation */
349 do {
350 retval = mem_ap_read_atomic_u32(swjdp,
351 a8->armv7a_common.debug_base + CPUDBG_DSCR,
352 &dscr);
353 } while ((dscr & DSCR_INSTR_COMP) == 0);
354
355 /* this "should never happen" ... */
356 if (dscr & DSCR_DTR_RX_FULL) {
357 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
358 /* Clear DCCRX */
359 retval = cortex_a8_exec_opcode(
360 a8->armv7a_common.armv4_5_common.target,
361 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
362 &dscr);
363 }
364
365 return retval;
366 }
367
368 static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
369 {
370 /* REVISIT what could be done here? */
371 return ERROR_OK;
372 }
373
374 static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
375 uint32_t opcode, uint32_t data)
376 {
377 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
378 int retval;
379 uint32_t dscr = DSCR_INSTR_COMP;
380
381 retval = cortex_a8_write_dcc(a8, data);
382
383 return cortex_a8_exec_opcode(
384 a8->armv7a_common.armv4_5_common.target,
385 opcode,
386 &dscr);
387 }
388
389 static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
390 uint32_t opcode, uint32_t data)
391 {
392 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
393 uint32_t dscr = DSCR_INSTR_COMP;
394 int retval;
395
396 retval = cortex_a8_write_dcc(a8, data);
397
398 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
399 retval = cortex_a8_exec_opcode(
400 a8->armv7a_common.armv4_5_common.target,
401 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
402 &dscr);
403
404 /* then the opcode, taking data from R0 */
405 retval = cortex_a8_exec_opcode(
406 a8->armv7a_common.armv4_5_common.target,
407 opcode,
408 &dscr);
409
410 return retval;
411 }
412
413 static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
414 {
415 struct target *target = dpm->arm->target;
416 uint32_t dscr = DSCR_INSTR_COMP;
417
418 /* "Prefetch flush" after modifying execution status in CPSR */
419 return cortex_a8_exec_opcode(target,
420 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
421 &dscr);
422 }
423
424 static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
425 uint32_t opcode, uint32_t *data)
426 {
427 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
428 int retval;
429 uint32_t dscr = DSCR_INSTR_COMP;
430
431 /* the opcode, writing data to DCC */
432 retval = cortex_a8_exec_opcode(
433 a8->armv7a_common.armv4_5_common.target,
434 opcode,
435 &dscr);
436
437 return cortex_a8_read_dcc(a8, data, &dscr);
438 }
439
440
441 static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
442 uint32_t opcode, uint32_t *data)
443 {
444 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
445 uint32_t dscr = DSCR_INSTR_COMP;
446 int retval;
447
448 /* the opcode, writing data to R0 */
449 retval = cortex_a8_exec_opcode(
450 a8->armv7a_common.armv4_5_common.target,
451 opcode,
452 &dscr);
453
454 /* write R0 to DCC */
455 retval = cortex_a8_exec_opcode(
456 a8->armv7a_common.armv4_5_common.target,
457 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
458 &dscr);
459
460 return cortex_a8_read_dcc(a8, data, &dscr);
461 }
462
463 static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
464 uint32_t addr, uint32_t control)
465 {
466 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
467 uint32_t vr = a8->armv7a_common.debug_base;
468 uint32_t cr = a8->armv7a_common.debug_base;
469 int retval;
470
471 switch (index) {
472 case 0 ... 15: /* breakpoints */
473 vr += CPUDBG_BVR_BASE;
474 cr += CPUDBG_BCR_BASE;
475 break;
476 case 16 ... 31: /* watchpoints */
477 vr += CPUDBG_WVR_BASE;
478 cr += CPUDBG_WCR_BASE;
479 index -= 16;
480 break;
481 default:
482 return ERROR_FAIL;
483 }
484 vr += 4 * index;
485 cr += 4 * index;
486
487 LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
488 (unsigned) vr, (unsigned) cr);
489
490 retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
491 vr, addr);
492 if (retval != ERROR_OK)
493 return retval;
494 retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
495 cr, control);
496 return retval;
497 }
498
499 static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
500 {
501 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
502 uint32_t cr;
503
504 switch (index) {
505 case 0 ... 15:
506 cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
507 break;
508 case 16 ... 31:
509 cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
510 index -= 16;
511 break;
512 default:
513 return ERROR_FAIL;
514 }
515 cr += 4 * index;
516
517 LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
518
519 /* clear control register */
520 return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
521 }
522
523 static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
524 {
525 struct arm_dpm *dpm = &a8->armv7a_common.dpm;
526 int retval;
527
528 dpm->arm = &a8->armv7a_common.armv4_5_common;
529 dpm->didr = didr;
530
531 dpm->prepare = cortex_a8_dpm_prepare;
532 dpm->finish = cortex_a8_dpm_finish;
533
534 dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
535 dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
536 dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
537
538 dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
539 dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
540
541 dpm->bpwp_enable = cortex_a8_bpwp_enable;
542 dpm->bpwp_disable = cortex_a8_bpwp_disable;
543
544 retval = arm_dpm_setup(dpm);
545 if (retval == ERROR_OK)
546 retval = arm_dpm_initialize(dpm);
547
548 return retval;
549 }
550
551
552 /*
553 * Cortex-A8 Run control
554 */
555
556 static int cortex_a8_poll(struct target *target)
557 {
558 int retval = ERROR_OK;
559 uint32_t dscr;
560 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
561 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
562 struct swjdp_common *swjdp = &armv7a->swjdp_info;
563 enum target_state prev_target_state = target->state;
564 uint8_t saved_apsel = dap_ap_get_select(swjdp);
565
566 dap_ap_select(swjdp, swjdp_debugap);
567 retval = mem_ap_read_atomic_u32(swjdp,
568 armv7a->debug_base + CPUDBG_DSCR, &dscr);
569 if (retval != ERROR_OK)
570 {
571 dap_ap_select(swjdp, saved_apsel);
572 return retval;
573 }
574 cortex_a8->cpudbg_dscr = dscr;
575
576 if ((dscr & 0x3) == 0x3)
577 {
578 if (prev_target_state != TARGET_HALTED)
579 {
580 /* We have a halting debug event */
581 LOG_DEBUG("Target halted");
582 target->state = TARGET_HALTED;
583 if ((prev_target_state == TARGET_RUNNING)
584 || (prev_target_state == TARGET_RESET))
585 {
586 retval = cortex_a8_debug_entry(target);
587 if (retval != ERROR_OK)
588 return retval;
589
590 target_call_event_callbacks(target,
591 TARGET_EVENT_HALTED);
592 }
593 if (prev_target_state == TARGET_DEBUG_RUNNING)
594 {
595 LOG_DEBUG(" ");
596
597 retval = cortex_a8_debug_entry(target);
598 if (retval != ERROR_OK)
599 return retval;
600
601 target_call_event_callbacks(target,
602 TARGET_EVENT_DEBUG_HALTED);
603 }
604 }
605 }
606 else if ((dscr & 0x3) == 0x2)
607 {
608 target->state = TARGET_RUNNING;
609 }
610 else
611 {
612 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
613 target->state = TARGET_UNKNOWN;
614 }
615
616 dap_ap_select(swjdp, saved_apsel);
617
618 return retval;
619 }
620
621 static int cortex_a8_halt(struct target *target)
622 {
623 int retval = ERROR_OK;
624 uint32_t dscr;
625 struct armv7a_common *armv7a = target_to_armv7a(target);
626 struct swjdp_common *swjdp = &armv7a->swjdp_info;
627 uint8_t saved_apsel = dap_ap_get_select(swjdp);
628 dap_ap_select(swjdp, swjdp_debugap);
629
630 /*
631 * Tell the core to be halted by writing DRCR with 0x1
632 * and then wait for the core to be halted.
633 */
634 retval = mem_ap_write_atomic_u32(swjdp,
635 armv7a->debug_base + CPUDBG_DRCR, 0x1);
636
637 /*
638 * enter halting debug mode
639 */
640 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
641 retval = mem_ap_write_atomic_u32(swjdp,
642 armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
643
644 if (retval != ERROR_OK)
645 goto out;
646
647 do {
648 mem_ap_read_atomic_u32(swjdp,
649 armv7a->debug_base + CPUDBG_DSCR, &dscr);
650 } while ((dscr & DSCR_CORE_HALTED) == 0);
651
652 target->debug_reason = DBG_REASON_DBGRQ;
653
654 out:
655 dap_ap_select(swjdp, saved_apsel);
656 return retval;
657 }
658
659 static int cortex_a8_resume(struct target *target, int current,
660 uint32_t address, int handle_breakpoints, int debug_execution)
661 {
662 struct armv7a_common *armv7a = target_to_armv7a(target);
663 struct arm *armv4_5 = &armv7a->armv4_5_common;
664 struct swjdp_common *swjdp = &armv7a->swjdp_info;
665
666 // struct breakpoint *breakpoint = NULL;
667 uint32_t resume_pc, dscr;
668
669 uint8_t saved_apsel = dap_ap_get_select(swjdp);
670 dap_ap_select(swjdp, swjdp_debugap);
671
672 if (!debug_execution)
673 target_free_all_working_areas(target);
674
675 #if 0
676 if (debug_execution)
677 {
678 /* Disable interrupts */
679 /* We disable interrupts in the PRIMASK register instead of
680 * masking with C_MASKINTS,
681 * This is probably the same issue as Cortex-M3 Errata 377493:
682 * C_MASKINTS in parallel with disabled interrupts can cause
683 * local faults to not be taken. */
684 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
685 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
686 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
687
688 /* Make sure we are in Thumb mode */
689 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
690 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
691 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
692 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
693 }
694 #endif
695
696 /* current = 1: continue on current pc, otherwise continue at <address> */
697 resume_pc = buf_get_u32(
698 armv4_5->core_cache->reg_list[15].value,
699 0, 32);
700 if (!current)
701 resume_pc = address;
702
703 /* Make sure that the Armv7 gdb thumb fixups does not
704 * kill the return address
705 */
706 switch (armv4_5->core_state)
707 {
708 case ARMV4_5_STATE_ARM:
709 resume_pc &= 0xFFFFFFFC;
710 break;
711 case ARMV4_5_STATE_THUMB:
712 case ARM_STATE_THUMB_EE:
713 /* When the return address is loaded into PC
714 * bit 0 must be 1 to stay in Thumb state
715 */
716 resume_pc |= 0x1;
717 break;
718 case ARMV4_5_STATE_JAZELLE:
719 LOG_ERROR("How do I resume into Jazelle state??");
720 return ERROR_FAIL;
721 }
722 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
723 buf_set_u32(armv4_5->core_cache->reg_list[15].value,
724 0, 32, resume_pc);
725 armv4_5->core_cache->reg_list[15].dirty = 1;
726 armv4_5->core_cache->reg_list[15].valid = 1;
727
728 cortex_a8_restore_context(target, handle_breakpoints);
729
730 #if 0
731 /* the front-end may request us not to handle breakpoints */
732 if (handle_breakpoints)
733 {
734 /* Single step past breakpoint at current address */
735 if ((breakpoint = breakpoint_find(target, resume_pc)))
736 {
737 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
738 cortex_m3_unset_breakpoint(target, breakpoint);
739 cortex_m3_single_step_core(target);
740 cortex_m3_set_breakpoint(target, breakpoint);
741 }
742 }
743
744 #endif
745 /* Restart core and wait for it to be started
746 * NOTE: this clears DSCR_ITR_EN and other bits.
747 *
748 * REVISIT: for single stepping, we probably want to
749 * disable IRQs by default, with optional override...
750 */
751 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
752
753 do {
754 mem_ap_read_atomic_u32(swjdp,
755 armv7a->debug_base + CPUDBG_DSCR, &dscr);
756 } while ((dscr & DSCR_CORE_RESTARTED) == 0);
757
758 target->debug_reason = DBG_REASON_NOTHALTED;
759 target->state = TARGET_RUNNING;
760
761 /* registers are now invalid */
762 register_cache_invalidate(armv4_5->core_cache);
763
764 if (!debug_execution)
765 {
766 target->state = TARGET_RUNNING;
767 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
768 LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
769 }
770 else
771 {
772 target->state = TARGET_DEBUG_RUNNING;
773 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
774 LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
775 }
776
777 dap_ap_select(swjdp, saved_apsel);
778
779 return ERROR_OK;
780 }
781
782 static int cortex_a8_debug_entry(struct target *target)
783 {
784 int i;
785 uint32_t regfile[16], wfar, cpsr, dscr;
786 int retval = ERROR_OK;
787 struct working_area *regfile_working_area = NULL;
788 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
789 struct armv7a_common *armv7a = target_to_armv7a(target);
790 struct arm *armv4_5 = &armv7a->armv4_5_common;
791 struct swjdp_common *swjdp = &armv7a->swjdp_info;
792 struct reg *reg;
793
794 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
795
796 mem_ap_read_atomic_u32(swjdp,
797 armv7a->debug_base + CPUDBG_DSCR, &dscr);
798
799 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
800 * imprecise data aborts get discarded by issuing a Data
801 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
802 */
803
804 /* Enable the ITR execution once we are in debug mode */
805 dscr |= DSCR_ITR_EN;
806 retval = mem_ap_write_atomic_u32(swjdp,
807 armv7a->debug_base + CPUDBG_DSCR, dscr);
808
809 /* Examine debug reason */
810 switch (DSCR_ENTRY(cortex_a8->cpudbg_dscr))
811 {
812 case 0: /* DRCR[0] write */
813 case 4: /* EDBGRQ */
814 target->debug_reason = DBG_REASON_DBGRQ;
815 break;
816 case 1: /* HW breakpoint */
817 case 3: /* SW BKPT */
818 case 5: /* vector catch */
819 target->debug_reason = DBG_REASON_BREAKPOINT;
820 break;
821 case 2: /* asynch watchpoint */
822 case 10: /* precise watchpoint */
823 target->debug_reason = DBG_REASON_WATCHPOINT;
824
825 /* save address of faulting instruction */
826 retval = mem_ap_read_atomic_u32(swjdp,
827 armv7a->debug_base + CPUDBG_WFAR,
828 &wfar);
829 arm_dpm_report_wfar(&armv7a->dpm, wfar);
830 break;
831 default:
832 target->debug_reason = DBG_REASON_UNDEFINED;
833 break;
834 }
835
836 /* REVISIT fast_reg_read is never set ... */
837
838 /* Examine target state and mode */
839 if (cortex_a8->fast_reg_read)
840 target_alloc_working_area(target, 64, &regfile_working_area);
841
842 /* First load register acessible through core debug port*/
843 if (!regfile_working_area)
844 {
845 retval = arm_dpm_read_current_registers(&armv7a->dpm);
846 }
847 else
848 {
849 dap_ap_select(swjdp, swjdp_memoryap);
850 cortex_a8_read_regs_through_mem(target,
851 regfile_working_area->address, regfile);
852 dap_ap_select(swjdp, swjdp_memoryap);
853 target_free_working_area(target, regfile_working_area);
854
855 /* read Current PSR */
856 cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
857 dap_ap_select(swjdp, swjdp_debugap);
858 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
859
860 arm_set_cpsr(armv4_5, cpsr);
861
862 /* update cache */
863 for (i = 0; i <= ARM_PC; i++)
864 {
865 reg = arm_reg_current(armv4_5, i);
866
867 buf_set_u32(reg->value, 0, 32, regfile[i]);
868 reg->valid = 1;
869 reg->dirty = 0;
870 }
871
872 /* Fixup PC Resume Address */
873 if (cpsr & (1 << 5))
874 {
875 // T bit set for Thumb or ThumbEE state
876 regfile[ARM_PC] -= 4;
877 }
878 else
879 {
880 // ARM state
881 regfile[ARM_PC] -= 8;
882 }
883
884 reg = armv4_5->core_cache->reg_list + 15;
885 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
886 reg->dirty = reg->valid;
887 }
888
889 #if 0
890 /* TODO, Move this */
891 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
892 cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
893 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
894
895 cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
896 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
897
898 cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
899 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
900 #endif
901
902 /* Are we in an exception handler */
903 // armv4_5->exception_number = 0;
904 if (armv7a->post_debug_entry)
905 armv7a->post_debug_entry(target);
906
907 return retval;
908 }
909
910 static void cortex_a8_post_debug_entry(struct target *target)
911 {
912 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
913 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
914 int retval;
915
916 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
917 retval = armv7a->armv4_5_common.mrc(target, 15,
918 0, 0, /* op1, op2 */
919 1, 0, /* CRn, CRm */
920 &cortex_a8->cp15_control_reg);
921 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
922
923 if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
924 {
925 uint32_t cache_type_reg;
926
927 /* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
928 retval = armv7a->armv4_5_common.mrc(target, 15,
929 0, 1, /* op1, op2 */
930 0, 0, /* CRn, CRm */
931 &cache_type_reg);
932 LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
933
934 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
935 armv4_5_identify_cache(cache_type_reg,
936 &armv7a->armv4_5_mmu.armv4_5_cache);
937 }
938
939 armv7a->armv4_5_mmu.mmu_enabled =
940 (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
941 armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
942 (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
943 armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
944 (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
945
946
947 }
948
949 static int cortex_a8_step(struct target *target, int current, uint32_t address,
950 int handle_breakpoints)
951 {
952 struct armv7a_common *armv7a = target_to_armv7a(target);
953 struct arm *armv4_5 = &armv7a->armv4_5_common;
954 struct breakpoint *breakpoint = NULL;
955 struct breakpoint stepbreakpoint;
956 struct reg *r;
957
958 int timeout = 100;
959
960 if (target->state != TARGET_HALTED)
961 {
962 LOG_WARNING("target not halted");
963 return ERROR_TARGET_NOT_HALTED;
964 }
965
966 /* current = 1: continue on current pc, otherwise continue at <address> */
967 r = armv4_5->core_cache->reg_list + 15;
968 if (!current)
969 {
970 buf_set_u32(r->value, 0, 32, address);
971 }
972 else
973 {
974 address = buf_get_u32(r->value, 0, 32);
975 }
976
977 /* The front-end may request us not to handle breakpoints.
978 * But since Cortex-A8 uses breakpoint for single step,
979 * we MUST handle breakpoints.
980 */
981 handle_breakpoints = 1;
982 if (handle_breakpoints) {
983 breakpoint = breakpoint_find(target, address);
984 if (breakpoint)
985 cortex_a8_unset_breakpoint(target, breakpoint);
986 }
987
988 /* Setup single step breakpoint */
989 stepbreakpoint.address = address;
990 stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
991 ? 2 : 4;
992 stepbreakpoint.type = BKPT_HARD;
993 stepbreakpoint.set = 0;
994
995 /* Break on IVA mismatch */
996 cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
997
998 target->debug_reason = DBG_REASON_SINGLESTEP;
999
1000 cortex_a8_resume(target, 1, address, 0, 0);
1001
1002 while (target->state != TARGET_HALTED)
1003 {
1004 cortex_a8_poll(target);
1005 if (--timeout == 0)
1006 {
1007 LOG_WARNING("timeout waiting for target halt");
1008 break;
1009 }
1010 }
1011
1012 cortex_a8_unset_breakpoint(target, &stepbreakpoint);
1013 if (timeout > 0)
1014 target->debug_reason = DBG_REASON_BREAKPOINT;
1015
1016 if (breakpoint)
1017 cortex_a8_set_breakpoint(target, breakpoint, 0);
1018
1019 if (target->state != TARGET_HALTED)
1020 LOG_DEBUG("target stepped");
1021
1022 return ERROR_OK;
1023 }
1024
1025 static int cortex_a8_restore_context(struct target *target, bool bpwp)
1026 {
1027 struct armv7a_common *armv7a = target_to_armv7a(target);
1028
1029 LOG_DEBUG(" ");
1030
1031 if (armv7a->pre_restore_context)
1032 armv7a->pre_restore_context(target);
1033
1034 arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
1035
1036 if (armv7a->post_restore_context)
1037 armv7a->post_restore_context(target);
1038
1039 return ERROR_OK;
1040 }
1041
1042
1043 /*
1044 * Cortex-A8 Breakpoint and watchpoint fuctions
1045 */
1046
1047 /* Setup hardware Breakpoint Register Pair */
1048 static int cortex_a8_set_breakpoint(struct target *target,
1049 struct breakpoint *breakpoint, uint8_t matchmode)
1050 {
1051 int retval;
1052 int brp_i=0;
1053 uint32_t control;
1054 uint8_t byte_addr_select = 0x0F;
1055 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1056 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1057 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1058
1059 if (breakpoint->set)
1060 {
1061 LOG_WARNING("breakpoint already set");
1062 return ERROR_OK;
1063 }
1064
1065 if (breakpoint->type == BKPT_HARD)
1066 {
1067 while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
1068 brp_i++ ;
1069 if (brp_i >= cortex_a8->brp_num)
1070 {
1071 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1072 return ERROR_FAIL;
1073 }
1074 breakpoint->set = brp_i + 1;
1075 if (breakpoint->length == 2)
1076 {
1077 byte_addr_select = (3 << (breakpoint->address & 0x02));
1078 }
1079 control = ((matchmode & 0x7) << 20)
1080 | (byte_addr_select << 5)
1081 | (3 << 1) | 1;
1082 brp_list[brp_i].used = 1;
1083 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1084 brp_list[brp_i].control = control;
1085 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1086 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1087 brp_list[brp_i].value);
1088 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1089 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1090 brp_list[brp_i].control);
1091 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1092 brp_list[brp_i].control,
1093 brp_list[brp_i].value);
1094 }
1095 else if (breakpoint->type == BKPT_SOFT)
1096 {
1097 uint8_t code[4];
1098 if (breakpoint->length == 2)
1099 {
1100 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1101 }
1102 else
1103 {
1104 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1105 }
1106 retval = target->type->read_memory(target,
1107 breakpoint->address & 0xFFFFFFFE,
1108 breakpoint->length, 1,
1109 breakpoint->orig_instr);
1110 if (retval != ERROR_OK)
1111 return retval;
1112 retval = target->type->write_memory(target,
1113 breakpoint->address & 0xFFFFFFFE,
1114 breakpoint->length, 1, code);
1115 if (retval != ERROR_OK)
1116 return retval;
1117 breakpoint->set = 0x11; /* Any nice value but 0 */
1118 }
1119
1120 return ERROR_OK;
1121 }
1122
1123 static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1124 {
1125 int retval;
1126 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1127 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1128 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1129
1130 if (!breakpoint->set)
1131 {
1132 LOG_WARNING("breakpoint not set");
1133 return ERROR_OK;
1134 }
1135
1136 if (breakpoint->type == BKPT_HARD)
1137 {
1138 int brp_i = breakpoint->set - 1;
1139 if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
1140 {
1141 LOG_DEBUG("Invalid BRP number in breakpoint");
1142 return ERROR_OK;
1143 }
1144 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1145 brp_list[brp_i].control, brp_list[brp_i].value);
1146 brp_list[brp_i].used = 0;
1147 brp_list[brp_i].value = 0;
1148 brp_list[brp_i].control = 0;
1149 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1150 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1151 brp_list[brp_i].control);
1152 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1153 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1154 brp_list[brp_i].value);
1155 }
1156 else
1157 {
1158 /* restore original instruction (kept in target endianness) */
1159 if (breakpoint->length == 4)
1160 {
1161 retval = target->type->write_memory(target,
1162 breakpoint->address & 0xFFFFFFFE,
1163 4, 1, breakpoint->orig_instr);
1164 if (retval != ERROR_OK)
1165 return retval;
1166 }
1167 else
1168 {
1169 retval = target->type->write_memory(target,
1170 breakpoint->address & 0xFFFFFFFE,
1171 2, 1, breakpoint->orig_instr);
1172 if (retval != ERROR_OK)
1173 return retval;
1174 }
1175 }
1176 breakpoint->set = 0;
1177
1178 return ERROR_OK;
1179 }
1180
1181 static int cortex_a8_add_breakpoint(struct target *target,
1182 struct breakpoint *breakpoint)
1183 {
1184 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1185
1186 if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
1187 {
1188 LOG_INFO("no hardware breakpoint available");
1189 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1190 }
1191
1192 if (breakpoint->type == BKPT_HARD)
1193 cortex_a8->brp_num_available--;
1194 cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1195
1196 return ERROR_OK;
1197 }
1198
1199 static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1200 {
1201 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1202
1203 #if 0
1204 /* It is perfectly possible to remove brakpoints while the taget is running */
1205 if (target->state != TARGET_HALTED)
1206 {
1207 LOG_WARNING("target not halted");
1208 return ERROR_TARGET_NOT_HALTED;
1209 }
1210 #endif
1211
1212 if (breakpoint->set)
1213 {
1214 cortex_a8_unset_breakpoint(target, breakpoint);
1215 if (breakpoint->type == BKPT_HARD)
1216 cortex_a8->brp_num_available++ ;
1217 }
1218
1219
1220 return ERROR_OK;
1221 }
1222
1223
1224
1225 /*
1226 * Cortex-A8 Reset fuctions
1227 */
1228
1229 static int cortex_a8_assert_reset(struct target *target)
1230 {
1231 struct armv7a_common *armv7a = target_to_armv7a(target);
1232
1233 LOG_DEBUG(" ");
1234
1235 /* FIXME when halt is requested, make it work somehow... */
1236
1237 /* Issue some kind of warm reset. */
1238 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1239 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1240 } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1241 /* REVISIT handle "pulls" cases, if there's
1242 * hardware that needs them to work.
1243 */
1244 jtag_add_reset(0, 1);
1245 } else {
1246 LOG_ERROR("%s: how to reset?", target_name(target));
1247 return ERROR_FAIL;
1248 }
1249
1250 /* registers are now invalid */
1251 register_cache_invalidate(armv7a->armv4_5_common.core_cache);
1252
1253 target->state = TARGET_RESET;
1254
1255 return ERROR_OK;
1256 }
1257
1258 static int cortex_a8_deassert_reset(struct target *target)
1259 {
1260 int retval;
1261
1262 LOG_DEBUG(" ");
1263
1264 /* be certain SRST is off */
1265 jtag_add_reset(0, 0);
1266
1267 retval = cortex_a8_poll(target);
1268
1269 if (target->reset_halt) {
1270 if (target->state != TARGET_HALTED) {
1271 LOG_WARNING("%s: ran after reset and before halt ...",
1272 target_name(target));
1273 if ((retval = target_halt(target)) != ERROR_OK)
1274 return retval;
1275 }
1276 }
1277
1278 return ERROR_OK;
1279 }
1280
1281 /*
1282 * Cortex-A8 Memory access
1283 *
1284 * This is same Cortex M3 but we must also use the correct
1285 * ap number for every access.
1286 */
1287
1288 static int cortex_a8_read_memory(struct target *target, uint32_t address,
1289 uint32_t size, uint32_t count, uint8_t *buffer)
1290 {
1291 struct armv7a_common *armv7a = target_to_armv7a(target);
1292 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1293 int retval = ERROR_INVALID_ARGUMENTS;
1294
1295 /* cortex_a8 handles unaligned memory access */
1296
1297 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1298
1299 if (count && buffer) {
1300 switch (size) {
1301 case 4:
1302 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1303 break;
1304 case 2:
1305 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1306 break;
1307 case 1:
1308 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1309 break;
1310 }
1311 }
1312
1313 return retval;
1314 }
1315
1316 static int cortex_a8_write_memory(struct target *target, uint32_t address,
1317 uint32_t size, uint32_t count, uint8_t *buffer)
1318 {
1319 struct armv7a_common *armv7a = target_to_armv7a(target);
1320 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1321 int retval = ERROR_INVALID_ARGUMENTS;
1322
1323 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1324
1325 if (count && buffer) {
1326 switch (size) {
1327 case 4:
1328 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1329 break;
1330 case 2:
1331 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1332 break;
1333 case 1:
1334 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1335 break;
1336 }
1337 }
1338
1339 /* REVISIT this op is generic ARMv7-A/R stuff */
1340 if (retval == ERROR_OK && target->state == TARGET_HALTED)
1341 {
1342 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
1343
1344 retval = dpm->prepare(dpm);
1345 if (retval != ERROR_OK)
1346 return retval;
1347
1348 /* The Cache handling will NOT work with MMU active, the
1349 * wrong addresses will be invalidated!
1350 *
1351 * For both ICache and DCache, walk all cache lines in the
1352 * address range. Cortex-A8 has fixed 64 byte line length.
1353 *
1354 * REVISIT per ARMv7, these may trigger watchpoints ...
1355 */
1356
1357 /* invalidate I-Cache */
1358 if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
1359 {
1360 /* ICIMVAU - Invalidate Cache single entry
1361 * with MVA to PoU
1362 * MCR p15, 0, r0, c7, c5, 1
1363 */
1364 for (uint32_t cacheline = address;
1365 cacheline < address + size * count;
1366 cacheline += 64) {
1367 retval = dpm->instr_write_data_r0(dpm,
1368 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
1369 cacheline);
1370 }
1371 }
1372
1373 /* invalidate D-Cache */
1374 if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
1375 {
1376 /* DCIMVAC - Invalidate data Cache line
1377 * with MVA to PoC
1378 * MCR p15, 0, r0, c7, c6, 1
1379 */
1380 for (uint32_t cacheline = address;
1381 cacheline < address + size * count;
1382 cacheline += 64) {
1383 retval = dpm->instr_write_data_r0(dpm,
1384 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
1385 cacheline);
1386 }
1387 }
1388
1389 /* (void) */ dpm->finish(dpm);
1390 }
1391
1392 return retval;
1393 }
1394
1395 static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
1396 uint32_t count, uint8_t *buffer)
1397 {
1398 return cortex_a8_write_memory(target, address, 4, count, buffer);
1399 }
1400
1401
1402 static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1403 {
1404 #if 0
1405 u16 dcrdr;
1406
1407 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1408 *ctrl = (uint8_t)dcrdr;
1409 *value = (uint8_t)(dcrdr >> 8);
1410
1411 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1412
1413 /* write ack back to software dcc register
1414 * signify we have read data */
1415 if (dcrdr & (1 << 0))
1416 {
1417 dcrdr = 0;
1418 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1419 }
1420 #endif
1421 return ERROR_OK;
1422 }
1423
1424
1425 static int cortex_a8_handle_target_request(void *priv)
1426 {
1427 struct target *target = priv;
1428 struct armv7a_common *armv7a = target_to_armv7a(target);
1429 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1430
1431 if (!target_was_examined(target))
1432 return ERROR_OK;
1433 if (!target->dbg_msg_enabled)
1434 return ERROR_OK;
1435
1436 if (target->state == TARGET_RUNNING)
1437 {
1438 uint8_t data = 0;
1439 uint8_t ctrl = 0;
1440
1441 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1442
1443 /* check if we have data */
1444 if (ctrl & (1 << 0))
1445 {
1446 uint32_t request;
1447
1448 /* we assume target is quick enough */
1449 request = data;
1450 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1451 request |= (data << 8);
1452 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1453 request |= (data << 16);
1454 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1455 request |= (data << 24);
1456 target_request(target, request);
1457 }
1458 }
1459
1460 return ERROR_OK;
1461 }
1462
1463 /*
1464 * Cortex-A8 target information and configuration
1465 */
1466
1467 static int cortex_a8_examine_first(struct target *target)
1468 {
1469 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1470 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1471 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1472 int i;
1473 int retval = ERROR_OK;
1474 uint32_t didr, ctypr, ttypr, cpuid;
1475
1476 LOG_DEBUG("TODO");
1477
1478 /* Here we shall insert a proper ROM Table scan */
1479 armv7a->debug_base = OMAP3530_DEBUG_BASE;
1480
1481 /* We do one extra read to ensure DAP is configured,
1482 * we call ahbap_debugport_init(swjdp) instead
1483 */
1484 ahbap_debugport_init(swjdp);
1485 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
1486 if ((retval = mem_ap_read_atomic_u32(swjdp,
1487 armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
1488 {
1489 LOG_DEBUG("Examine failed");
1490 return retval;
1491 }
1492
1493 if ((retval = mem_ap_read_atomic_u32(swjdp,
1494 armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
1495 {
1496 LOG_DEBUG("Examine failed");
1497 return retval;
1498 }
1499
1500 if ((retval = mem_ap_read_atomic_u32(swjdp,
1501 armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
1502 {
1503 LOG_DEBUG("Examine failed");
1504 return retval;
1505 }
1506
1507 if ((retval = mem_ap_read_atomic_u32(swjdp,
1508 armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
1509 {
1510 LOG_DEBUG("Examine failed");
1511 return retval;
1512 }
1513
1514 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
1515 LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
1516 LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
1517 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
1518
1519 armv7a->armv4_5_common.core_type = ARM_MODE_MON;
1520 cortex_a8_dpm_setup(cortex_a8, didr);
1521
1522 /* Setup Breakpoint Register Pairs */
1523 cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
1524 cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
1525 cortex_a8->brp_num_available = cortex_a8->brp_num;
1526 cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
1527 // cortex_a8->brb_enabled = ????;
1528 for (i = 0; i < cortex_a8->brp_num; i++)
1529 {
1530 cortex_a8->brp_list[i].used = 0;
1531 if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
1532 cortex_a8->brp_list[i].type = BRP_NORMAL;
1533 else
1534 cortex_a8->brp_list[i].type = BRP_CONTEXT;
1535 cortex_a8->brp_list[i].value = 0;
1536 cortex_a8->brp_list[i].control = 0;
1537 cortex_a8->brp_list[i].BRPn = i;
1538 }
1539
1540 LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num);
1541
1542 target_set_examined(target);
1543 return ERROR_OK;
1544 }
1545
1546 static int cortex_a8_examine(struct target *target)
1547 {
1548 int retval = ERROR_OK;
1549
1550 /* don't re-probe hardware after each reset */
1551 if (!target_was_examined(target))
1552 retval = cortex_a8_examine_first(target);
1553
1554 /* Configure core debug access */
1555 if (retval == ERROR_OK)
1556 retval = cortex_a8_init_debug_access(target);
1557
1558 return retval;
1559 }
1560
1561 /*
1562 * Cortex-A8 target creation and initialization
1563 */
1564
1565 static int cortex_a8_init_target(struct command_context *cmd_ctx,
1566 struct target *target)
1567 {
1568 /* examine_first() does a bunch of this */
1569 return ERROR_OK;
1570 }
1571
1572 static int cortex_a8_init_arch_info(struct target *target,
1573 struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
1574 {
1575 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1576 struct arm *armv4_5 = &armv7a->armv4_5_common;
1577 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1578
1579 /* Setup struct cortex_a8_common */
1580 cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
1581 armv4_5->arch_info = armv7a;
1582
1583 /* prepare JTAG information for the new target */
1584 cortex_a8->jtag_info.tap = tap;
1585 cortex_a8->jtag_info.scann_size = 4;
1586
1587 swjdp->dp_select_value = -1;
1588 swjdp->ap_csw_value = -1;
1589 swjdp->ap_tar_value = -1;
1590 swjdp->jtag_info = &cortex_a8->jtag_info;
1591 swjdp->memaccess_tck = 80;
1592
1593 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1594 swjdp->tar_autoincr_block = (1 << 10);
1595
1596 cortex_a8->fast_reg_read = 0;
1597
1598 /* register arch-specific functions */
1599 armv7a->examine_debug_reason = NULL;
1600
1601 armv7a->post_debug_entry = cortex_a8_post_debug_entry;
1602
1603 armv7a->pre_restore_context = NULL;
1604 armv7a->post_restore_context = NULL;
1605 armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
1606 // armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
1607 armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
1608 armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
1609 // armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
1610 // armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
1611 armv7a->armv4_5_mmu.has_tiny_pages = 1;
1612 armv7a->armv4_5_mmu.mmu_enabled = 0;
1613
1614
1615 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
1616
1617 /* REVISIT v7a setup should be in a v7a-specific routine */
1618 armv4_5_init_arch_info(target, armv4_5);
1619 armv7a->common_magic = ARMV7_COMMON_MAGIC;
1620
1621 target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
1622
1623 return ERROR_OK;
1624 }
1625
1626 static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
1627 {
1628 struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
1629
1630 cortex_a8_init_arch_info(target, cortex_a8, target->tap);
1631
1632 return ERROR_OK;
1633 }
1634
1635 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
1636 {
1637 struct target *target = get_current_target(CMD_CTX);
1638 struct armv7a_common *armv7a = target_to_armv7a(target);
1639
1640 return armv4_5_handle_cache_info_command(CMD_CTX,
1641 &armv7a->armv4_5_mmu.armv4_5_cache);
1642 }
1643
1644
1645 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
1646 {
1647 struct target *target = get_current_target(CMD_CTX);
1648
1649 cortex_a8_init_debug_access(target);
1650
1651 return ERROR_OK;
1652 }
1653
1654 static const struct command_registration cortex_a8_exec_command_handlers[] = {
1655 {
1656 .name = "cache_info",
1657 .handler = &cortex_a8_handle_cache_info_command,
1658 .mode = COMMAND_EXEC,
1659 .help = "display information about target caches",
1660 },
1661 {
1662 .name = "dbginit",
1663 .handler = &cortex_a8_handle_dbginit_command,
1664 .mode = COMMAND_EXEC,
1665 .help = "Initialize core debug",
1666 },
1667 COMMAND_REGISTRATION_DONE
1668 };
1669 static const struct command_registration cortex_a8_command_handlers[] = {
1670 {
1671 .chain = arm_command_handlers,
1672 },
1673 {
1674 .chain = armv7a_command_handlers,
1675 },
1676 {
1677 .name = "cortex_a8",
1678 .mode = COMMAND_ANY,
1679 .help = "Cortex-A8 command group",
1680 .chain = cortex_a8_exec_command_handlers,
1681 },
1682 COMMAND_REGISTRATION_DONE
1683 };
1684
1685 struct target_type cortexa8_target = {
1686 .name = "cortex_a8",
1687
1688 .poll = cortex_a8_poll,
1689 .arch_state = armv7a_arch_state,
1690
1691 .target_request_data = NULL,
1692
1693 .halt = cortex_a8_halt,
1694 .resume = cortex_a8_resume,
1695 .step = cortex_a8_step,
1696
1697 .assert_reset = cortex_a8_assert_reset,
1698 .deassert_reset = cortex_a8_deassert_reset,
1699 .soft_reset_halt = NULL,
1700
1701 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1702
1703 .read_memory = cortex_a8_read_memory,
1704 .write_memory = cortex_a8_write_memory,
1705 .bulk_write_memory = cortex_a8_bulk_write_memory,
1706
1707 .checksum_memory = arm_checksum_memory,
1708 .blank_check_memory = arm_blank_check_memory,
1709
1710 .run_algorithm = armv4_5_run_algorithm,
1711
1712 .add_breakpoint = cortex_a8_add_breakpoint,
1713 .remove_breakpoint = cortex_a8_remove_breakpoint,
1714 .add_watchpoint = NULL,
1715 .remove_watchpoint = NULL,
1716
1717 .commands = cortex_a8_command_handlers,
1718 .target_create = cortex_a8_target_create,
1719 .init_target = cortex_a8_init_target,
1720 .examine = cortex_a8_examine,
1721 };
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