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[openocd.git] / src / target / cortex_a8.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
30 * *
31 ***************************************************************************/
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include "breakpoints.h"
37 #include "cortex_a8.h"
38 #include "register.h"
39 #include "target_request.h"
40 #include "target_type.h"
41
42 static int cortex_a8_poll(struct target *target);
43 static int cortex_a8_debug_entry(struct target *target);
44 static int cortex_a8_restore_context(struct target *target, bool bpwp);
45 static int cortex_a8_set_breakpoint(struct target *target,
46 struct breakpoint *breakpoint, uint8_t matchmode);
47 static int cortex_a8_unset_breakpoint(struct target *target,
48 struct breakpoint *breakpoint);
49 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
50 uint32_t *value, int regnum);
51 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
52 uint32_t value, int regnum);
53 /*
54 * FIXME do topology discovery using the ROM; don't
55 * assume this is an OMAP3.
56 */
57 #define swjdp_memoryap 0
58 #define swjdp_debugap 1
59 #define OMAP3530_DEBUG_BASE 0x54011000
60
61 /*
62 * Cortex-A8 Basic debug access, very low level assumes state is saved
63 */
64 static int cortex_a8_init_debug_access(struct target *target)
65 {
66 struct armv7a_common *armv7a = target_to_armv7a(target);
67 struct swjdp_common *swjdp = &armv7a->swjdp_info;
68
69 int retval;
70 uint32_t dummy;
71
72 LOG_DEBUG(" ");
73
74 /* Unlocking the debug registers for modification */
75 /* The debugport might be uninitialised so try twice */
76 retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
77 if (retval != ERROR_OK)
78 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
79 /* Clear Sticky Power Down status Bit in PRSR to enable access to
80 the registers in the Core Power Domain */
81 retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
82 /* Enabling of instruction execution in debug mode is done in debug_entry code */
83
84 /* Resync breakpoint registers */
85
86 /* Since this is likley called from init or reset, update targtet state information*/
87 cortex_a8_poll(target);
88
89 return retval;
90 }
91
92 /* To reduce needless round-trips, pass in a pointer to the current
93 * DSCR value. Initialize it to zero if you just need to know the
94 * value on return from this function; or (1 << DSCR_INSTR_COMP) if
95 * you happen to know that no instruction is pending.
96 */
97 static int cortex_a8_exec_opcode(struct target *target,
98 uint32_t opcode, uint32_t *dscr_p)
99 {
100 uint32_t dscr;
101 int retval;
102 struct armv7a_common *armv7a = target_to_armv7a(target);
103 struct swjdp_common *swjdp = &armv7a->swjdp_info;
104
105 dscr = dscr_p ? *dscr_p : 0;
106
107 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
108
109 /* Wait for InstrCompl bit to be set */
110 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
111 {
112 retval = mem_ap_read_atomic_u32(swjdp,
113 armv7a->debug_base + CPUDBG_DSCR, &dscr);
114 if (retval != ERROR_OK)
115 {
116 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
117 return retval;
118 }
119 }
120
121 mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
122
123 do
124 {
125 retval = mem_ap_read_atomic_u32(swjdp,
126 armv7a->debug_base + CPUDBG_DSCR, &dscr);
127 if (retval != ERROR_OK)
128 {
129 LOG_ERROR("Could not read DSCR register");
130 return retval;
131 }
132 }
133 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
134
135 if (dscr_p)
136 *dscr_p = dscr;
137
138 return retval;
139 }
140
141 /**************************************************************************
142 Read core register with very few exec_opcode, fast but needs work_area.
143 This can cause problems with MMU active.
144 **************************************************************************/
145 static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
146 uint32_t * regfile)
147 {
148 int retval = ERROR_OK;
149 struct armv7a_common *armv7a = target_to_armv7a(target);
150 struct swjdp_common *swjdp = &armv7a->swjdp_info;
151
152 cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
153 cortex_a8_dap_write_coreregister_u32(target, address, 0);
154 cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
155 dap_ap_select(swjdp, swjdp_memoryap);
156 mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
157 dap_ap_select(swjdp, swjdp_debugap);
158
159 return retval;
160 }
161
162 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
163 uint32_t *value, int regnum)
164 {
165 int retval = ERROR_OK;
166 uint8_t reg = regnum&0xFF;
167 uint32_t dscr = 0;
168 struct armv7a_common *armv7a = target_to_armv7a(target);
169 struct swjdp_common *swjdp = &armv7a->swjdp_info;
170
171 if (reg > 17)
172 return retval;
173
174 if (reg < 15)
175 {
176 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
177 cortex_a8_exec_opcode(target,
178 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
179 &dscr);
180 }
181 else if (reg == 15)
182 {
183 /* "MOV r0, r15"; then move r0 to DCCTX */
184 cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
185 cortex_a8_exec_opcode(target,
186 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
187 &dscr);
188 }
189 else
190 {
191 /* "MRS r0, CPSR" or "MRS r0, SPSR"
192 * then move r0 to DCCTX
193 */
194 cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
195 cortex_a8_exec_opcode(target,
196 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
197 &dscr);
198 }
199
200 /* Wait for DTRRXfull then read DTRRTX */
201 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
202 {
203 retval = mem_ap_read_atomic_u32(swjdp,
204 armv7a->debug_base + CPUDBG_DSCR, &dscr);
205 }
206
207 retval = mem_ap_read_atomic_u32(swjdp,
208 armv7a->debug_base + CPUDBG_DTRTX, value);
209 LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
210
211 return retval;
212 }
213
214 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
215 uint32_t value, int regnum)
216 {
217 int retval = ERROR_OK;
218 uint8_t Rd = regnum&0xFF;
219 uint32_t dscr;
220 struct armv7a_common *armv7a = target_to_armv7a(target);
221 struct swjdp_common *swjdp = &armv7a->swjdp_info;
222
223 LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
224
225 /* Check that DCCRX is not full */
226 retval = mem_ap_read_atomic_u32(swjdp,
227 armv7a->debug_base + CPUDBG_DSCR, &dscr);
228 if (dscr & (1 << DSCR_DTR_RX_FULL))
229 {
230 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
231 /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
232 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
233 &dscr);
234 }
235
236 if (Rd > 17)
237 return retval;
238
239 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
240 LOG_DEBUG("write DCC 0x%08" PRIx32, value);
241 retval = mem_ap_write_u32(swjdp,
242 armv7a->debug_base + CPUDBG_DTRRX, value);
243
244 if (Rd < 15)
245 {
246 /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
247 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
248 &dscr);
249 }
250 else if (Rd == 15)
251 {
252 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
253 * then "mov r15, r0"
254 */
255 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
256 &dscr);
257 cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
258 }
259 else
260 {
261 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
262 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
263 */
264 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
265 &dscr);
266 cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
267 &dscr);
268
269 /* "Prefetch flush" after modifying execution status in CPSR */
270 if (Rd == 16)
271 cortex_a8_exec_opcode(target,
272 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
273 &dscr);
274 }
275
276 return retval;
277 }
278
279 /* Write to memory mapped registers directly with no cache or mmu handling */
280 static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
281 {
282 int retval;
283 struct armv7a_common *armv7a = target_to_armv7a(target);
284 struct swjdp_common *swjdp = &armv7a->swjdp_info;
285
286 retval = mem_ap_write_atomic_u32(swjdp, address, value);
287
288 return retval;
289 }
290
291 /*
292 * Cortex-A8 implementation of Debug Programmer's Model
293 *
294 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
295 * so there's no need to poll for it before executing an instruction.
296 *
297 * NOTE that in several of these cases the "stall" mode might be useful.
298 * It'd let us queue a few operations together... prepare/finish might
299 * be the places to enable/disable that mode.
300 */
301
302 static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
303 {
304 return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
305 }
306
307 static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
308 {
309 LOG_DEBUG("write DCC 0x%08" PRIx32, data);
310 return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
311 a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
312 }
313
314 static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
315 uint32_t *dscr_p)
316 {
317 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
318 uint32_t dscr = 1 << DSCR_INSTR_COMP;
319 int retval;
320
321 if (dscr_p)
322 dscr = *dscr_p;
323
324 /* Wait for DTRRXfull */
325 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
326 retval = mem_ap_read_atomic_u32(swjdp,
327 a8->armv7a_common.debug_base + CPUDBG_DSCR,
328 &dscr);
329 }
330
331 retval = mem_ap_read_atomic_u32(swjdp,
332 a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
333 //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
334
335 if (dscr_p)
336 *dscr_p = dscr;
337
338 return retval;
339 }
340
341 static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
342 {
343 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
344 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
345 uint32_t dscr;
346 int retval;
347
348 /* set up invariant: INSTR_COMP is set after ever DPM operation */
349 do {
350 retval = mem_ap_read_atomic_u32(swjdp,
351 a8->armv7a_common.debug_base + CPUDBG_DSCR,
352 &dscr);
353 } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
354
355 /* this "should never happen" ... */
356 if (dscr & (1 << DSCR_DTR_RX_FULL)) {
357 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
358 /* Clear DCCRX */
359 retval = cortex_a8_exec_opcode(
360 a8->armv7a_common.armv4_5_common.target,
361 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
362 &dscr);
363 }
364
365 return retval;
366 }
367
368 static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
369 {
370 /* REVISIT what could be done here? */
371 return ERROR_OK;
372 }
373
374 static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
375 uint32_t opcode, uint32_t data)
376 {
377 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
378 int retval;
379 uint32_t dscr = 1 << DSCR_INSTR_COMP;
380
381 retval = cortex_a8_write_dcc(a8, data);
382
383 return cortex_a8_exec_opcode(
384 a8->armv7a_common.armv4_5_common.target,
385 opcode,
386 &dscr);
387 }
388
389 static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
390 uint32_t opcode, uint32_t data)
391 {
392 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
393 uint32_t dscr = 1 << DSCR_INSTR_COMP;
394 int retval;
395
396 retval = cortex_a8_write_dcc(a8, data);
397
398 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
399 retval = cortex_a8_exec_opcode(
400 a8->armv7a_common.armv4_5_common.target,
401 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
402 &dscr);
403
404 /* then the opcode, taking data from R0 */
405 retval = cortex_a8_exec_opcode(
406 a8->armv7a_common.armv4_5_common.target,
407 opcode,
408 &dscr);
409
410 return retval;
411 }
412
413 static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
414 {
415 struct target *target = dpm->arm->target;
416 uint32_t dscr = 1 << DSCR_INSTR_COMP;
417
418 /* "Prefetch flush" after modifying execution status in CPSR */
419 return cortex_a8_exec_opcode(target,
420 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
421 &dscr);
422 }
423
424 static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
425 uint32_t opcode, uint32_t *data)
426 {
427 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
428 int retval;
429 uint32_t dscr = 1 << DSCR_INSTR_COMP;
430
431 /* the opcode, writing data to DCC */
432 retval = cortex_a8_exec_opcode(
433 a8->armv7a_common.armv4_5_common.target,
434 opcode,
435 &dscr);
436
437 return cortex_a8_read_dcc(a8, data, &dscr);
438 }
439
440
441 static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
442 uint32_t opcode, uint32_t *data)
443 {
444 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
445 uint32_t dscr = 1 << DSCR_INSTR_COMP;
446 int retval;
447
448 /* the opcode, writing data to R0 */
449 retval = cortex_a8_exec_opcode(
450 a8->armv7a_common.armv4_5_common.target,
451 opcode,
452 &dscr);
453
454 /* write R0 to DCC */
455 retval = cortex_a8_exec_opcode(
456 a8->armv7a_common.armv4_5_common.target,
457 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
458 &dscr);
459
460 return cortex_a8_read_dcc(a8, data, &dscr);
461 }
462
463 static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
464 uint32_t addr, uint32_t control)
465 {
466 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
467 uint32_t vr = a8->armv7a_common.debug_base;
468 uint32_t cr = a8->armv7a_common.debug_base;
469 int retval;
470
471 switch (index) {
472 case 0 ... 15: /* breakpoints */
473 vr += CPUDBG_BVR_BASE;
474 cr += CPUDBG_BCR_BASE;
475 break;
476 case 16 ... 31: /* watchpoints */
477 vr += CPUDBG_WVR_BASE;
478 cr += CPUDBG_WCR_BASE;
479 index -= 16;
480 break;
481 default:
482 return ERROR_FAIL;
483 }
484 vr += 4 * index;
485 cr += 4 * index;
486
487 LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
488 (unsigned) vr, (unsigned) cr);
489
490 retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
491 vr, addr);
492 if (retval != ERROR_OK)
493 return retval;
494 retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
495 cr, control);
496 return retval;
497 }
498
499 static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
500 {
501 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
502 uint32_t cr;
503
504 switch (index) {
505 case 0 ... 15:
506 cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
507 break;
508 case 16 ... 31:
509 cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
510 index -= 16;
511 break;
512 default:
513 return ERROR_FAIL;
514 }
515 cr += 4 * index;
516
517 LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
518
519 /* clear control register */
520 return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
521 }
522
523 static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
524 {
525 struct arm_dpm *dpm = &a8->armv7a_common.dpm;
526 int retval;
527
528 dpm->arm = &a8->armv7a_common.armv4_5_common;
529 dpm->didr = didr;
530
531 dpm->prepare = cortex_a8_dpm_prepare;
532 dpm->finish = cortex_a8_dpm_finish;
533
534 dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
535 dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
536 dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
537
538 dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
539 dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
540
541 dpm->bpwp_enable = cortex_a8_bpwp_enable;
542 dpm->bpwp_disable = cortex_a8_bpwp_disable;
543
544 retval = arm_dpm_setup(dpm);
545 if (retval == ERROR_OK)
546 retval = arm_dpm_initialize(dpm);
547
548 return retval;
549 }
550
551
552 /*
553 * Cortex-A8 Run control
554 */
555
556 static int cortex_a8_poll(struct target *target)
557 {
558 int retval = ERROR_OK;
559 uint32_t dscr;
560 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
561 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
562 struct swjdp_common *swjdp = &armv7a->swjdp_info;
563 enum target_state prev_target_state = target->state;
564 uint8_t saved_apsel = dap_ap_get_select(swjdp);
565
566 dap_ap_select(swjdp, swjdp_debugap);
567 retval = mem_ap_read_atomic_u32(swjdp,
568 armv7a->debug_base + CPUDBG_DSCR, &dscr);
569 if (retval != ERROR_OK)
570 {
571 dap_ap_select(swjdp, saved_apsel);
572 return retval;
573 }
574 cortex_a8->cpudbg_dscr = dscr;
575
576 if ((dscr & 0x3) == 0x3)
577 {
578 if (prev_target_state != TARGET_HALTED)
579 {
580 /* We have a halting debug event */
581 LOG_DEBUG("Target halted");
582 target->state = TARGET_HALTED;
583 if ((prev_target_state == TARGET_RUNNING)
584 || (prev_target_state == TARGET_RESET))
585 {
586 retval = cortex_a8_debug_entry(target);
587 if (retval != ERROR_OK)
588 return retval;
589
590 target_call_event_callbacks(target,
591 TARGET_EVENT_HALTED);
592 }
593 if (prev_target_state == TARGET_DEBUG_RUNNING)
594 {
595 LOG_DEBUG(" ");
596
597 retval = cortex_a8_debug_entry(target);
598 if (retval != ERROR_OK)
599 return retval;
600
601 target_call_event_callbacks(target,
602 TARGET_EVENT_DEBUG_HALTED);
603 }
604 }
605 }
606 else if ((dscr & 0x3) == 0x2)
607 {
608 target->state = TARGET_RUNNING;
609 }
610 else
611 {
612 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
613 target->state = TARGET_UNKNOWN;
614 }
615
616 dap_ap_select(swjdp, saved_apsel);
617
618 return retval;
619 }
620
621 static int cortex_a8_halt(struct target *target)
622 {
623 int retval = ERROR_OK;
624 uint32_t dscr;
625 struct armv7a_common *armv7a = target_to_armv7a(target);
626 struct swjdp_common *swjdp = &armv7a->swjdp_info;
627 uint8_t saved_apsel = dap_ap_get_select(swjdp);
628 dap_ap_select(swjdp, swjdp_debugap);
629
630 /*
631 * Tell the core to be halted by writing DRCR with 0x1
632 * and then wait for the core to be halted.
633 */
634 retval = mem_ap_write_atomic_u32(swjdp,
635 armv7a->debug_base + CPUDBG_DRCR, 0x1);
636
637 /*
638 * enter halting debug mode
639 */
640 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
641 retval = mem_ap_write_atomic_u32(swjdp,
642 armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
643
644 if (retval != ERROR_OK)
645 goto out;
646
647 do {
648 mem_ap_read_atomic_u32(swjdp,
649 armv7a->debug_base + CPUDBG_DSCR, &dscr);
650 } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
651
652 target->debug_reason = DBG_REASON_DBGRQ;
653
654 out:
655 dap_ap_select(swjdp, saved_apsel);
656 return retval;
657 }
658
659 static int cortex_a8_resume(struct target *target, int current,
660 uint32_t address, int handle_breakpoints, int debug_execution)
661 {
662 struct armv7a_common *armv7a = target_to_armv7a(target);
663 struct arm *armv4_5 = &armv7a->armv4_5_common;
664 struct swjdp_common *swjdp = &armv7a->swjdp_info;
665
666 // struct breakpoint *breakpoint = NULL;
667 uint32_t resume_pc, dscr;
668
669 uint8_t saved_apsel = dap_ap_get_select(swjdp);
670 dap_ap_select(swjdp, swjdp_debugap);
671
672 if (!debug_execution)
673 target_free_all_working_areas(target);
674
675 #if 0
676 if (debug_execution)
677 {
678 /* Disable interrupts */
679 /* We disable interrupts in the PRIMASK register instead of
680 * masking with C_MASKINTS,
681 * This is probably the same issue as Cortex-M3 Errata 377493:
682 * C_MASKINTS in parallel with disabled interrupts can cause
683 * local faults to not be taken. */
684 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
685 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
686 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
687
688 /* Make sure we are in Thumb mode */
689 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
690 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
691 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
692 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
693 }
694 #endif
695
696 /* current = 1: continue on current pc, otherwise continue at <address> */
697 resume_pc = buf_get_u32(
698 armv4_5->core_cache->reg_list[15].value,
699 0, 32);
700 if (!current)
701 resume_pc = address;
702
703 /* Make sure that the Armv7 gdb thumb fixups does not
704 * kill the return address
705 */
706 switch (armv4_5->core_state)
707 {
708 case ARMV4_5_STATE_ARM:
709 resume_pc &= 0xFFFFFFFC;
710 break;
711 case ARMV4_5_STATE_THUMB:
712 case ARM_STATE_THUMB_EE:
713 /* When the return address is loaded into PC
714 * bit 0 must be 1 to stay in Thumb state
715 */
716 resume_pc |= 0x1;
717 break;
718 case ARMV4_5_STATE_JAZELLE:
719 LOG_ERROR("How do I resume into Jazelle state??");
720 return ERROR_FAIL;
721 }
722 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
723 buf_set_u32(armv4_5->core_cache->reg_list[15].value,
724 0, 32, resume_pc);
725 armv4_5->core_cache->reg_list[15].dirty = 1;
726 armv4_5->core_cache->reg_list[15].valid = 1;
727
728 cortex_a8_restore_context(target, handle_breakpoints);
729
730 #if 0
731 /* the front-end may request us not to handle breakpoints */
732 if (handle_breakpoints)
733 {
734 /* Single step past breakpoint at current address */
735 if ((breakpoint = breakpoint_find(target, resume_pc)))
736 {
737 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
738 cortex_m3_unset_breakpoint(target, breakpoint);
739 cortex_m3_single_step_core(target);
740 cortex_m3_set_breakpoint(target, breakpoint);
741 }
742 }
743
744 #endif
745 /* Restart core and wait for it to be started */
746 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
747
748 do {
749 mem_ap_read_atomic_u32(swjdp,
750 armv7a->debug_base + CPUDBG_DSCR, &dscr);
751 } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
752
753 target->debug_reason = DBG_REASON_NOTHALTED;
754 target->state = TARGET_RUNNING;
755
756 /* registers are now invalid */
757 register_cache_invalidate(armv4_5->core_cache);
758
759 if (!debug_execution)
760 {
761 target->state = TARGET_RUNNING;
762 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
763 LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
764 }
765 else
766 {
767 target->state = TARGET_DEBUG_RUNNING;
768 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
769 LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
770 }
771
772 dap_ap_select(swjdp, saved_apsel);
773
774 return ERROR_OK;
775 }
776
777 static int cortex_a8_debug_entry(struct target *target)
778 {
779 int i;
780 uint32_t regfile[16], wfar, cpsr, dscr;
781 int retval = ERROR_OK;
782 struct working_area *regfile_working_area = NULL;
783 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
784 struct armv7a_common *armv7a = target_to_armv7a(target);
785 struct arm *armv4_5 = &armv7a->armv4_5_common;
786 struct swjdp_common *swjdp = &armv7a->swjdp_info;
787 struct reg *reg;
788
789 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
790
791 /* Enable the ITR execution once we are in debug mode */
792 mem_ap_read_atomic_u32(swjdp,
793 armv7a->debug_base + CPUDBG_DSCR, &dscr);
794
795 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
796 * imprecise data aborts get discarded by issuing a Data
797 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
798 */
799
800 dscr |= (1 << DSCR_EXT_INT_EN);
801 retval = mem_ap_write_atomic_u32(swjdp,
802 armv7a->debug_base + CPUDBG_DSCR, dscr);
803
804 /* Examine debug reason */
805 switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
806 {
807 case 0: /* DRCR[0] write */
808 case 4: /* EDBGRQ */
809 target->debug_reason = DBG_REASON_DBGRQ;
810 break;
811 case 1: /* HW breakpoint */
812 case 3: /* SW BKPT */
813 case 5: /* vector catch */
814 target->debug_reason = DBG_REASON_BREAKPOINT;
815 break;
816 case 2: /* asynch watchpoint */
817 case 10: /* precise watchpoint */
818 target->debug_reason = DBG_REASON_WATCHPOINT;
819
820 /* save address of faulting instruction */
821 retval = mem_ap_read_atomic_u32(swjdp,
822 armv7a->debug_base + CPUDBG_WFAR,
823 &wfar);
824 arm_dpm_report_wfar(&armv7a->dpm, wfar);
825 break;
826 default:
827 target->debug_reason = DBG_REASON_UNDEFINED;
828 break;
829 }
830
831 /* REVISIT fast_reg_read is never set ... */
832
833 /* Examine target state and mode */
834 if (cortex_a8->fast_reg_read)
835 target_alloc_working_area(target, 64, &regfile_working_area);
836
837 /* First load register acessible through core debug port*/
838 if (!regfile_working_area)
839 {
840 retval = arm_dpm_read_current_registers(&armv7a->dpm);
841 }
842 else
843 {
844 dap_ap_select(swjdp, swjdp_memoryap);
845 cortex_a8_read_regs_through_mem(target,
846 regfile_working_area->address, regfile);
847 dap_ap_select(swjdp, swjdp_memoryap);
848 target_free_working_area(target, regfile_working_area);
849
850 /* read Current PSR */
851 cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
852 dap_ap_select(swjdp, swjdp_debugap);
853 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
854
855 arm_set_cpsr(armv4_5, cpsr);
856
857 /* update cache */
858 for (i = 0; i <= ARM_PC; i++)
859 {
860 reg = arm_reg_current(armv4_5, i);
861
862 buf_set_u32(reg->value, 0, 32, regfile[i]);
863 reg->valid = 1;
864 reg->dirty = 0;
865 }
866
867 /* Fixup PC Resume Address */
868 if (cpsr & (1 << 5))
869 {
870 // T bit set for Thumb or ThumbEE state
871 regfile[ARM_PC] -= 4;
872 }
873 else
874 {
875 // ARM state
876 regfile[ARM_PC] -= 8;
877 }
878
879 reg = armv4_5->core_cache->reg_list + 15;
880 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
881 reg->dirty = reg->valid;
882 }
883
884 #if 0
885 /* TODO, Move this */
886 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
887 cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
888 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
889
890 cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
891 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
892
893 cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
894 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
895 #endif
896
897 /* Are we in an exception handler */
898 // armv4_5->exception_number = 0;
899 if (armv7a->post_debug_entry)
900 armv7a->post_debug_entry(target);
901
902 return retval;
903 }
904
905 static void cortex_a8_post_debug_entry(struct target *target)
906 {
907 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
908 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
909 int retval;
910
911 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
912 retval = armv7a->armv4_5_common.mrc(target, 15,
913 0, 0, /* op1, op2 */
914 1, 0, /* CRn, CRm */
915 &cortex_a8->cp15_control_reg);
916 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
917
918 if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
919 {
920 uint32_t cache_type_reg;
921
922 /* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
923 retval = armv7a->armv4_5_common.mrc(target, 15,
924 0, 1, /* op1, op2 */
925 0, 0, /* CRn, CRm */
926 &cache_type_reg);
927 LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
928
929 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
930 armv4_5_identify_cache(cache_type_reg,
931 &armv7a->armv4_5_mmu.armv4_5_cache);
932 }
933
934 armv7a->armv4_5_mmu.mmu_enabled =
935 (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
936 armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
937 (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
938 armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
939 (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
940
941
942 }
943
944 static int cortex_a8_step(struct target *target, int current, uint32_t address,
945 int handle_breakpoints)
946 {
947 struct armv7a_common *armv7a = target_to_armv7a(target);
948 struct arm *armv4_5 = &armv7a->armv4_5_common;
949 struct breakpoint *breakpoint = NULL;
950 struct breakpoint stepbreakpoint;
951 struct reg *r;
952
953 int timeout = 100;
954
955 if (target->state != TARGET_HALTED)
956 {
957 LOG_WARNING("target not halted");
958 return ERROR_TARGET_NOT_HALTED;
959 }
960
961 /* current = 1: continue on current pc, otherwise continue at <address> */
962 r = armv4_5->core_cache->reg_list + 15;
963 if (!current)
964 {
965 buf_set_u32(r->value, 0, 32, address);
966 }
967 else
968 {
969 address = buf_get_u32(r->value, 0, 32);
970 }
971
972 /* The front-end may request us not to handle breakpoints.
973 * But since Cortex-A8 uses breakpoint for single step,
974 * we MUST handle breakpoints.
975 */
976 handle_breakpoints = 1;
977 if (handle_breakpoints) {
978 breakpoint = breakpoint_find(target, address);
979 if (breakpoint)
980 cortex_a8_unset_breakpoint(target, breakpoint);
981 }
982
983 /* Setup single step breakpoint */
984 stepbreakpoint.address = address;
985 stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
986 ? 2 : 4;
987 stepbreakpoint.type = BKPT_HARD;
988 stepbreakpoint.set = 0;
989
990 /* Break on IVA mismatch */
991 cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
992
993 target->debug_reason = DBG_REASON_SINGLESTEP;
994
995 cortex_a8_resume(target, 1, address, 0, 0);
996
997 while (target->state != TARGET_HALTED)
998 {
999 cortex_a8_poll(target);
1000 if (--timeout == 0)
1001 {
1002 LOG_WARNING("timeout waiting for target halt");
1003 break;
1004 }
1005 }
1006
1007 cortex_a8_unset_breakpoint(target, &stepbreakpoint);
1008 if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
1009
1010 if (breakpoint)
1011 cortex_a8_set_breakpoint(target, breakpoint, 0);
1012
1013 if (target->state != TARGET_HALTED)
1014 LOG_DEBUG("target stepped");
1015
1016 return ERROR_OK;
1017 }
1018
1019 static int cortex_a8_restore_context(struct target *target, bool bpwp)
1020 {
1021 struct armv7a_common *armv7a = target_to_armv7a(target);
1022
1023 LOG_DEBUG(" ");
1024
1025 if (armv7a->pre_restore_context)
1026 armv7a->pre_restore_context(target);
1027
1028 arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
1029
1030 if (armv7a->post_restore_context)
1031 armv7a->post_restore_context(target);
1032
1033 return ERROR_OK;
1034 }
1035
1036
1037 /*
1038 * Cortex-A8 Breakpoint and watchpoint fuctions
1039 */
1040
1041 /* Setup hardware Breakpoint Register Pair */
1042 static int cortex_a8_set_breakpoint(struct target *target,
1043 struct breakpoint *breakpoint, uint8_t matchmode)
1044 {
1045 int retval;
1046 int brp_i=0;
1047 uint32_t control;
1048 uint8_t byte_addr_select = 0x0F;
1049 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1050 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1051 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1052
1053 if (breakpoint->set)
1054 {
1055 LOG_WARNING("breakpoint already set");
1056 return ERROR_OK;
1057 }
1058
1059 if (breakpoint->type == BKPT_HARD)
1060 {
1061 while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
1062 brp_i++ ;
1063 if (brp_i >= cortex_a8->brp_num)
1064 {
1065 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1066 return ERROR_FAIL;
1067 }
1068 breakpoint->set = brp_i + 1;
1069 if (breakpoint->length == 2)
1070 {
1071 byte_addr_select = (3 << (breakpoint->address & 0x02));
1072 }
1073 control = ((matchmode & 0x7) << 20)
1074 | (byte_addr_select << 5)
1075 | (3 << 1) | 1;
1076 brp_list[brp_i].used = 1;
1077 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1078 brp_list[brp_i].control = control;
1079 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1080 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1081 brp_list[brp_i].value);
1082 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1083 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1084 brp_list[brp_i].control);
1085 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1086 brp_list[brp_i].control,
1087 brp_list[brp_i].value);
1088 }
1089 else if (breakpoint->type == BKPT_SOFT)
1090 {
1091 uint8_t code[4];
1092 if (breakpoint->length == 2)
1093 {
1094 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1095 }
1096 else
1097 {
1098 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1099 }
1100 retval = target->type->read_memory(target,
1101 breakpoint->address & 0xFFFFFFFE,
1102 breakpoint->length, 1,
1103 breakpoint->orig_instr);
1104 if (retval != ERROR_OK)
1105 return retval;
1106 retval = target->type->write_memory(target,
1107 breakpoint->address & 0xFFFFFFFE,
1108 breakpoint->length, 1, code);
1109 if (retval != ERROR_OK)
1110 return retval;
1111 breakpoint->set = 0x11; /* Any nice value but 0 */
1112 }
1113
1114 return ERROR_OK;
1115 }
1116
1117 static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1118 {
1119 int retval;
1120 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1121 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1122 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1123
1124 if (!breakpoint->set)
1125 {
1126 LOG_WARNING("breakpoint not set");
1127 return ERROR_OK;
1128 }
1129
1130 if (breakpoint->type == BKPT_HARD)
1131 {
1132 int brp_i = breakpoint->set - 1;
1133 if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
1134 {
1135 LOG_DEBUG("Invalid BRP number in breakpoint");
1136 return ERROR_OK;
1137 }
1138 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1139 brp_list[brp_i].control, brp_list[brp_i].value);
1140 brp_list[brp_i].used = 0;
1141 brp_list[brp_i].value = 0;
1142 brp_list[brp_i].control = 0;
1143 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1144 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1145 brp_list[brp_i].control);
1146 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1147 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1148 brp_list[brp_i].value);
1149 }
1150 else
1151 {
1152 /* restore original instruction (kept in target endianness) */
1153 if (breakpoint->length == 4)
1154 {
1155 retval = target->type->write_memory(target,
1156 breakpoint->address & 0xFFFFFFFE,
1157 4, 1, breakpoint->orig_instr);
1158 if (retval != ERROR_OK)
1159 return retval;
1160 }
1161 else
1162 {
1163 retval = target->type->write_memory(target,
1164 breakpoint->address & 0xFFFFFFFE,
1165 2, 1, breakpoint->orig_instr);
1166 if (retval != ERROR_OK)
1167 return retval;
1168 }
1169 }
1170 breakpoint->set = 0;
1171
1172 return ERROR_OK;
1173 }
1174
1175 static int cortex_a8_add_breakpoint(struct target *target,
1176 struct breakpoint *breakpoint)
1177 {
1178 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1179
1180 if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
1181 {
1182 LOG_INFO("no hardware breakpoint available");
1183 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1184 }
1185
1186 if (breakpoint->type == BKPT_HARD)
1187 cortex_a8->brp_num_available--;
1188 cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1189
1190 return ERROR_OK;
1191 }
1192
1193 static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1194 {
1195 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1196
1197 #if 0
1198 /* It is perfectly possible to remove brakpoints while the taget is running */
1199 if (target->state != TARGET_HALTED)
1200 {
1201 LOG_WARNING("target not halted");
1202 return ERROR_TARGET_NOT_HALTED;
1203 }
1204 #endif
1205
1206 if (breakpoint->set)
1207 {
1208 cortex_a8_unset_breakpoint(target, breakpoint);
1209 if (breakpoint->type == BKPT_HARD)
1210 cortex_a8->brp_num_available++ ;
1211 }
1212
1213
1214 return ERROR_OK;
1215 }
1216
1217
1218
1219 /*
1220 * Cortex-A8 Reset fuctions
1221 */
1222
1223 static int cortex_a8_assert_reset(struct target *target)
1224 {
1225 struct armv7a_common *armv7a = target_to_armv7a(target);
1226
1227 LOG_DEBUG(" ");
1228
1229 /* FIXME when halt is requested, make it work somehow... */
1230
1231 /* Issue some kind of warm reset. */
1232 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1233 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1234 } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1235 /* REVISIT handle "pulls" cases, if there's
1236 * hardware that needs them to work.
1237 */
1238 jtag_add_reset(0, 1);
1239 } else {
1240 LOG_ERROR("%s: how to reset?", target_name(target));
1241 return ERROR_FAIL;
1242 }
1243
1244 /* registers are now invalid */
1245 register_cache_invalidate(armv7a->armv4_5_common.core_cache);
1246
1247 target->state = TARGET_RESET;
1248
1249 return ERROR_OK;
1250 }
1251
1252 static int cortex_a8_deassert_reset(struct target *target)
1253 {
1254 int retval;
1255
1256 LOG_DEBUG(" ");
1257
1258 /* be certain SRST is off */
1259 jtag_add_reset(0, 0);
1260
1261 retval = cortex_a8_poll(target);
1262
1263 if (target->reset_halt) {
1264 if (target->state != TARGET_HALTED) {
1265 LOG_WARNING("%s: ran after reset and before halt ...",
1266 target_name(target));
1267 if ((retval = target_halt(target)) != ERROR_OK)
1268 return retval;
1269 }
1270 }
1271
1272 return ERROR_OK;
1273 }
1274
1275 /*
1276 * Cortex-A8 Memory access
1277 *
1278 * This is same Cortex M3 but we must also use the correct
1279 * ap number for every access.
1280 */
1281
1282 static int cortex_a8_read_memory(struct target *target, uint32_t address,
1283 uint32_t size, uint32_t count, uint8_t *buffer)
1284 {
1285 struct armv7a_common *armv7a = target_to_armv7a(target);
1286 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1287 int retval = ERROR_INVALID_ARGUMENTS;
1288
1289 /* cortex_a8 handles unaligned memory access */
1290
1291 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1292
1293 if (count && buffer) {
1294 switch (size) {
1295 case 4:
1296 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1297 break;
1298 case 2:
1299 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1300 break;
1301 case 1:
1302 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1303 break;
1304 }
1305 }
1306
1307 return retval;
1308 }
1309
1310 static int cortex_a8_write_memory(struct target *target, uint32_t address,
1311 uint32_t size, uint32_t count, uint8_t *buffer)
1312 {
1313 struct armv7a_common *armv7a = target_to_armv7a(target);
1314 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1315 int retval = ERROR_INVALID_ARGUMENTS;
1316
1317 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1318
1319 if (count && buffer) {
1320 switch (size) {
1321 case 4:
1322 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1323 break;
1324 case 2:
1325 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1326 break;
1327 case 1:
1328 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1329 break;
1330 }
1331 }
1332
1333 /* REVISIT this op is generic ARMv7-A/R stuff */
1334 if (retval == ERROR_OK && target->state == TARGET_HALTED)
1335 {
1336 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
1337
1338 retval = dpm->prepare(dpm);
1339 if (retval != ERROR_OK)
1340 return retval;
1341
1342 /* The Cache handling will NOT work with MMU active, the
1343 * wrong addresses will be invalidated!
1344 *
1345 * For both ICache and DCache, walk all cache lines in the
1346 * address range. Cortex-A8 has fixed 64 byte line length.
1347 *
1348 * REVISIT per ARMv7, these may trigger watchpoints ...
1349 */
1350
1351 /* invalidate I-Cache */
1352 if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
1353 {
1354 /* ICIMVAU - Invalidate Cache single entry
1355 * with MVA to PoU
1356 * MCR p15, 0, r0, c7, c5, 1
1357 */
1358 for (uint32_t cacheline = address;
1359 cacheline < address + size * count;
1360 cacheline += 64) {
1361 retval = dpm->instr_write_data_r0(dpm,
1362 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
1363 cacheline);
1364 }
1365 }
1366
1367 /* invalidate D-Cache */
1368 if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
1369 {
1370 /* DCIMVAC - Invalidate data Cache line
1371 * with MVA to PoC
1372 * MCR p15, 0, r0, c7, c6, 1
1373 */
1374 for (uint32_t cacheline = address;
1375 cacheline < address + size * count;
1376 cacheline += 64) {
1377 retval = dpm->instr_write_data_r0(dpm,
1378 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
1379 cacheline);
1380 }
1381 }
1382
1383 /* (void) */ dpm->finish(dpm);
1384 }
1385
1386 return retval;
1387 }
1388
1389 static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
1390 uint32_t count, uint8_t *buffer)
1391 {
1392 return cortex_a8_write_memory(target, address, 4, count, buffer);
1393 }
1394
1395
1396 static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1397 {
1398 #if 0
1399 u16 dcrdr;
1400
1401 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1402 *ctrl = (uint8_t)dcrdr;
1403 *value = (uint8_t)(dcrdr >> 8);
1404
1405 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1406
1407 /* write ack back to software dcc register
1408 * signify we have read data */
1409 if (dcrdr & (1 << 0))
1410 {
1411 dcrdr = 0;
1412 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1413 }
1414 #endif
1415 return ERROR_OK;
1416 }
1417
1418
1419 static int cortex_a8_handle_target_request(void *priv)
1420 {
1421 struct target *target = priv;
1422 struct armv7a_common *armv7a = target_to_armv7a(target);
1423 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1424
1425 if (!target_was_examined(target))
1426 return ERROR_OK;
1427 if (!target->dbg_msg_enabled)
1428 return ERROR_OK;
1429
1430 if (target->state == TARGET_RUNNING)
1431 {
1432 uint8_t data = 0;
1433 uint8_t ctrl = 0;
1434
1435 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1436
1437 /* check if we have data */
1438 if (ctrl & (1 << 0))
1439 {
1440 uint32_t request;
1441
1442 /* we assume target is quick enough */
1443 request = data;
1444 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1445 request |= (data << 8);
1446 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1447 request |= (data << 16);
1448 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1449 request |= (data << 24);
1450 target_request(target, request);
1451 }
1452 }
1453
1454 return ERROR_OK;
1455 }
1456
1457 /*
1458 * Cortex-A8 target information and configuration
1459 */
1460
1461 static int cortex_a8_examine_first(struct target *target)
1462 {
1463 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1464 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1465 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1466 int i;
1467 int retval = ERROR_OK;
1468 uint32_t didr, ctypr, ttypr, cpuid;
1469
1470 LOG_DEBUG("TODO");
1471
1472 /* Here we shall insert a proper ROM Table scan */
1473 armv7a->debug_base = OMAP3530_DEBUG_BASE;
1474
1475 /* We do one extra read to ensure DAP is configured,
1476 * we call ahbap_debugport_init(swjdp) instead
1477 */
1478 ahbap_debugport_init(swjdp);
1479 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
1480 if ((retval = mem_ap_read_atomic_u32(swjdp,
1481 armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
1482 {
1483 LOG_DEBUG("Examine failed");
1484 return retval;
1485 }
1486
1487 if ((retval = mem_ap_read_atomic_u32(swjdp,
1488 armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
1489 {
1490 LOG_DEBUG("Examine failed");
1491 return retval;
1492 }
1493
1494 if ((retval = mem_ap_read_atomic_u32(swjdp,
1495 armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
1496 {
1497 LOG_DEBUG("Examine failed");
1498 return retval;
1499 }
1500
1501 if ((retval = mem_ap_read_atomic_u32(swjdp,
1502 armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
1503 {
1504 LOG_DEBUG("Examine failed");
1505 return retval;
1506 }
1507
1508 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
1509 LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
1510 LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
1511 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
1512
1513 armv7a->armv4_5_common.core_type = ARM_MODE_MON;
1514 cortex_a8_dpm_setup(cortex_a8, didr);
1515
1516 /* Setup Breakpoint Register Pairs */
1517 cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
1518 cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
1519 cortex_a8->brp_num_available = cortex_a8->brp_num;
1520 cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
1521 // cortex_a8->brb_enabled = ????;
1522 for (i = 0; i < cortex_a8->brp_num; i++)
1523 {
1524 cortex_a8->brp_list[i].used = 0;
1525 if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
1526 cortex_a8->brp_list[i].type = BRP_NORMAL;
1527 else
1528 cortex_a8->brp_list[i].type = BRP_CONTEXT;
1529 cortex_a8->brp_list[i].value = 0;
1530 cortex_a8->brp_list[i].control = 0;
1531 cortex_a8->brp_list[i].BRPn = i;
1532 }
1533
1534 LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num);
1535
1536 target_set_examined(target);
1537 return ERROR_OK;
1538 }
1539
1540 static int cortex_a8_examine(struct target *target)
1541 {
1542 int retval = ERROR_OK;
1543
1544 /* don't re-probe hardware after each reset */
1545 if (!target_was_examined(target))
1546 retval = cortex_a8_examine_first(target);
1547
1548 /* Configure core debug access */
1549 if (retval == ERROR_OK)
1550 retval = cortex_a8_init_debug_access(target);
1551
1552 return retval;
1553 }
1554
1555 /*
1556 * Cortex-A8 target creation and initialization
1557 */
1558
1559 static int cortex_a8_init_target(struct command_context *cmd_ctx,
1560 struct target *target)
1561 {
1562 /* examine_first() does a bunch of this */
1563 return ERROR_OK;
1564 }
1565
1566 static int cortex_a8_init_arch_info(struct target *target,
1567 struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
1568 {
1569 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1570 struct arm *armv4_5 = &armv7a->armv4_5_common;
1571 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1572
1573 /* Setup struct cortex_a8_common */
1574 cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
1575 armv4_5->arch_info = armv7a;
1576
1577 /* prepare JTAG information for the new target */
1578 cortex_a8->jtag_info.tap = tap;
1579 cortex_a8->jtag_info.scann_size = 4;
1580
1581 swjdp->dp_select_value = -1;
1582 swjdp->ap_csw_value = -1;
1583 swjdp->ap_tar_value = -1;
1584 swjdp->jtag_info = &cortex_a8->jtag_info;
1585 swjdp->memaccess_tck = 80;
1586
1587 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1588 swjdp->tar_autoincr_block = (1 << 10);
1589
1590 cortex_a8->fast_reg_read = 0;
1591
1592 /* register arch-specific functions */
1593 armv7a->examine_debug_reason = NULL;
1594
1595 armv7a->post_debug_entry = cortex_a8_post_debug_entry;
1596
1597 armv7a->pre_restore_context = NULL;
1598 armv7a->post_restore_context = NULL;
1599 armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
1600 // armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
1601 armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
1602 armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
1603 // armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
1604 // armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
1605 armv7a->armv4_5_mmu.has_tiny_pages = 1;
1606 armv7a->armv4_5_mmu.mmu_enabled = 0;
1607
1608
1609 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
1610
1611 /* REVISIT v7a setup should be in a v7a-specific routine */
1612 armv4_5_init_arch_info(target, armv4_5);
1613 armv7a->common_magic = ARMV7_COMMON_MAGIC;
1614
1615 target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
1616
1617 return ERROR_OK;
1618 }
1619
1620 static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
1621 {
1622 struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
1623
1624 cortex_a8_init_arch_info(target, cortex_a8, target->tap);
1625
1626 return ERROR_OK;
1627 }
1628
1629 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
1630 {
1631 struct target *target = get_current_target(CMD_CTX);
1632 struct armv7a_common *armv7a = target_to_armv7a(target);
1633
1634 return armv4_5_handle_cache_info_command(CMD_CTX,
1635 &armv7a->armv4_5_mmu.armv4_5_cache);
1636 }
1637
1638
1639 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
1640 {
1641 struct target *target = get_current_target(CMD_CTX);
1642
1643 cortex_a8_init_debug_access(target);
1644
1645 return ERROR_OK;
1646 }
1647
1648 static const struct command_registration cortex_a8_exec_command_handlers[] = {
1649 {
1650 .name = "cache_info",
1651 .handler = &cortex_a8_handle_cache_info_command,
1652 .mode = COMMAND_EXEC,
1653 .help = "display information about target caches",
1654 },
1655 {
1656 .name = "dbginit",
1657 .handler = &cortex_a8_handle_dbginit_command,
1658 .mode = COMMAND_EXEC,
1659 .help = "Initialize core debug",
1660 },
1661 COMMAND_REGISTRATION_DONE
1662 };
1663 static const struct command_registration cortex_a8_command_handlers[] = {
1664 {
1665 .chain = arm_command_handlers,
1666 },
1667 {
1668 .chain = armv7a_command_handlers,
1669 },
1670 {
1671 .name = "cortex_a8",
1672 .mode = COMMAND_ANY,
1673 .help = "Cortex-A8 command group",
1674 .chain = cortex_a8_exec_command_handlers,
1675 },
1676 COMMAND_REGISTRATION_DONE
1677 };
1678
1679 struct target_type cortexa8_target = {
1680 .name = "cortex_a8",
1681
1682 .poll = cortex_a8_poll,
1683 .arch_state = armv7a_arch_state,
1684
1685 .target_request_data = NULL,
1686
1687 .halt = cortex_a8_halt,
1688 .resume = cortex_a8_resume,
1689 .step = cortex_a8_step,
1690
1691 .assert_reset = cortex_a8_assert_reset,
1692 .deassert_reset = cortex_a8_deassert_reset,
1693 .soft_reset_halt = NULL,
1694
1695 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1696
1697 .read_memory = cortex_a8_read_memory,
1698 .write_memory = cortex_a8_write_memory,
1699 .bulk_write_memory = cortex_a8_bulk_write_memory,
1700
1701 .checksum_memory = arm_checksum_memory,
1702 .blank_check_memory = arm_blank_check_memory,
1703
1704 .run_algorithm = armv4_5_run_algorithm,
1705
1706 .add_breakpoint = cortex_a8_add_breakpoint,
1707 .remove_breakpoint = cortex_a8_remove_breakpoint,
1708 .add_watchpoint = NULL,
1709 .remove_watchpoint = NULL,
1710
1711 .commands = cortex_a8_command_handlers,
1712 .target_create = cortex_a8_target_create,
1713 .init_target = cortex_a8_init_target,
1714 .examine = cortex_a8_examine,
1715 };
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