src/target/embeddedice.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "embeddedice.h"
  25
  26 #include "armv4_5.h"
  27 #include "arm7_9_common.h"
  28
  29 #include "log.h"
  30 #include "arm_jtag.h"
  31 #include "types.h"
  32 #include "binarybuffer.h"
  33 #include "target.h"
  34 #include "register.h"
  35 #include "jtag.h"
  36
  37 #include <stdlib.h>
  38
  39 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
  40 {
  41         {"R", 1},
  42         {"W", 1},
  43         {"reserved", 26},
  44         {"version", 4}
  45 };
  46
  47 int embeddedice_reg_arch_info[] =
  48 {
  49         0x0, 0x1, 0x4, 0x5,
  50         0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
  51         0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
  52         0x2
  53 };
  54
  55 char* embeddedice_reg_list[] =
  56 {
  57         "debug_ctrl",
  58         "debug_status",
  59
  60         "comms_ctrl",
  61         "comms_data",
  62
  63         "watch 0 addr value",
  64         "watch 0 addr mask",
  65         "watch 0 data value",
  66         "watch 0 data mask",
  67         "watch 0 control value",
  68         "watch 0 control mask",
  69
  70         "watch 1 addr value",
  71         "watch 1 addr mask",
  72         "watch 1 data value",
  73         "watch 1 data mask",
  74         "watch 1 control value",
  75         "watch 1 control mask",
  76
  77         "vector catch"
  78 };
  79
  80 int embeddedice_reg_arch_type = -1;
  81
  82 int embeddedice_get_reg(reg_t *reg);
  83 int embeddedice_set_reg(reg_t *reg, u32 value);
  84 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
  85
  86 int embeddedice_write_reg(reg_t *reg, u32 value);
  87 int embeddedice_read_reg(reg_t *reg);
  88
  89 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
  90 {
  91         int retval;
  92         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
  93         reg_t *reg_list = NULL;
  94         embeddedice_reg_t *arch_info = NULL;
  95         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  96         int num_regs;
  97         int i;
  98         int eice_version = 0;
  99
 100         /* register a register arch-type for EmbeddedICE registers only once */
 101         if (embeddedice_reg_arch_type == -1)
 102                 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
 103
 104         if (arm7_9->has_vector_catch)
 105                 num_regs = 17;
 106         else
 107                 num_regs = 16;
 108
 109         /* the actual registers are kept in two arrays */
 110         reg_list = calloc(num_regs, sizeof(reg_t));
 111         arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
 112
 113         /* fill in values for the reg cache */
 114         reg_cache->name = "EmbeddedICE registers";
 115         reg_cache->next = NULL;
 116         reg_cache->reg_list = reg_list;
 117         reg_cache->num_regs = num_regs;
 118
 119         /* set up registers */
 120         for (i = 0; i < num_regs; i++)
 121         {
 122                 reg_list[i].name = embeddedice_reg_list[i];
 123                 reg_list[i].size = 32;
 124                 reg_list[i].dirty = 0;
 125                 reg_list[i].valid = 0;
 126                 reg_list[i].bitfield_desc = NULL;
 127                 reg_list[i].num_bitfields = 0;
 128                 reg_list[i].value = calloc(1, 4);
 129                 reg_list[i].arch_info = &arch_info[i];
 130                 reg_list[i].arch_type = embeddedice_reg_arch_type;
 131                 arch_info[i].addr = embeddedice_reg_arch_info[i];
 132                 arch_info[i].jtag_info = jtag_info;
 133         }
 134
 135         /* identify EmbeddedICE version by reading DCC control register */
 136         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 137         if ((retval=jtag_execute_queue())!=ERROR_OK)
 138         {
 139                 for (i = 0; i < num_regs; i++)
 140                 {
 141                         free(reg_list[i].value);
 142                 }
 143                 free(reg_list);
 144                 free(arch_info);
 145                 return NULL;
 146         }
 147
 148         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 149
 150         switch (eice_version)
 151         {
 152                 case 1:
 153                         reg_list[EICE_DBG_CTRL].size = 3;
 154                         reg_list[EICE_DBG_STAT].size = 5;
 155                         break;
 156                 case 2:
 157                         reg_list[EICE_DBG_CTRL].size = 4;
 158                         reg_list[EICE_DBG_STAT].size = 5;
 159                         arm7_9->has_single_step = 1;
 160                         break;
 161                 case 3:
 162                         LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
 163                         reg_list[EICE_DBG_CTRL].size = 6;
 164                         reg_list[EICE_DBG_STAT].size = 5;
 165                         arm7_9->has_single_step = 1;
 166                         arm7_9->has_monitor_mode = 1;
 167                         break;
 168                 case 4:
 169                         reg_list[EICE_DBG_CTRL].size = 6;
 170                         reg_list[EICE_DBG_STAT].size = 5;
 171                         arm7_9->has_monitor_mode = 1;
 172                         break;
 173                 case 5:
 174                         reg_list[EICE_DBG_CTRL].size = 6;
 175                         reg_list[EICE_DBG_STAT].size = 5;
 176                         arm7_9->has_single_step = 1;
 177                         arm7_9->has_monitor_mode = 1;
 178                         break;
 179                 case 6:
 180                         reg_list[EICE_DBG_CTRL].size = 6;
 181                         reg_list[EICE_DBG_STAT].size = 10;
 182                         arm7_9->has_monitor_mode = 1;
 183                         break;
 184                 case 7:
 185                         LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
 186                         reg_list[EICE_DBG_CTRL].size = 6;
 187                         reg_list[EICE_DBG_STAT].size = 5;
 188                         arm7_9->has_monitor_mode = 1;
 189                         break;
 190                 default:
 191                         LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 192         }
 193
 194         return reg_cache;
 195 }
 196
 197 int embeddedice_setup(target_t *target)
 198 {
 199         int retval;
 200         armv4_5_common_t *armv4_5 = target->arch_info;
 201         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 202
 203         /* explicitly disable monitor mode */
 204         if (arm7_9->has_monitor_mode)
 205         {
 206                 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 207
 208                 embeddedice_read_reg(dbg_ctrl);
 209                 if ((retval=jtag_execute_queue())!=ERROR_OK)
 210                         return retval;
 211                 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 212                 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
 213         }
 214         return jtag_execute_queue();
 215 }
 216
 217 int embeddedice_get_reg(reg_t *reg)
 218 {
 219         if (embeddedice_read_reg(reg) != ERROR_OK)
 220         {
 221                 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
 222                 exit(-1);
 223         }
 224
 225         if (jtag_execute_queue() != ERROR_OK)
 226         {
 227                 LOG_ERROR("register read failed");
 228         }
 229
 230         return ERROR_OK;
 231 }
 232
 233 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 234 {
 235         embeddedice_reg_t *ice_reg = reg->arch_info;
 236         u8 reg_addr = ice_reg->addr & 0x1f;
 237         scan_field_t fields[3];
 238         u8 field1_out[1];
 239         u8 field2_out[1];
 240
 241         jtag_add_end_state(TAP_RTI);
 242         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 243
 244         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 245
 246         fields[0].device = ice_reg->jtag_info->chain_pos;
 247         fields[0].num_bits = 32;
 248         fields[0].out_value = reg->value;
 249         fields[0].out_mask = NULL;
 250         fields[0].in_value = NULL;
 251         fields[0].in_check_value = NULL;
 252         fields[0].in_check_mask = NULL;
 253         fields[0].in_handler = NULL;
 254         fields[0].in_handler_priv = NULL;
 255
 256         fields[1].device = ice_reg->jtag_info->chain_pos;
 257         fields[1].num_bits = 5;
 258         fields[1].out_value = field1_out;
 259         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
 260         fields[1].out_mask = NULL;
 261         fields[1].in_value = NULL;
 262         fields[1].in_check_value = NULL;
 263         fields[1].in_check_mask = NULL;
 264         fields[1].in_handler = NULL;
 265         fields[1].in_handler_priv = NULL;
 266
 267         fields[2].device = ice_reg->jtag_info->chain_pos;
 268         fields[2].num_bits = 1;
 269         fields[2].out_value = field2_out;
 270         buf_set_u32(fields[2].out_value, 0, 1, 0);
 271         fields[2].out_mask = NULL;
 272         fields[2].in_value = NULL;
 273         fields[2].in_check_value = NULL;
 274         fields[2].in_check_mask = NULL;
 275         fields[2].in_handler = NULL;
 276         fields[2].in_handler_priv = NULL;
 277
 278         jtag_add_dr_scan(3, fields, -1);
 279
 280         fields[0].in_value = reg->value;
 281         jtag_set_check_value(fields+0, check_value, check_mask, NULL);
 282
 283         /* when reading the DCC data register, leaving the address field set to
 284          * EICE_COMMS_DATA would read the register twice
 285          * reading the control register is safe
 286          */
 287         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 288
 289         jtag_add_dr_scan(3, fields, -1);
 290
 291         return ERROR_OK;
 292 }
 293
 294 /* receive <size> words of 32 bit from the DCC
 295  * we pretend the target is always going to be fast enough
 296  * (relative to the JTAG clock), so we don't need to handshake
 297  */
 298 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 299 {
 300         scan_field_t fields[3];
 301         u8 field1_out[1];
 302         u8 field2_out[1];
 303
 304         jtag_add_end_state(TAP_RTI);
 305         arm_jtag_scann(jtag_info, 0x2);
 306         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 307
 308         fields[0].device = jtag_info->chain_pos;
 309         fields[0].num_bits = 32;
 310         fields[0].out_value = NULL;
 311         fields[0].out_mask = NULL;
 312         fields[0].in_value = NULL;
 313         fields[0].in_check_value = NULL;
 314         fields[0].in_check_mask = NULL;
 315         fields[0].in_handler = NULL;
 316         fields[0].in_handler_priv = NULL;
 317
 318         fields[1].device = jtag_info->chain_pos;
 319         fields[1].num_bits = 5;
 320         fields[1].out_value = field1_out;
 321         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 322         fields[1].out_mask = NULL;
 323         fields[1].in_value = NULL;
 324         fields[1].in_check_value = NULL;
 325         fields[1].in_check_mask = NULL;
 326         fields[1].in_handler = NULL;
 327         fields[1].in_handler_priv = NULL;
 328
 329         fields[2].device = jtag_info->chain_pos;
 330         fields[2].num_bits = 1;
 331         fields[2].out_value = field2_out;
 332         buf_set_u32(fields[2].out_value, 0, 1, 0);
 333         fields[2].out_mask = NULL;
 334         fields[2].in_value = NULL;
 335         fields[2].in_check_value = NULL;
 336         fields[2].in_check_mask = NULL;
 337         fields[2].in_handler = NULL;
 338         fields[2].in_handler_priv = NULL;
 339
 340         jtag_add_dr_scan(3, fields, -1);
 341
 342         while (size > 0)
 343         {
 344                 /* when reading the last item, set the register address to the DCC control reg,
 345                  * to avoid reading additional data from the DCC data reg
 346                  */
 347                 if (size == 1)
 348                         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 349
 350                 fields[0].in_handler = arm_jtag_buf_to_u32;
 351                 fields[0].in_handler_priv = data;
 352                 jtag_add_dr_scan(3, fields, -1);
 353
 354                 data++;
 355                 size--;
 356         }
 357
 358         return jtag_execute_queue();
 359 }
 360
 361 int embeddedice_read_reg(reg_t *reg)
 362 {
 363         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 364 }
 365
 366 int embeddedice_set_reg(reg_t *reg, u32 value)
 367 {
 368         if (embeddedice_write_reg(reg, value) != ERROR_OK)
 369         {
 370                 LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
 371                 exit(-1);
 372         }
 373
 374         buf_set_u32(reg->value, 0, reg->size, value);
 375         reg->valid = 1;
 376         reg->dirty = 0;
 377
 378         return ERROR_OK;
 379 }
 380
 381 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 382 {
 383         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 384
 385         if (jtag_execute_queue() != ERROR_OK)
 386         {
 387                 LOG_ERROR("register write failed");
 388                 exit(-1);
 389         }
 390         return ERROR_OK;
 391 }
 392
 393 int embeddedice_write_reg(reg_t *reg, u32 value)
 394 {
 395         embeddedice_reg_t *ice_reg = reg->arch_info;
 396
 397         LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
 398
 399         jtag_add_end_state(TAP_RTI);
 400         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 401
 402         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 403
 404         u8 reg_addr = ice_reg->addr & 0x1f;
 405         embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
 406
 407         return ERROR_OK;
 408 }
 409
 410 int embeddedice_store_reg(reg_t *reg)
 411 {
 412         return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 413 }
 414
 415 /* send <size> words of 32 bit to the DCC
 416  * we pretend the target is always going to be fast enough
 417  * (relative to the JTAG clock), so we don't need to handshake
 418  */
 419 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
 420 {
 421         scan_field_t fields[3];
 422         u8 field0_out[4];
 423         u8 field1_out[1];
 424         u8 field2_out[1];
 425
 426         jtag_add_end_state(TAP_RTI);
 427         arm_jtag_scann(jtag_info, 0x2);
 428         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 429
 430         fields[0].device = jtag_info->chain_pos;
 431         fields[0].num_bits = 32;
 432         fields[0].out_value = field0_out;
 433         fields[0].out_mask = NULL;
 434         fields[0].in_value = NULL;
 435         fields[0].in_check_value = NULL;
 436         fields[0].in_check_mask = NULL;
 437         fields[0].in_handler = NULL;
 438         fields[0].in_handler_priv = NULL;
 439
 440         fields[1].device = jtag_info->chain_pos;
 441         fields[1].num_bits = 5;
 442         fields[1].out_value = field1_out;
 443         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 444         fields[1].out_mask = NULL;
 445         fields[1].in_value = NULL;
 446         fields[1].in_check_value = NULL;
 447         fields[1].in_check_mask = NULL;
 448         fields[1].in_handler = NULL;
 449         fields[1].in_handler_priv = NULL;
 450
 451         fields[2].device = jtag_info->chain_pos;
 452         fields[2].num_bits = 1;
 453         fields[2].out_value = field2_out;
 454         buf_set_u32(fields[2].out_value, 0, 1, 1);
 455         fields[2].out_mask = NULL;
 456         fields[2].in_value = NULL;
 457         fields[2].in_check_value = NULL;
 458         fields[2].in_check_mask = NULL;
 459         fields[2].in_handler = NULL;
 460         fields[2].in_handler_priv = NULL;
 461
 462         while (size > 0)
 463         {
 464                 buf_set_u32(fields[0].out_value, 0, 32, *data);
 465                 jtag_add_dr_scan(3, fields, -1);
 466
 467                 data++;
 468                 size--;
 469         }
 470
 471         /* call to jtag_execute_queue() intentionally omitted */
 472         return ERROR_OK;
 473 }
 474
 475 /* wait for DCC control register R/W handshake bit to become active
 476  */
 477 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 478 {
 479         scan_field_t fields[3];
 480         u8 field0_in[4];
 481         u8 field1_out[1];
 482         u8 field2_out[1];
 483         int retval;
 484         int hsact;
 485         struct timeval lap;
 486         struct timeval now;
 487
 488         if (hsbit == EICE_COMM_CTRL_WBIT)
 489                 hsact = 1;
 490         else if (hsbit == EICE_COMM_CTRL_RBIT)
 491                 hsact = 0;
 492         else
 493                 return ERROR_INVALID_ARGUMENTS;
 494
 495         jtag_add_end_state(TAP_RTI);
 496         arm_jtag_scann(jtag_info, 0x2);
 497         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 498
 499         fields[0].device = jtag_info->chain_pos;
 500         fields[0].num_bits = 32;
 501         fields[0].out_value = NULL;
 502         fields[0].out_mask = NULL;
 503         fields[0].in_value = field0_in;
 504         fields[0].in_check_value = NULL;
 505         fields[0].in_check_mask = NULL;
 506         fields[0].in_handler = NULL;
 507         fields[0].in_handler_priv = NULL;
 508
 509         fields[1].device = jtag_info->chain_pos;
 510         fields[1].num_bits = 5;
 511         fields[1].out_value = field1_out;
 512         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 513         fields[1].out_mask = NULL;
 514         fields[1].in_value = NULL;
 515         fields[1].in_check_value = NULL;
 516         fields[1].in_check_mask = NULL;
 517         fields[1].in_handler = NULL;
 518         fields[1].in_handler_priv = NULL;
 519
 520         fields[2].device = jtag_info->chain_pos;
 521         fields[2].num_bits = 1;
 522         fields[2].out_value = field2_out;
 523         buf_set_u32(fields[2].out_value, 0, 1, 0);
 524         fields[2].out_mask = NULL;
 525         fields[2].in_value = NULL;
 526         fields[2].in_check_value = NULL;
 527         fields[2].in_check_mask = NULL;
 528         fields[2].in_handler = NULL;
 529         fields[2].in_handler_priv = NULL;
 530
 531         jtag_add_dr_scan(3, fields, -1);
 532         gettimeofday(&lap, NULL);
 533         do
 534         {
 535                 jtag_add_dr_scan(3, fields, -1);
 536                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 537                         return retval;
 538
 539                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
 540                         return ERROR_OK;
 541
 542                 gettimeofday(&now, NULL);
 543         }
 544         while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
 545
 546         return ERROR_TARGET_TIMEOUT;
 547 }