1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007-2010 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "embeddedice.h"
36 * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
37 * module found on scan chain 2 in ARM7, ARM9, and some other families
38 * of ARM cores. The module is called "EmbeddedICE-RT" if it has
39 * monitor mode support.
41 * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
42 * Communications Channel (DCC) used to read or write 32-bit words to
43 * OpenOCD-aware code running on the target CPU.
44 * Newer modules also include vector catch hardware. Some versions
45 * support hardware single-stepping, "monitor mode" debug (which is not
46 * currently supported by OpenOCD), or extended reporting on why the
47 * core entered debug mode.
50 static int embeddedice_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
);
53 * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
63 /* width is assigned based on EICE version */
66 .name
= "debug_status",
68 /* width is assigned based on EICE version */
80 [EICE_W0_ADDR_VALUE
] = {
81 .name
= "watch_0_addr_value",
85 [EICE_W0_ADDR_MASK
] = {
86 .name
= "watch_0_addr_mask",
90 [EICE_W0_DATA_VALUE
] = {
91 .name
= "watch_0_data_value",
95 [EICE_W0_DATA_MASK
] = {
96 .name
= "watch_0_data_mask",
100 [EICE_W0_CONTROL_VALUE
] = {
101 .name
= "watch_0_control_value",
105 [EICE_W0_CONTROL_MASK
] = {
106 .name
= "watch_0_control_mask",
110 [EICE_W1_ADDR_VALUE
] = {
111 .name
= "watch_1_addr_value",
115 [EICE_W1_ADDR_MASK
] = {
116 .name
= "watch_1_addr_mask",
120 [EICE_W1_DATA_VALUE
] = {
121 .name
= "watch_1_data_value",
125 [EICE_W1_DATA_MASK
] = {
126 .name
= "watch_1_data_mask",
130 [EICE_W1_CONTROL_VALUE
] = {
131 .name
= "watch_1_control_value",
135 [EICE_W1_CONTROL_MASK
] = {
136 .name
= "watch_1_control_mask",
140 /* vector_catch isn't always present */
142 .name
= "vector_catch",
149 static int embeddedice_get_reg(struct reg
*reg
)
153 if ((retval
= embeddedice_read_reg(reg
)) != ERROR_OK
)
154 LOG_ERROR("error queueing EmbeddedICE register read");
155 else if ((retval
= jtag_execute_queue()) != ERROR_OK
)
156 LOG_ERROR("EmbeddedICE register read failed");
161 static const struct reg_arch_type eice_reg_type
= {
162 .get
= embeddedice_get_reg
,
163 .set
= embeddedice_set_reg_w_exec
,
167 * Probe EmbeddedICE module and set up local records of its registers.
168 * Different versions of the modules have different capabilities, such as
169 * hardware support for vector_catch, single stepping, and monitor mode.
172 embeddedice_build_reg_cache(struct target
*target
, struct arm7_9_common
*arm7_9
)
175 struct reg_cache
*reg_cache
= malloc(sizeof(struct reg_cache
));
176 struct reg
*reg_list
= NULL
;
177 struct embeddedice_reg
*arch_info
= NULL
;
178 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
179 int num_regs
= ARRAY_SIZE(eice_regs
);
181 int eice_version
= 0;
183 /* vector_catch isn't always present */
184 if (!arm7_9
->has_vector_catch
)
187 /* the actual registers are kept in two arrays */
188 reg_list
= calloc(num_regs
, sizeof(struct reg
));
189 arch_info
= calloc(num_regs
, sizeof(struct embeddedice_reg
));
191 /* fill in values for the reg cache */
192 reg_cache
->name
= "EmbeddedICE registers";
193 reg_cache
->next
= NULL
;
194 reg_cache
->reg_list
= reg_list
;
195 reg_cache
->num_regs
= num_regs
;
197 /* FIXME the second watchpoint unit on Feroceon and Dragonite
198 * seems not to work ... we should have a way to not set up
199 * its four registers here!
202 /* set up registers */
203 for (i
= 0; i
< num_regs
; i
++)
205 reg_list
[i
].name
= eice_regs
[i
].name
;
206 reg_list
[i
].size
= eice_regs
[i
].width
;
207 reg_list
[i
].dirty
= 0;
208 reg_list
[i
].valid
= 0;
209 reg_list
[i
].value
= calloc(1, 4);
210 reg_list
[i
].arch_info
= &arch_info
[i
];
211 reg_list
[i
].type
= &eice_reg_type
;
212 arch_info
[i
].addr
= eice_regs
[i
].addr
;
213 arch_info
[i
].jtag_info
= jtag_info
;
216 /* identify EmbeddedICE version by reading DCC control register */
217 embeddedice_read_reg(®_list
[EICE_COMMS_CTRL
]);
218 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
220 for (i
= 0; i
< num_regs
; i
++)
222 free(reg_list
[i
].value
);
230 eice_version
= buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 28, 4);
231 LOG_INFO("Embedded ICE version %d", eice_version
);
233 switch (eice_version
)
236 /* ARM7TDMI r3, ARM7TDMI-S r3
238 * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
239 * that it has 6-bit CTRL and 5-bit STAT... doc bug?
240 * ARM7TDMI r4 docs say EICE v4.
242 reg_list
[EICE_DBG_CTRL
].size
= 3;
243 reg_list
[EICE_DBG_STAT
].size
= 5;
247 reg_list
[EICE_DBG_CTRL
].size
= 4;
248 reg_list
[EICE_DBG_STAT
].size
= 5;
249 arm7_9
->has_single_step
= 1;
252 LOG_ERROR("EmbeddedICE v%d handling might be broken",
254 reg_list
[EICE_DBG_CTRL
].size
= 6;
255 reg_list
[EICE_DBG_STAT
].size
= 5;
256 arm7_9
->has_single_step
= 1;
257 arm7_9
->has_monitor_mode
= 1;
261 reg_list
[EICE_DBG_CTRL
].size
= 6;
262 reg_list
[EICE_DBG_STAT
].size
= 5;
263 arm7_9
->has_monitor_mode
= 1;
267 reg_list
[EICE_DBG_CTRL
].size
= 6;
268 reg_list
[EICE_DBG_STAT
].size
= 5;
269 arm7_9
->has_single_step
= 1;
270 arm7_9
->has_monitor_mode
= 1;
273 /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
274 reg_list
[EICE_DBG_CTRL
].size
= 6;
275 reg_list
[EICE_DBG_STAT
].size
= 10;
276 /* DBG_STAT has MOE bits */
277 arm7_9
->has_monitor_mode
= 1;
280 LOG_ERROR("EmbeddedICE v%d handling might be broken",
282 reg_list
[EICE_DBG_CTRL
].size
= 6;
283 reg_list
[EICE_DBG_STAT
].size
= 5;
284 arm7_9
->has_monitor_mode
= 1;
288 * The Feroceon implementation has the version number
289 * in some unusual bits. Let feroceon.c validate it
290 * and do the appropriate setup itself.
292 if (strcmp(target_type_name(target
), "feroceon") == 0 ||
293 strcmp(target_type_name(target
), "dragonite") == 0)
295 LOG_ERROR("unknown EmbeddedICE version "
296 "(comms ctrl: 0x%8.8" PRIx32
")",
297 buf_get_u32(reg_list
[EICE_COMMS_CTRL
].value
, 0, 32));
300 /* On Feroceon and Dragonite the second unit is seemingly missing. */
301 LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
302 target_name(target
), arm7_9
->wp_available_max
,
303 (arm7_9
->wp_available_max
!= 1) ? "s" : "");
309 * Initialize EmbeddedICE module, if needed.
311 int embeddedice_setup(struct target
*target
)
314 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
316 /* Explicitly disable monitor mode. For now we only support halting
317 * debug ... we don't know how to talk with a resident debug monitor
318 * that manages break requests. ARM's "Angel Debug Monitor" is one
319 * common example of such code.
321 if (arm7_9
->has_monitor_mode
)
323 struct reg
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
325 embeddedice_read_reg(dbg_ctrl
);
326 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
328 buf_set_u32(dbg_ctrl
->value
, 4, 1, 0);
329 embeddedice_set_reg_w_exec(dbg_ctrl
, dbg_ctrl
->value
);
331 return jtag_execute_queue();
335 * Queue a read for an EmbeddedICE register into the register cache,
336 * optionally checking the value read.
337 * Note that at this level, all registers are 32 bits wide.
339 int embeddedice_read_reg_w_check(struct reg
*reg
,
340 uint8_t *check_value
, uint8_t *check_mask
)
342 struct embeddedice_reg
*ice_reg
= reg
->arch_info
;
343 uint8_t reg_addr
= ice_reg
->addr
& 0x1f;
344 struct scan_field fields
[3];
345 uint8_t field1_out
[1];
346 uint8_t field2_out
[1];
349 arm_jtag_scann(ice_reg
->jtag_info
, 0x2, TAP_IDLE
);
351 retval
= arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
352 if (retval
!= ERROR_OK
)
355 /* bits 31:0 -- data (ignored here) */
356 fields
[0].num_bits
= 32;
357 fields
[0].out_value
= reg
->value
;
358 fields
[0].in_value
= NULL
;
359 fields
[0].check_value
= NULL
;
360 fields
[0].check_mask
= NULL
;
362 /* bits 36:32 -- register */
363 fields
[1].num_bits
= 5;
364 fields
[1].out_value
= field1_out
;
365 field1_out
[0] = reg_addr
;
366 fields
[1].in_value
= NULL
;
367 fields
[1].check_value
= NULL
;
368 fields
[1].check_mask
= NULL
;
370 /* bit 37 -- 0/read */
371 fields
[2].num_bits
= 1;
372 fields
[2].out_value
= field2_out
;
374 fields
[2].in_value
= NULL
;
375 fields
[2].check_value
= NULL
;
376 fields
[2].check_mask
= NULL
;
378 /* traverse Update-DR, setting address for the next read */
379 jtag_add_dr_scan(ice_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
381 /* bits 31:0 -- the data we're reading (and maybe checking) */
382 fields
[0].in_value
= reg
->value
;
383 fields
[0].check_value
= check_value
;
384 fields
[0].check_mask
= check_mask
;
386 /* when reading the DCC data register, leaving the address field set to
387 * EICE_COMMS_DATA would read the register twice
388 * reading the control register is safe
390 field1_out
[0] = eice_regs
[EICE_COMMS_CTRL
].addr
;
392 /* traverse Update-DR, reading but with no other side effects */
393 jtag_add_dr_scan_check(ice_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
399 * Receive a block of size 32-bit words from the DCC.
400 * We assume the target is always going to be fast enough (relative to
401 * the JTAG clock) that the debugger won't need to poll the handshake
402 * bit. The JTAG clock is usually at least six times slower than the
403 * functional clock, so the 50+ JTAG clocks needed to receive the word
404 * allow hundreds of instruction cycles (per word) in the target.
406 int embeddedice_receive(struct arm_jtag
*jtag_info
, uint32_t *data
, uint32_t size
)
408 struct scan_field fields
[3];
409 uint8_t field1_out
[1];
410 uint8_t field2_out
[1];
413 arm_jtag_scann(jtag_info
, 0x2, TAP_IDLE
);
414 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
415 if (retval
!= ERROR_OK
)
418 fields
[0].num_bits
= 32;
419 fields
[0].out_value
= NULL
;
420 fields
[0].in_value
= NULL
;
422 fields
[1].num_bits
= 5;
423 fields
[1].out_value
= field1_out
;
424 field1_out
[0] = eice_regs
[EICE_COMMS_DATA
].addr
;
425 fields
[1].in_value
= NULL
;
427 fields
[2].num_bits
= 1;
428 fields
[2].out_value
= field2_out
;
430 fields
[2].in_value
= NULL
;
432 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
436 /* when reading the last item, set the register address to the DCC control reg,
437 * to avoid reading additional data from the DCC data reg
440 field1_out
[0] = eice_regs
[EICE_COMMS_CTRL
].addr
;
442 fields
[0].in_value
= (uint8_t *)data
;
443 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
444 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)data
);
450 return jtag_execute_queue();
454 * Queue a read for an EmbeddedICE register into the register cache,
455 * not checking the value read.
457 int embeddedice_read_reg(struct reg
*reg
)
459 return embeddedice_read_reg_w_check(reg
, NULL
, NULL
);
463 * Queue a write for an EmbeddedICE register, updating the register cache.
464 * Uses embeddedice_write_reg().
466 void embeddedice_set_reg(struct reg
*reg
, uint32_t value
)
468 embeddedice_write_reg(reg
, value
);
470 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
477 * Write an EmbeddedICE register, updating the register cache.
478 * Uses embeddedice_set_reg(); not queued.
480 static int embeddedice_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
)
484 embeddedice_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
485 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
486 LOG_ERROR("register write failed");
491 * Queue a write for an EmbeddedICE register, bypassing the register cache.
493 void embeddedice_write_reg(struct reg
*reg
, uint32_t value
)
495 struct embeddedice_reg
*ice_reg
= reg
->arch_info
;
498 LOG_DEBUG("%i: 0x%8.8" PRIx32
"", ice_reg
->addr
, value
);
500 arm_jtag_scann(ice_reg
->jtag_info
, 0x2, TAP_IDLE
);
502 retval
= arm_jtag_set_instr(ice_reg
->jtag_info
, ice_reg
->jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
504 uint8_t reg_addr
= ice_reg
->addr
& 0x1f;
505 embeddedice_write_reg_inner(ice_reg
->jtag_info
->tap
, reg_addr
, value
);
509 * Queue a write for an EmbeddedICE register, using cached value.
510 * Uses embeddedice_write_reg().
512 void embeddedice_store_reg(struct reg
*reg
)
514 embeddedice_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
518 * Send a block of size 32-bit words to the DCC.
519 * We assume the target is always going to be fast enough (relative to
520 * the JTAG clock) that the debugger won't need to poll the handshake
521 * bit. The JTAG clock is usually at least six times slower than the
522 * functional clock, so the 50+ JTAG clocks needed to receive the word
523 * allow hundreds of instruction cycles (per word) in the target.
525 int embeddedice_send(struct arm_jtag
*jtag_info
, uint32_t *data
, uint32_t size
)
527 struct scan_field fields
[3];
528 uint8_t field0_out
[4];
529 uint8_t field1_out
[1];
530 uint8_t field2_out
[1];
533 arm_jtag_scann(jtag_info
, 0x2, TAP_IDLE
);
534 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
535 if (retval
!= ERROR_OK
)
538 fields
[0].num_bits
= 32;
539 fields
[0].out_value
= field0_out
;
540 fields
[0].in_value
= NULL
;
542 fields
[1].num_bits
= 5;
543 fields
[1].out_value
= field1_out
;
544 field1_out
[0] = eice_regs
[EICE_COMMS_DATA
].addr
;
545 fields
[1].in_value
= NULL
;
547 fields
[2].num_bits
= 1;
548 fields
[2].out_value
= field2_out
;
551 fields
[2].in_value
= NULL
;
555 buf_set_u32(field0_out
, 0, 32, *data
);
556 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
562 /* call to jtag_execute_queue() intentionally omitted */
567 * Poll DCC control register until read or write handshake completes.
569 int embeddedice_handshake(struct arm_jtag
*jtag_info
, int hsbit
, uint32_t timeout
)
571 struct scan_field fields
[3];
572 uint8_t field0_in
[4];
573 uint8_t field1_out
[1];
574 uint8_t field2_out
[1];
580 if (hsbit
== EICE_COMM_CTRL_WBIT
)
582 else if (hsbit
== EICE_COMM_CTRL_RBIT
)
585 return ERROR_INVALID_ARGUMENTS
;
587 arm_jtag_scann(jtag_info
, 0x2, TAP_IDLE
);
588 retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
589 if (retval
!= ERROR_OK
)
592 fields
[0].num_bits
= 32;
593 fields
[0].out_value
= NULL
;
594 fields
[0].in_value
= field0_in
;
596 fields
[1].num_bits
= 5;
597 fields
[1].out_value
= field1_out
;
598 field1_out
[0] = eice_regs
[EICE_COMMS_DATA
].addr
;
599 fields
[1].in_value
= NULL
;
601 fields
[2].num_bits
= 1;
602 fields
[2].out_value
= field2_out
;
604 fields
[2].in_value
= NULL
;
606 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
607 gettimeofday(&lap
, NULL
);
609 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
610 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
613 if (buf_get_u32(field0_in
, hsbit
, 1) == hsact
)
616 gettimeofday(&now
, NULL
);
617 } while ((uint32_t)((now
.tv_sec
- lap
.tv_sec
) * 1000
618 + (now
.tv_usec
- lap
.tv_usec
) / 1000) <= timeout
);
620 return ERROR_TARGET_TIMEOUT
;
623 #ifndef HAVE_JTAG_MINIDRIVER_H
625 * This is an inner loop of the open loop DCC write of data to target
627 void embeddedice_write_dcc(struct jtag_tap
*tap
,
628 int reg_addr
, uint8_t *buffer
, int little
, int count
)
632 for (i
= 0; i
< count
; i
++)
634 embeddedice_write_reg_inner(tap
, reg_addr
,
635 fast_target_buffer_get_u32(buffer
, little
));
640 /* provided by minidriver */
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