src/target/espressif/esp32s3.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   ESP32-S3 target for OpenOCD                                           *
   5  *   Copyright (C) 2020 Espressif Systems Ltd.                             *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_TARGET_ESP32S3_H
   9 #define OPENOCD_TARGET_ESP32S3_H
  10
  11 #include <target/xtensa/xtensa_regs.h>
  12
  13 #define ESP32_S3_DROM_LOW             0x3C000000
  14 #define ESP32_S3_DROM_HIGH            0x3D000000
  15 #define ESP32_S3_IROM_LOW             0x42000000
  16 #define ESP32_S3_IROM_HIGH            0x44000000
  17
  18 /*Number of registers returned directly by the G command
  19  *Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
  20 #define ESP32_S3_NUM_REGS_G_COMMAND   128
  21
  22 enum esp32s3_reg_id {
  23         /* chip specific registers that extend ISA go after ISA-defined ones */
  24         ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
  25         ESP32_S3_REG_IDX_ACCX_0,
  26         ESP32_S3_REG_IDX_ACCX_1,
  27         ESP32_S3_REG_IDX_QACC_H_0,
  28         ESP32_S3_REG_IDX_QACC_H_1,
  29         ESP32_S3_REG_IDX_QACC_H_2,
  30         ESP32_S3_REG_IDX_QACC_H_3,
  31         ESP32_S3_REG_IDX_QACC_H_4,
  32         ESP32_S3_REG_IDX_QACC_L_0,
  33         ESP32_S3_REG_IDX_QACC_L_1,
  34         ESP32_S3_REG_IDX_QACC_L_2,
  35         ESP32_S3_REG_IDX_QACC_L_3,
  36         ESP32_S3_REG_IDX_QACC_L_4,
  37         ESP32_S3_REG_IDX_SAR_BYTE,
  38         ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
  39         ESP32_S3_REG_IDX_UA_STATE_0,
  40         ESP32_S3_REG_IDX_UA_STATE_1,
  41         ESP32_S3_REG_IDX_UA_STATE_2,
  42         ESP32_S3_REG_IDX_UA_STATE_3,
  43         ESP32_S3_REG_IDX_Q0,
  44         ESP32_S3_REG_IDX_Q1,
  45         ESP32_S3_REG_IDX_Q2,
  46         ESP32_S3_REG_IDX_Q3,
  47         ESP32_S3_REG_IDX_Q4,
  48         ESP32_S3_REG_IDX_Q5,
  49         ESP32_S3_REG_IDX_Q6,
  50         ESP32_S3_REG_IDX_Q7,
  51         ESP32_S3_NUM_REGS,
  52 };
  53
  54 #endif  /* OPENOCD_TARGET_ESP32S3_H */