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[openocd.git] / src / target / etb.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm7_9_common.h"
25 #include "etb.h"
26
27
28 static char* etb_reg_list[] =
29 {
30 "ETB_identification",
31 "ETB_ram_depth",
32 "ETB_ram_width",
33 "ETB_status",
34 "ETB_ram_data",
35 "ETB_ram_read_pointer",
36 "ETB_ram_write_pointer",
37 "ETB_trigger_counter",
38 "ETB_control",
39 };
40
41 static int etb_reg_arch_type = -1;
42
43 static int etb_get_reg(reg_t *reg);
44
45 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46
47 static int etb_set_instr(etb_t *etb, u32 new_instr)
48 {
49 jtag_tap_t *tap;
50
51 tap = etb->tap;
52 if (tap==NULL)
53 return ERROR_FAIL;
54
55 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
56 {
57 scan_field_t field;
58
59 field.tap = tap;
60 field.num_bits = tap->ir_length;
61 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
62 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
63
64 field.in_value = NULL;
65
66 jtag_add_ir_scan(1, &field, TAP_INVALID);
67
68 free(field.out_value);
69 }
70
71 return ERROR_OK;
72 }
73
74 static int etb_scann(etb_t *etb, u32 new_scan_chain)
75 {
76 if (etb->cur_scan_chain != new_scan_chain)
77 {
78 scan_field_t field;
79
80 field.tap = etb->tap;
81 field.num_bits = 5;
82 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
83 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
84
85 field.in_value = NULL;
86
87 /* select INTEST instruction */
88 etb_set_instr(etb, 0x2);
89 jtag_add_dr_scan(1, &field, TAP_INVALID);
90
91 etb->cur_scan_chain = new_scan_chain;
92
93 free(field.out_value);
94 }
95
96 return ERROR_OK;
97 }
98
99 reg_cache_t* etb_build_reg_cache(etb_t *etb)
100 {
101 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
102 reg_t *reg_list = NULL;
103 etb_reg_t *arch_info = NULL;
104 int num_regs = 9;
105 int i;
106
107 /* register a register arch-type for etm registers only once */
108 if (etb_reg_arch_type == -1)
109 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
110
111 /* the actual registers are kept in two arrays */
112 reg_list = calloc(num_regs, sizeof(reg_t));
113 arch_info = calloc(num_regs, sizeof(etb_reg_t));
114
115 /* fill in values for the reg cache */
116 reg_cache->name = "etb registers";
117 reg_cache->next = NULL;
118 reg_cache->reg_list = reg_list;
119 reg_cache->num_regs = num_regs;
120
121 /* set up registers */
122 for (i = 0; i < num_regs; i++)
123 {
124 reg_list[i].name = etb_reg_list[i];
125 reg_list[i].size = 32;
126 reg_list[i].dirty = 0;
127 reg_list[i].valid = 0;
128 reg_list[i].bitfield_desc = NULL;
129 reg_list[i].num_bitfields = 0;
130 reg_list[i].value = calloc(1, 4);
131 reg_list[i].arch_info = &arch_info[i];
132 reg_list[i].arch_type = etb_reg_arch_type;
133 reg_list[i].size = 32;
134 arch_info[i].addr = i;
135 arch_info[i].etb = etb;
136 }
137
138 return reg_cache;
139 }
140
141 static int etb_get_reg(reg_t *reg)
142 {
143 int retval;
144
145 if ((retval = etb_read_reg(reg)) != ERROR_OK)
146 {
147 LOG_ERROR("BUG: error scheduling etm register read");
148 return retval;
149 }
150
151 if ((retval = jtag_execute_queue()) != ERROR_OK)
152 {
153 LOG_ERROR("register read failed");
154 return retval;
155 }
156
157 return ERROR_OK;
158 }
159
160
161 static void etb_getbuf(u8 *in)
162 {
163 *((u32 *)in)=buf_get_u32(in, 0, 32);
164 }
165
166
167 static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
168 {
169 scan_field_t fields[3];
170 int i;
171
172 jtag_add_end_state(TAP_IDLE);
173 etb_scann(etb, 0x0);
174 etb_set_instr(etb, 0xc);
175
176 fields[0].tap = etb->tap;
177 fields[0].num_bits = 32;
178 fields[0].out_value = NULL;
179 fields[0].in_value = NULL;
180
181 fields[1].tap = etb->tap;
182 fields[1].num_bits = 7;
183 fields[1].out_value = malloc(1);
184 buf_set_u32(fields[1].out_value, 0, 7, 4);
185 fields[1].in_value = NULL;
186
187 fields[2].tap = etb->tap;
188 fields[2].num_bits = 1;
189 fields[2].out_value = malloc(1);
190 buf_set_u32(fields[2].out_value, 0, 1, 0);
191 fields[2].in_value = NULL;
192
193 jtag_add_dr_scan(3, fields, TAP_INVALID);
194
195 for (i = 0; i < num_frames; i++)
196 {
197 /* ensure nR/W reamins set to read */
198 buf_set_u32(fields[2].out_value, 0, 1, 0);
199
200 /* address remains set to 0x4 (RAM data) until we read the last frame */
201 if (i < num_frames - 1)
202 buf_set_u32(fields[1].out_value, 0, 7, 4);
203 else
204 buf_set_u32(fields[1].out_value, 0, 7, 0);
205
206 fields[0].in_value = (u8 *)(data+i);
207 jtag_add_dr_scan(3, fields, TAP_INVALID);
208
209 jtag_add_callback(etb_getbuf, (u8 *)(data+i));
210 }
211
212 jtag_execute_queue();
213
214 free(fields[1].out_value);
215 free(fields[2].out_value);
216
217 return ERROR_OK;
218 }
219
220 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
221 {
222 etb_reg_t *etb_reg = reg->arch_info;
223 u8 reg_addr = etb_reg->addr & 0x7f;
224 scan_field_t fields[3];
225
226 LOG_DEBUG("%i", etb_reg->addr);
227
228 jtag_add_end_state(TAP_IDLE);
229 etb_scann(etb_reg->etb, 0x0);
230 etb_set_instr(etb_reg->etb, 0xc);
231
232 fields[0].tap = etb_reg->etb->tap;
233 fields[0].num_bits = 32;
234 fields[0].out_value = reg->value;
235 fields[0].in_value = NULL;
236
237 fields[1].tap = etb_reg->etb->tap;
238 fields[1].num_bits = 7;
239 fields[1].out_value = malloc(1);
240 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
241 fields[1].in_value = NULL;
242
243 fields[2].tap = etb_reg->etb->tap;
244 fields[2].num_bits = 1;
245 fields[2].out_value = malloc(1);
246 buf_set_u32(fields[2].out_value, 0, 1, 0);
247 fields[2].in_value = NULL;
248
249 jtag_add_dr_scan(3, fields, TAP_INVALID);
250
251 /* read the identification register in the second run, to make sure we
252 * don't read the ETB data register twice, skipping every second entry
253 */
254 buf_set_u32(fields[1].out_value, 0, 7, 0x0);
255 fields[0].in_value = reg->value;
256
257 jtag_add_dr_scan(3, fields, TAP_INVALID);
258
259 jtag_check_value_mask(fields+0, check_value, check_mask);
260
261 free(fields[1].out_value);
262 free(fields[2].out_value);
263
264 return ERROR_OK;
265 }
266
267 int etb_read_reg(reg_t *reg)
268 {
269 return etb_read_reg_w_check(reg, NULL, NULL);
270 }
271
272 int etb_set_reg(reg_t *reg, u32 value)
273 {
274 int retval;
275
276 if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
277 {
278 LOG_ERROR("BUG: error scheduling etm register write");
279 return retval;
280 }
281
282 buf_set_u32(reg->value, 0, reg->size, value);
283 reg->valid = 1;
284 reg->dirty = 0;
285
286 return ERROR_OK;
287 }
288
289 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
290 {
291 int retval;
292
293 etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
294
295 if ((retval = jtag_execute_queue()) != ERROR_OK)
296 {
297 LOG_ERROR("register write failed");
298 return retval;
299 }
300 return ERROR_OK;
301 }
302
303 int etb_write_reg(reg_t *reg, u32 value)
304 {
305 etb_reg_t *etb_reg = reg->arch_info;
306 u8 reg_addr = etb_reg->addr & 0x7f;
307 scan_field_t fields[3];
308
309 LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
310
311 jtag_add_end_state(TAP_IDLE);
312 etb_scann(etb_reg->etb, 0x0);
313 etb_set_instr(etb_reg->etb, 0xc);
314
315 fields[0].tap = etb_reg->etb->tap;
316 fields[0].num_bits = 32;
317 fields[0].out_value = malloc(4);
318 buf_set_u32(fields[0].out_value, 0, 32, value);
319 fields[0].in_value = NULL;
320
321 fields[1].tap = etb_reg->etb->tap;
322 fields[1].num_bits = 7;
323 fields[1].out_value = malloc(1);
324 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
325 fields[1].in_value = NULL;
326
327 fields[2].tap = etb_reg->etb->tap;
328 fields[2].num_bits = 1;
329 fields[2].out_value = malloc(1);
330 buf_set_u32(fields[2].out_value, 0, 1, 1);
331
332 fields[2].in_value = NULL;
333
334 free(fields[0].out_value);
335 free(fields[1].out_value);
336 free(fields[2].out_value);
337
338 return ERROR_OK;
339 }
340
341 int etb_store_reg(reg_t *reg)
342 {
343 return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
344 }
345
346 static int etb_register_commands(struct command_context_s *cmd_ctx)
347 {
348 command_t *etb_cmd;
349
350 etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
351
352 register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
353
354 return ERROR_OK;
355 }
356
357 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
358 {
359 target_t *target;
360 jtag_tap_t *tap;
361 armv4_5_common_t *armv4_5;
362 arm7_9_common_t *arm7_9;
363
364 if (argc != 2)
365 {
366 return ERROR_COMMAND_SYNTAX_ERROR;
367 }
368
369 target = get_target_by_num(strtoul(args[0], NULL, 0));
370
371 if (!target)
372 {
373 LOG_ERROR("target number '%s' not defined", args[0]);
374 return ERROR_FAIL;
375 }
376
377 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
378 {
379 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
380 return ERROR_FAIL;
381 }
382
383 tap = jtag_TapByString( args[1] );
384 if (tap == NULL)
385 {
386 command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
387 return ERROR_FAIL;
388 }
389
390 if (arm7_9->etm_ctx)
391 {
392 etb_t *etb = malloc(sizeof(etb_t));
393
394 arm7_9->etm_ctx->capture_driver_priv = etb;
395
396 etb->tap = tap;
397 etb->cur_scan_chain = 0xffffffff;
398 etb->reg_cache = NULL;
399 etb->ram_width = 0;
400 etb->ram_depth = 0;
401 }
402 else
403 {
404 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
405 return ERROR_FAIL;
406 }
407
408 return ERROR_OK;
409 }
410
411 static int etb_init(etm_context_t *etm_ctx)
412 {
413 etb_t *etb = etm_ctx->capture_driver_priv;
414
415 etb->etm_ctx = etm_ctx;
416
417 /* identify ETB RAM depth and width */
418 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
419 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
420 jtag_execute_queue();
421
422 etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
423 etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
424
425 return ERROR_OK;
426 }
427
428 static trace_status_t etb_status(etm_context_t *etm_ctx)
429 {
430 etb_t *etb = etm_ctx->capture_driver_priv;
431
432 etb->etm_ctx = etm_ctx;
433
434 /* if tracing is currently idle, return this information */
435 if (etm_ctx->capture_status == TRACE_IDLE)
436 {
437 return etm_ctx->capture_status;
438 }
439 else if (etm_ctx->capture_status & TRACE_RUNNING)
440 {
441 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
442 int etb_timeout = 100;
443
444 /* trace is running, check the ETB status flags */
445 etb_get_reg(etb_status_reg);
446
447 /* check Full bit to identify an overflow */
448 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
449 etm_ctx->capture_status |= TRACE_OVERFLOWED;
450
451 /* check Triggered bit to identify trigger condition */
452 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
453 etm_ctx->capture_status |= TRACE_TRIGGERED;
454
455 /* check AcqComp to identify trace completion */
456 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
457 {
458 while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
459 {
460 /* wait for data formatter idle */
461 etb_get_reg(etb_status_reg);
462 }
463
464 if (etb_timeout == 0)
465 {
466 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
467 buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
468 }
469
470 if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
471 {
472 LOG_ERROR("trace completed, but no trigger condition detected");
473 }
474
475 etm_ctx->capture_status &= ~TRACE_RUNNING;
476 etm_ctx->capture_status |= TRACE_COMPLETED;
477 }
478 }
479
480 return etm_ctx->capture_status;
481 }
482
483 static int etb_read_trace(etm_context_t *etm_ctx)
484 {
485 etb_t *etb = etm_ctx->capture_driver_priv;
486 int first_frame = 0;
487 int num_frames = etb->ram_depth;
488 u32 *trace_data = NULL;
489 int i, j;
490
491 etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
492 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
493 jtag_execute_queue();
494
495 /* check if we overflowed, and adjust first frame of the trace accordingly
496 * if we didn't overflow, read only up to the frame that would be written next,
497 * i.e. don't read invalid entries
498 */
499 if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
500 {
501 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
502 }
503 else
504 {
505 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
506 }
507
508 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
509
510 /* read data into temporary array for unpacking */
511 trace_data = malloc(sizeof(u32) * num_frames);
512 etb_read_ram(etb, trace_data, num_frames);
513
514 if (etm_ctx->trace_depth > 0)
515 {
516 free(etm_ctx->trace_data);
517 }
518
519 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
520 etm_ctx->trace_depth = num_frames * 3;
521 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
522 etm_ctx->trace_depth = num_frames * 2;
523 else
524 etm_ctx->trace_depth = num_frames;
525
526 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
527
528 for (i = 0, j = 0; i < num_frames; i++)
529 {
530 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
531 {
532 /* trace word j */
533 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
534 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
535 etm_ctx->trace_data[j].flags = 0;
536 if ((trace_data[i] & 0x80) >> 7)
537 {
538 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
539 }
540 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
541 {
542 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
543 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
544 }
545
546 /* trace word j+1 */
547 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
548 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
549 etm_ctx->trace_data[j+1].flags = 0;
550 if ((trace_data[i] & 0x8000) >> 15)
551 {
552 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
553 }
554 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
555 {
556 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
557 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
558 }
559
560 /* trace word j+2 */
561 etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
562 etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
563 etm_ctx->trace_data[j+2].flags = 0;
564 if ((trace_data[i] & 0x800000) >> 23)
565 {
566 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
567 }
568 if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
569 {
570 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
571 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
572 }
573
574 j += 3;
575 }
576 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
577 {
578 /* trace word j */
579 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
580 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
581 etm_ctx->trace_data[j].flags = 0;
582 if ((trace_data[i] & 0x800) >> 11)
583 {
584 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
585 }
586 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
587 {
588 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
589 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
590 }
591
592 /* trace word j+1 */
593 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
594 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
595 etm_ctx->trace_data[j+1].flags = 0;
596 if ((trace_data[i] & 0x800000) >> 23)
597 {
598 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
599 }
600 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
601 {
602 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
603 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
604 }
605
606 j += 2;
607 }
608 else
609 {
610 /* trace word j */
611 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
612 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
613 etm_ctx->trace_data[j].flags = 0;
614 if ((trace_data[i] & 0x80000) >> 19)
615 {
616 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
617 }
618 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
619 {
620 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
621 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
622 }
623
624 j += 1;
625 }
626 }
627
628 free(trace_data);
629
630 return ERROR_OK;
631 }
632
633 static int etb_start_capture(etm_context_t *etm_ctx)
634 {
635 etb_t *etb = etm_ctx->capture_driver_priv;
636 u32 etb_ctrl_value = 0x1;
637 u32 trigger_count;
638
639 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
640 {
641 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
642 {
643 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
644 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
645 }
646 etb_ctrl_value |= 0x2;
647 }
648
649 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
650 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
651
652 trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
653
654 etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
655 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
656 etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
657 jtag_execute_queue();
658
659 /* we're starting a new trace, initialize capture status */
660 etm_ctx->capture_status = TRACE_RUNNING;
661
662 return ERROR_OK;
663 }
664
665 static int etb_stop_capture(etm_context_t *etm_ctx)
666 {
667 etb_t *etb = etm_ctx->capture_driver_priv;
668 reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
669
670 etb_write_reg(etb_ctrl_reg, 0x0);
671 jtag_execute_queue();
672
673 /* trace stopped, just clear running flag, but preserve others */
674 etm_ctx->capture_status &= ~TRACE_RUNNING;
675
676 return ERROR_OK;
677 }
678
679 etm_capture_driver_t etb_capture_driver =
680 {
681 .name = "etb",
682 .register_commands = etb_register_commands,
683 .init = etb_init,
684 .status = etb_status,
685 .start_capture = etb_start_capture,
686 .stop_capture = etb_stop_capture,
687 .read_trace = etb_read_trace,
688 };
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