target: create/use register_cache_invalidate()
[openocd.git] / src / target / mips32.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2007,2008 √ėyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "mips32.h"
30 #include "register.h"
31
32
33 char* mips32_core_reg_list[] =
34 {
35 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
36 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
37 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
38 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
39 "status", "lo", "hi", "badvaddr", "cause", "pc"
40 };
41
42 struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
43 {
44 {0, NULL, NULL},
45 {1, NULL, NULL},
46 {2, NULL, NULL},
47 {3, NULL, NULL},
48 {4, NULL, NULL},
49 {5, NULL, NULL},
50 {6, NULL, NULL},
51 {7, NULL, NULL},
52 {8, NULL, NULL},
53 {9, NULL, NULL},
54 {10, NULL, NULL},
55 {11, NULL, NULL},
56 {12, NULL, NULL},
57 {13, NULL, NULL},
58 {14, NULL, NULL},
59 {15, NULL, NULL},
60 {16, NULL, NULL},
61 {17, NULL, NULL},
62 {18, NULL, NULL},
63 {19, NULL, NULL},
64 {20, NULL, NULL},
65 {21, NULL, NULL},
66 {22, NULL, NULL},
67 {23, NULL, NULL},
68 {24, NULL, NULL},
69 {25, NULL, NULL},
70 {26, NULL, NULL},
71 {27, NULL, NULL},
72 {28, NULL, NULL},
73 {29, NULL, NULL},
74 {30, NULL, NULL},
75 {31, NULL, NULL},
76
77 {32, NULL, NULL},
78 {33, NULL, NULL},
79 {34, NULL, NULL},
80 {35, NULL, NULL},
81 {36, NULL, NULL},
82 {37, NULL, NULL},
83 };
84
85 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
86 * we also add 18 unknown registers to handle gdb requests */
87
88 #define MIPS32NUMFPREGS 34 + 18
89
90 uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
91
92 struct reg mips32_gdb_dummy_fp_reg =
93 {
94 .name = "GDB dummy floating-point register",
95 .value = mips32_gdb_dummy_fp_value,
96 .dirty = 0,
97 .valid = 1,
98 .size = 32,
99 .arch_info = NULL,
100 };
101
102 int mips32_get_core_reg(struct reg *reg)
103 {
104 int retval;
105 struct mips32_core_reg *mips32_reg = reg->arch_info;
106 struct target *target = mips32_reg->target;
107 struct mips32_common *mips32_target = target->arch_info;
108
109 if (target->state != TARGET_HALTED)
110 {
111 return ERROR_TARGET_NOT_HALTED;
112 }
113
114 retval = mips32_target->read_core_reg(target, mips32_reg->num);
115
116 return retval;
117 }
118
119 int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
120 {
121 struct mips32_core_reg *mips32_reg = reg->arch_info;
122 struct target *target = mips32_reg->target;
123 uint32_t value = buf_get_u32(buf, 0, 32);
124
125 if (target->state != TARGET_HALTED)
126 {
127 return ERROR_TARGET_NOT_HALTED;
128 }
129
130 buf_set_u32(reg->value, 0, 32, value);
131 reg->dirty = 1;
132 reg->valid = 1;
133
134 return ERROR_OK;
135 }
136
137 int mips32_read_core_reg(struct target *target, int num)
138 {
139 uint32_t reg_value;
140 struct mips32_core_reg *mips_core_reg;
141
142 /* get pointers to arch-specific information */
143 struct mips32_common *mips32 = target->arch_info;
144
145 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
146 return ERROR_INVALID_ARGUMENTS;
147
148 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
149 reg_value = mips32->core_regs[num];
150 buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
151 mips32->core_cache->reg_list[num].valid = 1;
152 mips32->core_cache->reg_list[num].dirty = 0;
153
154 return ERROR_OK;
155 }
156
157 int mips32_write_core_reg(struct target *target, int num)
158 {
159 uint32_t reg_value;
160 struct mips32_core_reg *mips_core_reg;
161
162 /* get pointers to arch-specific information */
163 struct mips32_common *mips32 = target->arch_info;
164
165 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
166 return ERROR_INVALID_ARGUMENTS;
167
168 reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
169 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
170 mips32->core_regs[num] = reg_value;
171 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
172 mips32->core_cache->reg_list[num].valid = 1;
173 mips32->core_cache->reg_list[num].dirty = 0;
174
175 return ERROR_OK;
176 }
177
178 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
179 {
180 /* get pointers to arch-specific information */
181 struct mips32_common *mips32 = target->arch_info;
182 int i;
183
184 /* include floating point registers */
185 *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
186 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
187
188 for (i = 0; i < MIPS32NUMCOREREGS; i++)
189 {
190 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
191 }
192
193 /* add dummy floating points regs */
194 for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
195 {
196 (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
197 }
198
199 return ERROR_OK;
200 }
201
202 int mips32_save_context(struct target *target)
203 {
204 int i;
205
206 /* get pointers to arch-specific information */
207 struct mips32_common *mips32 = target->arch_info;
208 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
209
210 /* read core registers */
211 mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
212
213 for (i = 0; i < MIPS32NUMCOREREGS; i++)
214 {
215 if (!mips32->core_cache->reg_list[i].valid)
216 {
217 mips32->read_core_reg(target, i);
218 }
219 }
220
221 return ERROR_OK;
222 }
223
224 int mips32_restore_context(struct target *target)
225 {
226 int i;
227
228 /* get pointers to arch-specific information */
229 struct mips32_common *mips32 = target->arch_info;
230 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
231
232 for (i = 0; i < MIPS32NUMCOREREGS; i++)
233 {
234 if (mips32->core_cache->reg_list[i].dirty)
235 {
236 mips32->write_core_reg(target, i);
237 }
238 }
239
240 /* write core regs */
241 mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
242
243 return ERROR_OK;
244 }
245
246 int mips32_arch_state(struct target *target)
247 {
248 struct mips32_common *mips32 = target->arch_info;
249
250 if (mips32->common_magic != MIPS32_COMMON_MAGIC)
251 {
252 LOG_ERROR("BUG: called for a non-MIPS32 target");
253 return ERROR_FAIL;
254 }
255
256 LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
257 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
258 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
259
260 return ERROR_OK;
261 }
262
263 static const struct reg_arch_type mips32_reg_type = {
264 .get = mips32_get_core_reg,
265 .set = mips32_set_core_reg,
266 };
267
268 struct reg_cache *mips32_build_reg_cache(struct target *target)
269 {
270 /* get pointers to arch-specific information */
271 struct mips32_common *mips32 = target->arch_info;
272
273 int num_regs = MIPS32NUMCOREREGS;
274 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
275 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
276 struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
277 struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
278 int i;
279
280 register_init_dummy(&mips32_gdb_dummy_fp_reg);
281
282 /* Build the process context cache */
283 cache->name = "mips32 registers";
284 cache->next = NULL;
285 cache->reg_list = reg_list;
286 cache->num_regs = num_regs;
287 (*cache_p) = cache;
288 mips32->core_cache = cache;
289
290 for (i = 0; i < num_regs; i++)
291 {
292 arch_info[i] = mips32_core_reg_list_arch_info[i];
293 arch_info[i].target = target;
294 arch_info[i].mips32_common = mips32;
295 reg_list[i].name = mips32_core_reg_list[i];
296 reg_list[i].size = 32;
297 reg_list[i].value = calloc(1, 4);
298 reg_list[i].dirty = 0;
299 reg_list[i].valid = 0;
300 reg_list[i].type = &mips32_reg_type;
301 reg_list[i].arch_info = &arch_info[i];
302 }
303
304 return cache;
305 }
306
307 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
308 {
309 target->arch_info = mips32;
310 mips32->common_magic = MIPS32_COMMON_MAGIC;
311
312 /* has breakpoint/watchpint unit been scanned */
313 mips32->bp_scanned = 0;
314 mips32->data_break_list = NULL;
315
316 mips32->ejtag_info.tap = tap;
317 mips32->read_core_reg = mips32_read_core_reg;
318 mips32->write_core_reg = mips32_write_core_reg;
319
320 return ERROR_OK;
321 }
322
323 int mips32_register_commands(struct command_context *cmd_ctx)
324 {
325 return ERROR_OK;
326 }
327
328 int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
329 {
330 /*TODO*/
331 return ERROR_OK;
332 }
333
334 int mips32_examine(struct target *target)
335 {
336 struct mips32_common *mips32 = target->arch_info;
337
338 if (!target_was_examined(target))
339 {
340 target_set_examined(target);
341
342 /* we will configure later */
343 mips32->bp_scanned = 0;
344 mips32->num_inst_bpoints = 0;
345 mips32->num_data_bpoints = 0;
346 mips32->num_inst_bpoints_avail = 0;
347 mips32->num_data_bpoints_avail = 0;
348 }
349
350 return ERROR_OK;
351 }
352
353 int mips32_configure_break_unit(struct target *target)
354 {
355 /* get pointers to arch-specific information */
356 struct mips32_common *mips32 = target->arch_info;
357 int retval;
358 uint32_t dcr, bpinfo;
359 int i;
360
361 if (mips32->bp_scanned)
362 return ERROR_OK;
363
364 /* get info about breakpoint support */
365 if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
366 return retval;
367
368 if (dcr & (1 << 16))
369 {
370 /* get number of inst breakpoints */
371 if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
372 return retval;
373
374 mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
375 mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
376 mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
377 for (i = 0; i < mips32->num_inst_bpoints; i++)
378 {
379 mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
380 }
381
382 /* clear IBIS reg */
383 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
384 return retval;
385 }
386
387 if (dcr & (1 << 17))
388 {
389 /* get number of data breakpoints */
390 if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
391 return retval;
392
393 mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
394 mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
395 mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
396 for (i = 0; i < mips32->num_data_bpoints; i++)
397 {
398 mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
399 }
400
401 /* clear DBIS reg */
402 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
403 return retval;
404 }
405
406 LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
407
408 mips32->bp_scanned = 1;
409
410 return ERROR_OK;
411 }
412
413 int mips32_enable_interrupts(struct target *target, int enable)
414 {
415 int retval;
416 int update = 0;
417 uint32_t dcr;
418
419 /* read debug control register */
420 if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
421 return retval;
422
423 if (enable)
424 {
425 if (!(dcr & (1 << 4)))
426 {
427 /* enable interrupts */
428 dcr |= (1 << 4);
429 update = 1;
430 }
431 }
432 else
433 {
434 if (dcr & (1 << 4))
435 {
436 /* disable interrupts */
437 dcr &= ~(1 << 4);
438 update = 1;
439 }
440 }
441
442 if (update)
443 {
444 if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
445 return retval;
446 }
447
448 return ERROR_OK;
449 }

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