1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
36 char* mips32_core_reg_list
[] =
38 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
39 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
40 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
41 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
42 "status", "lo", "hi", "badvaddr", "cause", "pc"
45 mips32_core_reg_t mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] =
88 u8 mips32_gdb_dummy_fsr_value
[] = {0, 0, 0, 0};
90 reg_t mips32_gdb_dummy_fsr_reg
=
92 "GDB dummy floating-point status register", mips32_gdb_dummy_fsr_value
, 0, 1, 32, NULL
, 0, NULL
, 0
95 u8 mips32_gdb_dummy_fir_value
[] = {0, 0, 0, 0};
97 reg_t mips32_gdb_dummy_fir_reg
=
99 "GDB dummy floating-point register", mips32_gdb_dummy_fir_value
, 0, 1, 32, NULL
, 0, NULL
, 0
102 int mips32_core_reg_arch_type
= -1;
104 int mips32_get_core_reg(reg_t
*reg
)
107 mips32_core_reg_t
*mips32_reg
= reg
->arch_info
;
108 target_t
*target
= mips32_reg
->target
;
109 mips32_common_t
*mips32_target
= target
->arch_info
;
111 if (target
->state
!= TARGET_HALTED
)
113 return ERROR_TARGET_NOT_HALTED
;
116 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
121 int mips32_set_core_reg(reg_t
*reg
, u8
*buf
)
123 mips32_core_reg_t
*mips32_reg
= reg
->arch_info
;
124 target_t
*target
= mips32_reg
->target
;
125 u32 value
= buf_get_u32(buf
, 0, 32);
127 if (target
->state
!= TARGET_HALTED
)
129 return ERROR_TARGET_NOT_HALTED
;
132 buf_set_u32(reg
->value
, 0, 32, value
);
139 int mips32_read_core_reg(struct target_s
*target
, int num
)
142 mips32_core_reg_t
*mips_core_reg
;
144 /* get pointers to arch-specific information */
145 mips32_common_t
*mips32
= target
->arch_info
;
147 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
148 return ERROR_INVALID_ARGUMENTS
;
150 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
151 reg_value
= mips32
->core_regs
[num
];
152 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
153 mips32
->core_cache
->reg_list
[num
].valid
= 1;
154 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
159 int mips32_write_core_reg(struct target_s
*target
, int num
)
162 mips32_core_reg_t
*mips_core_reg
;
164 /* get pointers to arch-specific information */
165 mips32_common_t
*mips32
= target
->arch_info
;
167 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
168 return ERROR_INVALID_ARGUMENTS
;
170 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
171 mips_core_reg
= mips32
->core_cache
->reg_list
[num
].arch_info
;
172 mips32
->core_regs
[num
] = reg_value
;
173 LOG_DEBUG("write core reg %i value 0x%x", num
, reg_value
);
174 mips32
->core_cache
->reg_list
[num
].valid
= 1;
175 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
180 int mips32_invalidate_core_regs(target_t
*target
)
182 /* get pointers to arch-specific information */
183 mips32_common_t
*mips32
= target
->arch_info
;
186 for (i
= 0; i
< mips32
->core_cache
->num_regs
; i
++)
188 mips32
->core_cache
->reg_list
[i
].valid
= 0;
189 mips32
->core_cache
->reg_list
[i
].dirty
= 0;
195 int mips32_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
197 /* get pointers to arch-specific information */
198 mips32_common_t
*mips32
= target
->arch_info
;
201 /* include fsr/fir reg */
202 *reg_list_size
= MIPS32NUMCOREREGS
+ 2;
203 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
205 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
207 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
210 /* add dummy floating points regs */
211 (*reg_list
)[38] = &mips32_gdb_dummy_fsr_reg
;
212 (*reg_list
)[39] = &mips32_gdb_dummy_fir_reg
;
217 int mips32_save_context(target_t
*target
)
221 /* get pointers to arch-specific information */
222 mips32_common_t
*mips32
= target
->arch_info
;
223 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
225 /* read core registers */
226 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
228 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
230 if (!mips32
->core_cache
->reg_list
[i
].valid
)
232 mips32
->read_core_reg(target
, i
);
239 int mips32_restore_context(target_t
*target
)
243 /* get pointers to arch-specific information */
244 mips32_common_t
*mips32
= target
->arch_info
;
245 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
247 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
249 if (mips32
->core_cache
->reg_list
[i
].dirty
)
251 mips32
->write_core_reg(target
, i
);
255 /* write core regs */
256 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
261 int mips32_arch_state(struct target_s
*target
)
263 mips32_common_t
*mips32
= target
->arch_info
;
265 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
)
267 LOG_ERROR("BUG: called for a non-MIPS32 target");
271 LOG_USER("target halted due to %s, pc: 0x%8.8x",
272 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
273 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
278 reg_cache_t
*mips32_build_reg_cache(target_t
*target
)
280 /* get pointers to arch-specific information */
281 mips32_common_t
*mips32
= target
->arch_info
;
283 int num_regs
= MIPS32NUMCOREREGS
;
284 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
285 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
286 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
287 mips32_core_reg_t
*arch_info
= malloc(sizeof(mips32_core_reg_t
) * num_regs
);
290 if (mips32_core_reg_arch_type
== -1)
291 mips32_core_reg_arch_type
= register_reg_arch_type(mips32_get_core_reg
, mips32_set_core_reg
);
293 register_init_dummy(&mips32_gdb_dummy_fsr_reg
);
294 register_init_dummy(&mips32_gdb_dummy_fir_reg
);
296 /* Build the process context cache */
297 cache
->name
= "mips32 registers";
299 cache
->reg_list
= reg_list
;
300 cache
->num_regs
= num_regs
;
302 mips32
->core_cache
= cache
;
304 for (i
= 0; i
< num_regs
; i
++)
306 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
307 arch_info
[i
].target
= target
;
308 arch_info
[i
].mips32_common
= mips32
;
309 reg_list
[i
].name
= mips32_core_reg_list
[i
];
310 reg_list
[i
].size
= 32;
311 reg_list
[i
].value
= calloc(1, 4);
312 reg_list
[i
].dirty
= 0;
313 reg_list
[i
].valid
= 0;
314 reg_list
[i
].bitfield_desc
= NULL
;
315 reg_list
[i
].num_bitfields
= 0;
316 reg_list
[i
].arch_type
= mips32_core_reg_arch_type
;
317 reg_list
[i
].arch_info
= &arch_info
[i
];
323 int mips32_init_arch_info(target_t
*target
, mips32_common_t
*mips32
, int chain_pos
, const char *variant
)
325 target
->arch_info
= mips32
;
326 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
328 mips32
->ejtag_info
.chain_pos
= chain_pos
;
329 mips32
->read_core_reg
= mips32_read_core_reg
;
330 mips32
->write_core_reg
= mips32_write_core_reg
;
335 int mips32_register_commands(struct command_context_s
*cmd_ctx
)
340 int mips32_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
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