src/target/mips32.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2008 by Spencer Oliver                                  *
   5  *   spen@spen-soft.co.uk                                                  *
   6  *                                                                         *
   7  *   Copyright (C) 2008 by David T.L. Wong                                 *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  ***************************************************************************/
  12
  13 #ifndef OPENOCD_TARGET_MIPS32_H
  14 #define OPENOCD_TARGET_MIPS32_H
  15
  16 #include <helper/bits.h>
  17
  18 #include "target.h"
  19 #include "mips32_pracc.h"
  20
  21 #define MIPS32_COMMON_MAGIC             0xB320B320U
  22
  23 /**
  24  * Memory segments (32bit kernel mode addresses)
  25  * These are the traditional names used in the 32-bit universe.
  26  */
  27 #define KUSEG                   0x00000000
  28 #define KSEG0                   0x80000000
  29 #define KSEG1                   0xa0000000
  30 #define KSEG2                   0xc0000000
  31 #define KSEG3                   0xe0000000
  32
  33 /** Returns the kernel segment base of a given address */
  34 #define KSEGX(a)                ((a) & 0xe0000000)
  35
  36 /** CP0 CONFIG register fields */
  37 #define MIPS32_CONFIG0_KU_SHIFT 25
  38 #define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)
  39
  40 #define MIPS32_CONFIG0_K0_SHIFT 0
  41 #define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT)
  42
  43 #define MIPS32_CONFIG0_K23_SHIFT 28
  44 #define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT)
  45
  46 #define MIPS32_CONFIG0_AR_SHIFT 10
  47 #define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)
  48
  49 #define MIPS32_CONFIG1_FP_SHIFT 0
  50 #define MIPS32_CONFIG1_FP_MASK  BIT(MIPS32_CONFIG1_FP_SHIFT)
  51
  52 #define MIPS32_CONFIG1_DL_SHIFT 10
  53 #define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)
  54
  55 #define MIPS32_CONFIG3_CDMM_SHIFT       3
  56 #define MIPS32_CONFIG3_CDMM_MASK        BIT(MIPS32_CONFIG3_CDMM_SHIFT)
  57
  58 #define MIPS32_CONFIG3_DSPP_SHIFT       10
  59 #define MIPS32_CONFIG3_DSPP_MASK        BIT(MIPS32_CONFIG3_DSPP_SHIFT)
  60
  61 #define MIPS32_CONFIG3_DSPREV_SHIFT     11
  62 #define MIPS32_CONFIG3_DSPREV_MASK      BIT(MIPS32_CONFIG3_DSPREV_SHIFT)
  63
  64 #define MIPS32_CONFIG3_ISA_SHIFT        14
  65 #define MIPS32_CONFIG3_ISA_MASK         (3 << MIPS32_CONFIG3_ISA_SHIFT)
  66
  67 #define MIPS32_ARCH_REL1 0x0
  68 #define MIPS32_ARCH_REL2 0x1
  69
  70 #define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
  71
  72 #define MIPS32_NUM_DSPREGS              9
  73
  74 /* Bit Mask indicating CP0 register supported by this core */
  75 #define MIPS_CP0_MK4            0x0001
  76 #define MIPS_CP0_MAPTIV_UC      0x0002
  77 #define MIPS_CP0_MAPTIV_UP      0x0004
  78 #define MIPS_CP0_IAPTIV         0x0008
  79
  80 /* CP0 Status register fields */
  81 #define MIPS32_CP0_STATUS_FR_SHIFT      26
  82 #define MIPS32_CP0_STATUS_CU1_SHIFT     29
  83
  84 /* CP1 FIR register fields */
  85 #define MIPS32_CP1_FIR_F64_SHIFT        22
  86
  87 static const struct mips32_cp0 {
  88         unsigned int reg;
  89         unsigned int sel;
  90         const char *name;
  91         const unsigned int core;
  92 } mips32_cp0_regs[] = {
  93         {0, 0, "index", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
  94         {0, 1, "mvpcontrol", MIPS_CP0_IAPTIV},
  95         {0, 2, "mvpconf0", MIPS_CP0_IAPTIV},
  96         {0, 3, "mvpconf1", MIPS_CP0_IAPTIV},
  97         {1, 0, "random", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
  98         {1, 1, "vpecontrol", MIPS_CP0_IAPTIV},
  99         {1, 2, "vpeconf0", MIPS_CP0_IAPTIV},
 100         {1, 3, "vpeconf1", MIPS_CP0_IAPTIV},
 101         {1, 4, "yqmask", MIPS_CP0_IAPTIV},
 102         {1, 5, "vpeschedule", MIPS_CP0_IAPTIV},
 103         {1, 6, "vpeschefback", MIPS_CP0_IAPTIV},
 104         {1, 7, "vpeopt", MIPS_CP0_IAPTIV},
 105         {2, 0, "entrylo0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
 106         {2, 1, "tcstatus", MIPS_CP0_IAPTIV},
 107         {2, 2, "tcbind", MIPS_CP0_IAPTIV},
 108         {2, 3, "tcrestart", MIPS_CP0_IAPTIV},
 109         {2, 4, "tchalt", MIPS_CP0_IAPTIV},
 110         {2, 5, "tccontext", MIPS_CP0_IAPTIV},
 111         {2, 6, "tcschedule", MIPS_CP0_IAPTIV},
 112         {2, 7, "tcschefback", MIPS_CP0_IAPTIV},
 113         {3, 0, "entrylo1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
 114         {3, 7, "tcopt", MIPS_CP0_IAPTIV},
 115         {4, 0, "context", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
 116         {4, 2, "userlocal", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 117         {5, 0, "pagemask", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
 118         {5, 1, "pagegrain", MIPS_CP0_MAPTIV_UP},
 119         {5, 2, "segctl0", MIPS_CP0_IAPTIV},
 120         {5, 3, "segctl1", MIPS_CP0_IAPTIV},
 121         {5, 4, "segctl2", MIPS_CP0_IAPTIV},
 122         {6, 0, "wired", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
 123         {6, 1, "srsconf0", MIPS_CP0_IAPTIV},
 124         {6, 2, "srsconf1", MIPS_CP0_IAPTIV},
 125         {6, 3, "srsconf2", MIPS_CP0_IAPTIV},
 126         {6, 4, "srsconf3", MIPS_CP0_IAPTIV},
 127         {6, 5, "srsconf4", MIPS_CP0_IAPTIV},
 128         {7, 0, "hwrena", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 129         {8, 0, "badvaddr", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 130         {8, 1, "badinstr", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
 131         {8, 2, "badinstrp", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
 132         {9, 0, "count", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 133         {10, 0, "entryhi", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
 134         {10, 4, "guestctl1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
 135         {10, 5, "guestctl2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
 136         {10, 6, "guestctl3", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
 137         {11, 0, "compare", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 138         {11, 4, "guestctl0ext", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
 139         {12, 0, "status", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 140         {12, 1, "intctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 141         {12, 2, "srsctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 142         {12, 3, "srsmap", MIPS_CP0_IAPTIV},
 143         {12, 3, "srsmap1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
 144         {12, 4, "view_ipl", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 145         {12, 5, "srsmap2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
 146         {12, 6, "guestctl0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
 147         {12, 7, "gtoffset", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
 148         {13, 0, "cause", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 149         {13, 5, "nestedexc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 150         {14, 0, "epc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 151         {14, 2, "nestedepc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 152         {15, 0, "prid", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 153         {15, 1, "ebase", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 154         {15, 2, "cdmmbase", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 155         {15, 3, "cmgcrbase", MIPS_CP0_IAPTIV},
 156         {16, 0, "config", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 157         {16, 1, "config1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 158         {16, 2, "config2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 159         {16, 3, "config3", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 160         {16, 4, "config4", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 161         {16, 5, "config5", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 162         {16, 7, "config7", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 163         {17, 0, "lladdr", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 164         {18, 0, "watchlo0", MIPS_CP0_IAPTIV},
 165         {18, 1, "watchlo1", MIPS_CP0_IAPTIV},
 166         {18, 2, "watchlo2", MIPS_CP0_IAPTIV},
 167         {18, 3, "watchlo3", MIPS_CP0_IAPTIV},
 168         {19, 0, "watchhi0", MIPS_CP0_IAPTIV},
 169         {19, 1, "watchhi1", MIPS_CP0_IAPTIV},
 170         {19, 2, "watchhi2", MIPS_CP0_IAPTIV},
 171         {19, 3, "watchhi3", MIPS_CP0_IAPTIV},
 172         {23, 0, "debug", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 173         {23, 1, "tracecontrol", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 174         {23, 2, "tracecontrol2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 175         {23, 3, "usertracedata1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 176         {23, 4, "tracebpc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 177         {23, 4, "traceibpc", MIPS_CP0_IAPTIV},
 178         {23, 5, "tracedbpc", MIPS_CP0_IAPTIV},
 179         {24, 0, "depc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 180         {24, 2, "tracecontrol3", MIPS_CP0_IAPTIV},
 181         {24, 3, "usertracedata2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 182         {25, 0, "perfctl0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 183         {25, 1, "perfcnt0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 184         {25, 2, "perfctl1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 185         {25, 3, "perfcnt1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 186         {26, 0, "errctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 187         {27, 0, "cacheerr", MIPS_CP0_IAPTIV},
 188         {28, 0, "itaglo", MIPS_CP0_IAPTIV},
 189         {28, 0, "taglo", MIPS_CP0_IAPTIV},
 190         {28, 1, "idatalo", MIPS_CP0_IAPTIV},
 191         {28, 1, "datalo", MIPS_CP0_IAPTIV},
 192         {28, 2, "dtaglo", MIPS_CP0_IAPTIV},
 193         {28, 3, "ddatalo", MIPS_CP0_IAPTIV},
 194         {28, 4, "l23taglo", MIPS_CP0_IAPTIV},
 195         {28, 5, "l23datalo", MIPS_CP0_IAPTIV},
 196         {29, 1, "idatahi", MIPS_CP0_IAPTIV},
 197         {29, 2, "dtaghi", MIPS_CP0_IAPTIV},
 198         {29, 5, "l23datahi", MIPS_CP0_IAPTIV},
 199         {30, 0, "errorepc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 200         {31, 0, "desave", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
 201         {31, 2, "kscratch1", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
 202         {31, 3, "kscratch2", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
 203 };
 204
 205 #define MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs))
 206
 207 /* Insert extra NOPs after the DRET instruction on exit from debug. */
 208 #define EJTAG_QUIRK_PAD_DRET            BIT(0)
 209
 210 /* offsets into mips32 core register cache */
 211 enum {
 212         MIPS32_PC = 37,
 213         MIPS32_FIR = 71,
 214         MIPS32NUMCOREREGS
 215 };
 216
 217 /* offsets into mips32 core register cache */
 218
 219 #define MIPS32_REG_GP_COUNT                     34
 220 #define MIPS32_REG_FP_COUNT                     32
 221 #define MIPS32_REG_FPC_COUNT                    2
 222 #define MIPS32_REG_C0_COUNT                     5
 223
 224 #define MIPS32_REGLIST_GP_INDEX                 0
 225 #define MIPS32_REGLIST_FP_INDEX                 (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT)
 226 #define MIPS32_REGLIST_FPC_INDEX                (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT)
 227 #define MIPS32_REGLIST_C0_INDEX                 (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT)
 228
 229 #define MIPS32_REGLIST_C0_STATUS_INDEX          (MIPS32_REGLIST_C0_INDEX + 0)
 230 #define MIPS32_REGLIST_C0_BADVADDR_INDEX        (MIPS32_REGLIST_C0_INDEX + 1)
 231 #define MIPS32_REGLIST_C0_CAUSE_INDEX           (MIPS32_REGLIST_C0_INDEX + 2)
 232 #define MIPS32_REGLIST_C0_PC_INDEX              (MIPS32_REGLIST_C0_INDEX + 3)
 233 #define MIPS32_REGLIST_C0_GUESTCTL1_INDEX       (MIPS32_REGLIST_C0_INDEX + 4)
 234
 235 #define MIPS32_REG_C0_STATUS_INDEX              0
 236 #define MIPS32_REG_C0_BADVADDR_INDEX            1
 237 #define MIPS32_REG_C0_CAUSE_INDEX               2
 238 #define MIPS32_REG_C0_PC_INDEX                  3
 239 #define MIPS32_REG_C0_GUESTCTL1_INDEX           4
 240
 241 enum mips32_isa_mode {
 242         MIPS32_ISA_MIPS32 = 0,
 243         MIPS32_ISA_MIPS16E = 1,
 244         MIPS32_ISA_MMIPS32 = 3,
 245 };
 246
 247 enum mips32_isa_imp {
 248         MIPS32_ONLY = 0,
 249         MMIPS32_ONLY = 1,
 250         MIPS32_MIPS16 = 2,
 251         MIPS32_MMIPS32 = 3,
 252 };
 253
 254 /* Release 2~5 does not have much change regarding to the ISA under User mode,
 255 * therefore no new Architecture Revision(AR) level is assigned to them.
 256 * Release 6 changed some instruction's encoding/mnemonic, removed instructions that
 257 * has lost its purposes/none are using, and added some new instructions as well.
 258 */
 259 enum mips32_isa_rel {
 260         MIPS32_RELEASE_1 = 0,
 261         MIPS32_RELEASE_2 = 1,
 262         MIPS32_RELEASE_6 = 2,
 263         MIPS32_RELEASE_UNKNOWN,
 264 };
 265
 266 enum mips32_isa_supported {
 267         MIPS16,
 268         MIPS32,
 269         MIPS64,
 270         MICROMIPS_ONLY,
 271         MIPS32_AT_RESET_AND_MICROMIPS,
 272         MICROMIPS_AT_RESET_AND_MIPS32,
 273 };
 274 #define MIPS32_CORE_MASK        0xFFFFFF00
 275 #define MIPS32_VARIANT_MASK     0x00FF
 276
 277 /* This struct contains mips cpu types with their name respectively.
 278  * The PrID register format is as following:
 279  *  - Company Optionsp[31:24]
 280  *  - Company ID[23:16]
 281  *  - Processor ID[15:8]
 282  *  - Revision[7:0]
 283  * Here the revision field represents the maximum value of revision.
 284  */
 285 static const struct cpu_entry {
 286         uint32_t prid;
 287         enum mips32_isa_supported isa;
 288         const char *vendor;
 289         const char *cpu_name;
 290 } mips32_cpu_entry[] = {
 291         /* MIPS Technologies cores */
 292         {0x000180FF, MIPS32, "MIPS", "4Kc"},
 293         {0x000181FF, MIPS64, "MIPS", "5Kc"},
 294         {0x000182FF, MIPS64, "MIPS", "20Kc"},
 295         {0x000183FF, MIPS32, "MIPS", "4KM"},
 296
 297         {0x000184FF, MIPS32, "MIPS", "4KEc"},
 298         {0x000190FF, MIPS32, "MIPS", "4KEc"},
 299
 300         {0x000185FF, MIPS32, "MIPS", "4KEm"},
 301         {0x000191FF, MIPS32, "MIPS", "4KEm"},
 302
 303         {0x000186FF, MIPS32, "MIPS", "4KSc"},
 304         {0x000187FF, MIPS32, "MIPS", "M4K"},
 305         {0x000188FF, MIPS64, "MIPS", "25Kf"},
 306         {0x000189FF, MIPS64, "MIPS", "5KEc"},
 307         {0x000192FF, MIPS32, "MIPS", "4KSD"},
 308         {0x000193FF, MIPS32, "MIPS", "24Kc"},
 309         {0x000195FF, MIPS32, "MIPS", "34Kc"},
 310         {0x000196FF, MIPS32, "MIPS", "24KEc"},
 311         {0x000197FF, MIPS32, "MIPS", "74Kc"},
 312         {0x000199FF, MIPS32, "MIPS", "1004Kc"},
 313         {0x00019AFF, MIPS32, "MIPS", "1074Kc"},
 314         {0x00019BFF, MIPS32, "MIPS", "M14K"},
 315         {0x00019CFF, MIPS32, "MIPS", "M14Kc"},
 316         {0x00019DFF, MIPS32, "MIPS", "microAptiv_UC(M14KE)"},
 317         {0x00019EFF, MIPS32, "MIPS", "microAptiv_UP(M14KEc)"},
 318         {0x0001A0FF, MIPS32, "MIPS", "interAptiv"},
 319         {0x0001A1FF, MIPS32, "MIPS", "interAptiv_CM"},
 320         {0x0001A2FF, MIPS32, "MIPS", "proAptiv"},
 321         {0x0001A3FF, MIPS32, "MIPS", "proAptiv_CM"},
 322         {0x0001A6FF, MIPS32, "MIPS", "M5100"},
 323         {0x0001A7FF, MIPS32, "MIPS", "M5150"},
 324         {0x0001A8FF, MIPS32, "MIPS", "P5600"},
 325         {0x0001A9FF, MIPS32, "MIPS", "I5500"},
 326
 327         /* Broadcom */
 328         {0x000200FF, MIPS32, "Broadcom", "Broadcom"},
 329
 330         /* AMD Alchemy Series*/
 331         /* NOTE: AMD/Alchemy series uses Company Option instead of
 332          * Processor ID, to match the find function, Processor ID field
 333          * is the copy of Company Option field */
 334         {0x000300FF, MIPS32, "AMD Alchemy", "AU1000"},
 335         {0x010301FF, MIPS32, "AMD Alchemy", "AU1500"},
 336         {0x020302FF, MIPS32, "AMD Alchemy", "AU1100"},
 337         {0x030303FF, MIPS32, "AMD Alchemy", "AU1550"},
 338         {0x04030401, MIPS32, "AMD Alchemy", "AU1200"},
 339         {0x040304FF, MIPS32, "AMD Alchemy", "AU1250"},
 340         {0x050305FF, MIPS32, "AMD Alchemy", "AU1210"},
 341
 342         /* Altera */
 343         {0x001000FF, MIPS32, "Altera", "Altera"},
 344
 345         /* Lexra */
 346         {0x000B00FF, MIPS32, "Lexra", "Lexra"},
 347
 348         /* Ingenic */
 349         {0x00e102FF, MIPS32, "Ingenic", "Ingenic XBurst rev1"},
 350
 351         {0xFFFFFFFF, MIPS32, "Unknown", "Unknown"}
 352 };
 353
 354 #define MIPS32_NUM_CPU_ENTRIES (ARRAY_SIZE(mips32_cpu_entry))
 355
 356 enum mips32_fp_imp {
 357         MIPS32_FP_IMP_NONE = 0,
 358         MIPS32_FP_IMP_32 = 1,
 359         MIPS32_FP_IMP_64 = 2,
 360         MIPS32_FP_IMP_UNKNOWN = 3,
 361 };
 362
 363 enum mips32_dsp_imp {
 364         MIPS32_DSP_IMP_NONE = 0,
 365         MIPS32_DSP_IMP_REV1 = 1,
 366         MIPS32_DSP_IMP_REV2 = 2,
 367 };
 368
 369 struct mips32_comparator {
 370         int used;
 371         uint32_t bp_value;
 372         uint32_t reg_address;
 373 };
 374
 375 struct mips32_core_regs {
 376         uint32_t gpr[MIPS32_REG_GP_COUNT];
 377         uint64_t fpr[MIPS32_REG_FP_COUNT];
 378         uint32_t fpcr[MIPS32_REG_FPC_COUNT];
 379         uint32_t cp0[MIPS32_REG_C0_COUNT];
 380 };
 381
 382 struct mips32_common {
 383         unsigned int common_magic;
 384
 385         void *arch_info;
 386         struct reg_cache *core_cache;
 387         struct mips_ejtag ejtag_info;
 388
 389         struct mips32_core_regs core_regs;
 390
 391         enum mips32_isa_mode isa_mode;
 392         enum mips32_isa_imp isa_imp;
 393         enum mips32_isa_rel isa_rel;
 394         enum mips32_fp_imp fp_imp;
 395         enum mips32_dsp_imp dsp_imp;
 396
 397         int fdc;
 398         int semihosting;
 399
 400         /* The cp0 registers implemented on different processor cores could be different, too.
 401          * Here you can see most of the registers are implemented on interAptiv, which is
 402          * a 2c4t SMP processor, it has more features than M-class processors, like vpe
 403          * and other config registers for multhreading. */
 404         uint32_t cp0_mask;
 405
 406         /* FPU enabled (cp0.status.cu1) */
 407         bool fpu_enabled;
 408         /* FPU mode (cp0.status.fr) */
 409         bool fpu_in_64bit;
 410
 411         /* processor identification register */
 412         uint32_t prid;
 413         /* detected CPU type */
 414         const struct cpu_entry *cpu_info;
 415         /* CPU specific quirks */
 416         uint32_t cpu_quirks;
 417
 418         /* working area for fastdata access */
 419         struct working_area *fast_data_area;
 420
 421         int bp_scanned;
 422         int num_inst_bpoints;
 423         int num_data_bpoints;
 424         int num_inst_bpoints_avail;
 425         int num_data_bpoints_avail;
 426         struct mips32_comparator *inst_break_list;
 427         struct mips32_comparator *data_break_list;
 428
 429         /* register cache to processor synchronization */
 430         int (*read_core_reg)(struct target *target, unsigned int num);
 431         int (*write_core_reg)(struct target *target, unsigned int num);
 432 };
 433
 434 static inline struct mips32_common *
 435 target_to_mips32(struct target *target)
 436 {
 437         return target->arch_info;
 438 }
 439
 440 struct mips32_core_reg {
 441         uint32_t num;
 442         struct target *target;
 443         struct mips32_common *mips32_common;
 444 };
 445
 446 struct mips32_algorithm {
 447         unsigned int common_magic;
 448         enum mips32_isa_mode isa_mode;
 449 };
 450
 451 #define MIPS32_OP_ADDU  0x21u
 452 #define MIPS32_OP_ADDIU 0x09u
 453 #define MIPS32_OP_ANDI  0x0Cu
 454 #define MIPS32_OP_BEQ   0x04u
 455 #define MIPS32_OP_BGTZ  0x07u
 456 #define MIPS32_OP_BNE   0x05u
 457 #define MIPS32_OP_ADD   0x20u
 458 #define MIPS32_OP_ADDI  0x08u
 459 #define MIPS32_OP_AND   0x24u
 460 #define MIPS32_OP_CACHE 0x2Fu
 461 #define MIPS32_OP_COP0  0x10u
 462 #define MIPS32_OP_J     0x02u
 463 #define MIPS32_OP_JR    0x08u
 464 #define MIPS32_OP_LUI   0x0Fu
 465 #define MIPS32_OP_LW    0x23u
 466 #define MIPS32_OP_LB    0x20u
 467 #define MIPS32_OP_LBU   0x24u
 468 #define MIPS32_OP_LHU   0x25u
 469 #define MIPS32_OP_MFHI  0x10u
 470 #define MIPS32_OP_MTHI  0x11u
 471 #define MIPS32_OP_MFLO  0x12u
 472 #define MIPS32_OP_MTLO  0x13u
 473 #define MIPS32_OP_RDHWR 0x3Bu
 474 #define MIPS32_OP_SB    0x28u
 475 #define MIPS32_OP_SH    0x29u
 476 #define MIPS32_OP_SW    0x2Bu
 477 #define MIPS32_OP_ORI   0x0Du
 478 #define MIPS32_OP_XORI  0x0Eu
 479 #define MIPS32_OP_XOR   0x26u
 480 #define MIPS32_OP_SLTU  0x2Bu
 481 #define MIPS32_OP_SRL   0x02u
 482 #define MIPS32_OP_SRA   0x03u
 483 #define MIPS32_OP_SYNCI 0x1Fu
 484 #define MIPS32_OP_SLL   0x00u
 485 #define MIPS32_OP_SLLV  0x04u
 486 #define MIPS32_OP_SLTI  0x0Au
 487 #define MIPS32_OP_MOVN  0x0Bu
 488
 489 #define MIPS32_OP_REGIMM        0x01u
 490 #define MIPS32_OP_SDBBP 0x3Fu
 491 #define MIPS32_OP_SPECIAL       0x00u
 492 #define MIPS32_OP_SPECIAL2      0x07u
 493 #define MIPS32_OP_SPECIAL3      0x1Fu
 494
 495 #define MIPS32_COP_MF   0x00u
 496 #define MIPS32_COP_CF   0x02u
 497 #define MIPS32_COP_MFH  0x03u
 498 #define MIPS32_COP_MT   0x04u
 499 #define MIPS32_COP_MTH  0x07u
 500
 501 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
 502         (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
 503 #define MIPS32_I_INST(opcode, rs, rt, immd) \
 504         (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
 505 #define MIPS32_J_INST(opcode, addr)     (((opcode) << 26) | (addr))
 506
 507 #define MIPS32_ISA_NOP                          0
 508 #define MIPS32_ISA_ADD(dst, src, tar)           MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADD)
 509 #define MIPS32_ISA_ADDI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
 510 #define MIPS32_ISA_ADDIU(tar, src, val)         MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)
 511 #define MIPS32_ISA_ADDU(dst, src, tar)          MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)
 512 #define MIPS32_ISA_AND(dst, src, tar)           MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND)
 513 #define MIPS32_ISA_ANDI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)
 514
 515 #define MIPS32_ISA_B(off)                       MIPS32_ISA_BEQ(0, 0, off)
 516 #define MIPS32_ISA_BEQ(src, tar, off)           MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 517 #define MIPS32_ISA_BGTZ(reg, off)               MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
 518 #define MIPS32_ISA_BNE(src, tar, off)           MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 519 #define MIPS32_ISA_CACHE(op, off, base)         MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
 520 #define MIPS32_ISA_J(tar)                       MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)
 521 #define MIPS32_ISA_JR(reg)                      MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 522 #define MIPS32_ISA_JRHB(reg)            MIPS32_R_INST(0, reg, 0, 0, 0x10, MIPS32_OP_JR)
 523
 524 #define MIPS32_ISA_LB(reg, off, base)           MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)
 525 #define MIPS32_ISA_LBU(reg, off, base)          MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
 526 #define MIPS32_ISA_LHU(reg, off, base)          MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
 527 #define MIPS32_ISA_LUI(reg, val)                MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
 528 #define MIPS32_ISA_LW(reg, off, base)           MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
 529
 530 #define MIPS32_ISA_MFC0(gpr, cpr, sel)          MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MF, gpr, cpr, 0, sel)
 531 #define MIPS32_ISA_MTC0(gpr, cpr, sel)          MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP_MT, gpr, cpr, 0, sel)
 532 #define MIPS32_ISA_MFLO(reg)                    MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
 533 #define MIPS32_ISA_MFHI(reg)                    MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
 534 #define MIPS32_ISA_MTLO(reg)                    MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
 535 #define MIPS32_ISA_MTHI(reg)                    MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
 536
 537 #define MIPS32_ISA_MUL(dst, src, t)             MIPS32_R_INST(28, src, t, dst, 0, MIPS32_OP_MUL)
 538 #define MIPS32_ISA_MOVN(dst, src, tar)          MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)
 539 #define MIPS32_ISA_OR(dst, src, val)            MIPS32_R_INST(0, src, val, dst, 0, 37)
 540 #define MIPS32_ISA_ORI(tar, src, val)           MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
 541 #define MIPS32_ISA_RDHWR(tar, dst)              MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
 542 #define MIPS32_ISA_SB(reg, off, base)           MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 543 #define MIPS32_ISA_SH(reg, off, base)           MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
 544 #define MIPS32_ISA_SW(reg, off, base)           MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
 545
 546 #define MIPS32_ISA_SLL(dst, src, sa)            MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
 547 #define MIPS32_ISA_SLLV(dst, src, sa)           MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLLV)
 548 #define MIPS32_ISA_SLTI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)
 549 #define MIPS32_ISA_SLTU(dst, src, tar)          MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
 550 #define MIPS32_ISA_SRA(reg, src, off)           MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA)
 551 #define MIPS32_ISA_SRL(reg, src, off)           MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRL)
 552 #define MIPS32_ISA_SYNC                         0xFu
 553 #define MIPS32_ISA_SYNCI(off, base)             MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
 554
 555 #define MIPS32_ISA_XOR(reg, val1, val2)         MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
 556 #define MIPS32_ISA_XORI(tar, src, val)          MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
 557
 558 #define MIPS32_ISA_SYNCI_STEP           0x1     /* reg num od address step size to be used with synci instruction */
 559
 560 /**
 561  * Cache operations definitions
 562  * Operation field is 5 bits long :
 563  * 1) bits 1..0 hold cache type
 564  * 2) bits 4..2 hold operation code
 565  */
 566 #define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2))
 567 #define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2))
 568
 569 /* ejtag specific instructions */
 570 #define MIPS32_ISA_DRET                         0x4200001Fu
 571 /* MIPS32_ISA_J_INST(MIPS32_ISA_OP_SPECIAL2, MIPS32_ISA_OP_SDBBP) */
 572 #define MIPS32_ISA_SDBBP                        0x7000003Fu
 573 #define MIPS16_ISA_SDBBP                        0xE801u
 574
 575 /*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
 576 #define MMIPS32_POOL32A                                 0x00u
 577 #define MMIPS32_POOL32F                                 0x15u
 578 #define MMIPS32_POOL32FXF                               0x3Bu
 579 #define MMIPS32_POOL32AXF                               0x3Cu
 580 #define MMIPS32_POOL32B                                 0x08u
 581 #define MMIPS32_POOL32I                                 0x10u
 582 #define MMIPS32_OP_ADDI                 0x04u
 583 #define MMIPS32_OP_ADDIU                0x0Cu
 584 #define MMIPS32_OP_ADDU                 0x150u
 585 #define MMIPS32_OP_AND                  0x250u
 586 #define MMIPS32_OP_ANDI                 0x34u
 587 #define MMIPS32_OP_BEQ                  0x25u
 588 #define MMIPS32_OP_BGTZ                 0x06u
 589 #define MMIPS32_OP_BNE                  0x2Du
 590 #define MMIPS32_OP_CACHE                0x06u
 591 #define MMIPS32_OP_J                    0x35u
 592 #define MMIPS32_OP_JALR                 0x03Cu
 593 #define MMIPS32_OP_JALRHB               0x07Cu
 594 #define MMIPS32_OP_LB                   0x07u
 595 #define MMIPS32_OP_LBU                  0x05u
 596 #define MMIPS32_OP_LHU                  0x0Du
 597 #define MMIPS32_OP_LUI                  0x0Du
 598 #define MMIPS32_OP_LW                   0x3Fu
 599 #define MMIPS32_OP_MFC0                 0x03u
 600 #define MMIPS32_OP_MTC0                 0x0Bu
 601 #define MMIPS32_OP_MFLO                 0x075u
 602 #define MMIPS32_OP_MFHI                 0x035u
 603 #define MMIPS32_OP_MTLO                 0x0F5u
 604 #define MMIPS32_OP_MTHI                 0x0B5u
 605 #define MMIPS32_OP_MOVN                 0x018u
 606 #define MMIPS32_OP_ORI                  0x14u
 607 #define MMIPS32_OP_RDHWR                0x1ACu
 608 #define MMIPS32_OP_SB                   0x06u
 609 #define MMIPS32_OP_SH                   0x0Eu
 610 #define MMIPS32_OP_SW                   0x3Eu
 611 #define MMIPS32_OP_SLTU                 0x390u
 612 #define MMIPS32_OP_SLL                  0x000u
 613 #define MMIPS32_OP_SLTI                 0x24u
 614 #define MMIPS32_OP_SRL                  0x040u
 615 #define MMIPS32_OP_SYNCI                0x10u
 616 #define MMIPS32_OP_XOR                  0x310u
 617 #define MMIPS32_OP_XORI                 0x1Cu
 618
 619 #define MMIPS32_ADDI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)
 620 #define MMIPS32_ADDIU(tar, src, val)            MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)
 621 #define MMIPS32_ADDU(dst, src, tar)             MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
 622 #define MMIPS32_AND(dst, src, tar)              MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
 623 #define MMIPS32_ANDI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)
 624
 625 #define MMIPS32_B(off)                          MMIPS32_BEQ(0, 0, off)
 626 #define MMIPS32_BEQ(src, tar, off)              MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)
 627 #define MMIPS32_BGTZ(reg, off)                  MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_BGTZ, reg, off)
 628 #define MMIPS32_BNE(src, tar, off)              MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
 629 #define MMIPS32_CACHE(op, off, base)            MIPS32_R_INST(MMIPS32_POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
 630
 631 #define MMIPS32_J(tar)                          MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
 632 #define MMIPS32_JR(reg)                         MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALR, MMIPS32_POOL32AXF)
 633 #define MMIPS32_JRHB(reg)                       MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_JALRHB, MMIPS32_POOL32AXF)
 634 #define MMIPS32_LB(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
 635 #define MMIPS32_LBU(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
 636 #define MMIPS32_LHU(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
 637 #define MMIPS32_LUI(reg, val)                   MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_LUI, reg, val)
 638 #define MMIPS32_LW(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
 639
 640 #define MMIPS32_MFC0(gpr, cpr, sel)             MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
 641                                                                                                                 MMIPS32_OP_MFC0, MMIPS32_POOL32AXF)
 642 #define MMIPS32_MFLO(reg)                       MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, MMIPS32_POOL32AXF)
 643 #define MMIPS32_MFHI(reg)                       MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, MMIPS32_POOL32AXF)
 644 #define MMIPS32_MTC0(gpr, cpr, sel)             MIPS32_R_INST(MMIPS32_POOL32A, gpr, cpr, sel,\
 645                                                                                                                 MMIPS32_OP_MTC0, MMIPS32_POOL32AXF)
 646 #define MMIPS32_MTLO(reg)                       MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, MMIPS32_POOL32AXF)
 647 #define MMIPS32_MTHI(reg)                       MIPS32_R_INST(MMIPS32_POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, MMIPS32_POOL32AXF)
 648
 649 #define MMIPS32_MOVN(dst, src, tar)             MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
 650 #define MMIPS32_NOP                             0
 651 #define MMIPS32_ORI(tar, src, val)              MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
 652 #define MMIPS32_RDHWR(tar, dst)                 MIPS32_R_INST(MMIPS32_POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, MMIPS32_POOL32AXF)
 653 #define MMIPS32_SB(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
 654 #define MMIPS32_SH(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
 655 #define MMIPS32_SW(reg, off, base)              MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
 656
 657 #define MMIPS32_SRL(reg, src, off)              MIPS32_R_INST(MMIPS32_POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
 658 #define MMIPS32_SLTU(dst, src, tar)             MIPS32_R_INST(MMIPS32_POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
 659 #define MMIPS32_SYNCI(off, base)                MIPS32_I_INST(MMIPS32_POOL32I, MMIPS32_OP_SYNCI, base, off)
 660 #define MMIPS32_SLL(dst, src, sa)               MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
 661 #define MMIPS32_SLLV(dst, src, sa)              MIPS32_R_INST(MMIPS32_POOL32A, dst, src, sa, 0, MMIPS32_OP_SLLV)
 662 #define MMIPS32_SLTI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
 663 #define MMIPS32_SYNC                            0x00001A7Cu /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1ADu, MMIPS32_POOL32AXF) */
 664
 665 #define MMIPS32_XOR(reg, val1, val2)            MIPS32_R_INST(MMIPS32_POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
 666 #define MMIPS32_XORI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
 667
 668 #define MMIPS32_SYNCI_STEP      0x1u    /* reg num od address step size to be used with synci instruction */
 669
 670
 671 /* ejtag specific instructions */
 672 #define MMIPS32_DRET                    0x0000E37Cu     /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x38D, MMIPS32_POOL32AXF) */
 673 #define MMIPS32_SDBBP                   0x0000DB7Cu     /* MIPS32_R_INST(MMIPS32_POOL32A, 0, 0, 0, 0x1BD, MMIPS32_POOL32AXF) */
 674 #define MMIPS16_SDBBP                   0x46C0u         /* POOL16C instr */
 675
 676 /* instruction code with isa selection */
 677 #define MIPS32_NOP                              0       /* same for both isa's */
 678 #define MIPS32_ADDI(isa, tar, src, val)         (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val))
 679 #define MIPS32_ADDIU(isa, tar, src, val)        (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val))
 680 #define MIPS32_ADDU(isa, dst, src, tar)         (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar))
 681 #define MIPS32_AND(isa, dst, src, tar)          (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar))
 682 #define MIPS32_ANDI(isa, tar, src, val)         (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val))
 683
 684 #define MIPS32_B(isa, off)                      (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off))
 685 #define MIPS32_BEQ(isa, src, tar, off)          (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off))
 686 #define MIPS32_BGTZ(isa, reg, off)              (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))
 687 #define MIPS32_BNE(isa, src, tar, off)          (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))
 688 #define MIPS32_CACHE(isa, op, off, base)        (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))
 689
 690 #define MIPS32_J(isa, tar)                      (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))
 691 #define MIPS32_JR(isa, reg)                     (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))
 692 #define MIPS32_JRHB(isa, reg)           (isa ? MMIPS32_JRHB(reg) : MIPS32_ISA_JRHB(reg))
 693 #define MIPS32_LB(isa, reg, off, base)          (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))
 694 #define MIPS32_LBU(isa, reg, off, base)         (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))
 695 #define MIPS32_LHU(isa, reg, off, base)         (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))
 696 #define MIPS32_LW(isa, reg, off, base)          (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))
 697 #define MIPS32_LUI(isa, reg, val)               (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))
 698
 699 #define MIPS32_MFC0(isa, gpr, cpr, sel)         (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))
 700 #define MIPS32_MTC0(isa, gpr, cpr, sel)         (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))
 701 #define MIPS32_MFLO(isa, reg)                   (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))
 702 #define MIPS32_MFHI(isa, reg)                   (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))
 703 #define MIPS32_MTLO(isa, reg)                   (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))
 704 #define MIPS32_MTHI(isa, reg)                   (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))
 705
 706 #define MIPS32_MUL(isa, dst, src, t)            (MIPS32_ISA_MUL(dst, src, t))
 707 #define MIPS32_MOVN(isa, dst, src, tar)         (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))
 708 #define MIPS32_ORI(isa, tar, src, val)          (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))
 709 #define MIPS32_RDHWR(isa, tar, dst)             (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))
 710 #define MIPS32_SB(isa, reg, off, base)          (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))
 711 #define MIPS32_SH(isa, reg, off, base)          (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))
 712 #define MIPS32_SW(isa, reg, off, base)          (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))
 713
 714 #define MIPS32_SLL(isa, dst, src, sa)           (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))
 715 #define MIPS32_EHB(isa)                         (isa ? MMIPS32_SLL(0, 0, 3) : MIPS32_ISA_SLL(0, 0, 3))
 716 #define MIPS32_SLLV(isa, dst, src, sa)          (MIPS32_ISA_SLLV(dst, src, sa))
 717 #define MIPS32_SLTI(isa, tar, src, val)         (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))
 718 #define MIPS32_SLTU(isa, dst, src, tar)         (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))
 719 #define MIPS32_SRL(isa, reg, src, off)          (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))
 720
 721 #define MIPS32_SYNCI(isa, off, base)            (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base))
 722 #define MIPS32_SYNC(isa)                        (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC)
 723 #define MIPS32_XOR(isa, reg, val1, val2)        (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2))
 724 #define MIPS32_XORI(isa, tar, src, val)         (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val))
 725
 726 #define MIPS32_SYNCI_STEP                       0x1
 727
 728 /* ejtag specific instructions */
 729 #define MIPS32_DRET(isa)                        (isa ? MMIPS32_DRET : MIPS32_ISA_DRET)
 730 #define MIPS32_SDBBP(isa)                       (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP)
 731
 732 #define MIPS16_SDBBP(isa)                       (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
 733
 734 /* ejtag specific instructions */
 735 #define MICRO_MIPS32_SDBBP                      0x000046C0
 736 #define MICRO_MIPS_SDBBP                        0x46C0
 737 /*
 738  * MIPS32 Config1 Register (CP0 Register 16, Select 1)
 739  */
 740 #define MIPS32_CFG1_M                   0x80000000              /* Config2 implemented */
 741 #define MIPS32_CFG1_MMUSMASK            0x7e000000              /* mmu size - 1 */
 742 #define MIPS32_CFG1_MMUSSHIFT           25
 743 #define MIPS32_CFG1_ISMASK              0x01c00000              /* icache lines 64<<n */
 744 #define MIPS32_CFG1_ISSHIFT             22
 745 #define MIPS32_CFG1_ILMASK              0x00380000              /* icache line size 2<<n */
 746 #define MIPS32_CFG1_ILSHIFT             19
 747 #define MIPS32_CFG1_IAMASK              0x00070000              /* icache ways - 1 */
 748 #define MIPS32_CFG1_IASHIFT             16
 749 #define MIPS32_CFG1_DSMASK              0x0000e000              /* dcache lines 64<<n */
 750 #define MIPS32_CFG1_DSSHIFT             13
 751 #define MIPS32_CFG1_DLMASK              0x00001c00              /* dcache line size 2<<n */
 752 #define MIPS32_CFG1_DLSHIFT             10
 753 #define MIPS32_CFG1_DAMASK              0x00000380              /* dcache ways - 1 */
 754 #define MIPS32_CFG1_DASHIFT             7
 755 #define MIPS32_CFG1_C2                  0x00000040              /* Coprocessor 2 present */
 756 #define MIPS32_CFG1_MD                  0x00000020              /* MDMX implemented */
 757 #define MIPS32_CFG1_PC                  0x00000010              /* performance counters implemented */
 758 #define MIPS32_CFG1_WR                  0x00000008              /* watch registers implemented */
 759 #define MIPS32_CFG1_CA                  0x00000004              /* compression (mips16) implemented */
 760 #define MIPS32_CFG1_EP                  0x00000002              /* ejtag implemented */
 761 #define MIPS32_CFG1_FP                  0x00000001              /* fpu implemented */
 762
 763 /*
 764  * MIPS32 Coprocessor 0 register numbers
 765  */
 766 #define MIPS32_C0_INDEX                 0
 767 #define MIPS32_C0_INX                   0
 768 #define MIPS32_C0_RANDOM                1
 769 #define MIPS32_C0_RAND                  1
 770 #define MIPS32_C0_ENTRYLO0              2
 771 #define MIPS32_C0_TLBLO0                2
 772 #define MIPS32_C0_ENTRYLO1              3
 773 #define MIPS32_C0_TLBLO1                3
 774 #define MIPS32_C0_CONTEXT               4
 775 #define MIPS32_C0_CTXT                  4
 776 #define MIPS32_C0_PAGEMASK              5
 777 #define MIPS32_C0_PAGEGRAIN             (5, 1)
 778 #define MIPS32_C0_WIRED                 6
 779 #define MIPS32_C0_HWRENA                7
 780 #define MIPS32_C0_BADVADDR              8
 781 #define MIPS32_C0_VADDR                 8
 782 #define MIPS32_C0_COUNT                 9
 783 #define MIPS32_C0_ENTRYHI               10
 784 #define MIPS32_C0_TLBHI                 10
 785 #define MIPS32_C0_GUESTCTL1             10
 786 #define MIPS32_C0_COMPARE               11
 787 #define MIPS32_C0_STATUS                12
 788 #define MIPS32_C0_SR                    12
 789 #define MIPS32_C0_INTCTL                (12, 1)
 790 #define MIPS32_C0_SRSCTL                (12, 2)
 791 #define MIPS32_C0_SRSMAP                (12, 3)
 792 #define MIPS32_C0_CAUSE                 13
 793 #define MIPS32_C0_CR                    13
 794 #define MIPS32_C0_EPC                   14
 795 #define MIPS32_C0_PRID                  15
 796 #define MIPS32_C0_EBASE                 (15, 1)
 797 #define MIPS32_C0_CONFIG                16
 798 #define MIPS32_C0_CONFIG0               (16, 0)
 799 #define MIPS32_C0_CONFIG1               (16, 1)
 800 #define MIPS32_C0_CONFIG2               (16, 2)
 801 #define MIPS32_C0_CONFIG3               (16, 3)
 802 #define MIPS32_C0_LLADDR                17
 803 #define MIPS32_C0_WATCHLO               18
 804 #define MIPS32_C0_WATCHHI               19
 805 #define MIPS32_C0_DEBUG                 23
 806 #define MIPS32_C0_DEPC                  24
 807 #define MIPS32_C0_PERFCNT               25
 808 #define MIPS32_C0_ERRCTL                26
 809 #define MIPS32_C0_CACHEERR              27
 810 #define MIPS32_C0_TAGLO                 28
 811 #define MIPS32_C0_ITAGLO                28
 812 #define MIPS32_C0_DTAGLO                (28, 2)
 813 #define MIPS32_C0_TAGLO2                (28, 4)
 814 #define MIPS32_C0_DATALO                (28, 1)
 815 #define MIPS32_C0_IDATALO               (28, 1)
 816 #define MIPS32_C0_DDATALO               (28, 3)
 817 #define MIPS32_C0_DATALO2               (28, 5)
 818 #define MIPS32_C0_TAGHI                 29
 819 #define MIPS32_C0_ITAGHI                29
 820 #define MIPS32_C0_DATAHI                (29, 1)
 821 #define MIPS32_C0_ERRPC                 30
 822 #define MIPS32_C0_DESAVE                31
 823
 824 /*
 825  * MIPS32 MMU types
 826  */
 827 #define MIPS32_MMU_TLB                  1
 828 #define MIPS32_MMU_BAT                  2
 829 #define MIPS32_MMU_FIXED                3
 830 #define MIPS32_MMU_DUAL_VTLB_FTLB       4
 831
 832 extern const struct command_registration mips32_command_handlers[];
 833
 834 int mips32_arch_state(struct target *target);
 835
 836 int mips32_init_arch_info(struct target *target,
 837                 struct mips32_common *mips32, struct jtag_tap *tap);
 838
 839 int mips32_restore_context(struct target *target);
 840 int mips32_save_context(struct target *target);
 841
 842 struct reg_cache *mips32_build_reg_cache(struct target *target);
 843
 844 int mips32_run_algorithm(struct target *target,
 845                 int num_mem_params, struct mem_param *mem_params,
 846                 int num_reg_params, struct reg_param *reg_params,
 847                 target_addr_t entry_point, target_addr_t exit_point,
 848                 unsigned int timeout_ms, void *arch_info);
 849
 850 int mips32_configure_break_unit(struct target *target);
 851
 852 int mips32_enable_interrupts(struct target *target, int enable);
 853
 854 int mips32_examine(struct target *target);
 855
 856 int mips32_cpu_probe(struct target *target);
 857
 858 int mips32_read_config_regs(struct target *target);
 859
 860 int mips32_register_commands(struct command_context *cmd_ctx);
 861
 862 int mips32_get_gdb_reg_list(struct target *target,
 863                 struct reg **reg_list[], int *reg_list_size,
 864                 enum target_register_class reg_class);
 865 int mips32_checksum_memory(struct target *target, target_addr_t address,
 866                 uint32_t count, uint32_t *checksum);
 867 int mips32_blank_check_memory(struct target *target,
 868                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 869
 870 bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info);
 871 bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info);
 872
 873 #endif /* OPENOCD_TARGET_MIPS32_H */