1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the *
24 * Free Software Foundation, Inc., *
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
26 ***************************************************************************/
29 * This version has optimized assembly routines for 32 bit operations:
32 * - write array of words
34 * One thing to be aware of is that the MIPS32 cpu will execute the
35 * instruction after a branch instruction (one delay slot).
42 * The LW $1, ($2 +100) instruction is also executed. If this is
43 * not wanted a NOP can be inserted:
50 * or the code can be changed to:
56 * The original code contained NOPs. I have removed these and moved
59 * I also moved the PRACC_STACK to 0xFF204000. This allows
60 * the use of 16 bits offsets to get pointers to the input
61 * and output area relative to the stack. Note that the stack
62 * isn't really a stack (the stack pointer is not 'moving')
63 * but a FIFO simulated in software.
65 * These changes result in a 35% speed increase when programming an
68 * More improvement could be gained if the registers do no need
69 * to be preserved but in that case the routines should be aware
70 * OpenOCD is used as a flash programmer or as a debug tool.
79 #include <helper/time_support.h>
82 #include "mips32_pracc.h"
84 struct mips32_pracc_context
{
85 uint32_t *local_iparam
;
87 uint32_t *local_oparam
;
93 struct mips_ejtag
*ejtag_info
;
96 static int mips32_pracc_sync_cache(struct mips_ejtag
*ejtag_info
,
97 uint32_t start_addr
, uint32_t end_addr
);
98 static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag
*ejtag_info
,
99 uint32_t start_addr
, uint32_t end_addr
);
101 static int wait_for_pracc_rw(struct mips_ejtag
*ejtag_info
, uint32_t *ctrl
)
104 long long then
= timeval_ms();
108 /* wait for the PrAcc to become "1" */
109 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
112 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
113 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
114 if (retval
!= ERROR_OK
)
117 if (ejtag_ctrl
& EJTAG_CTRL_PRACC
)
120 timeout
= timeval_ms() - then
;
121 if (timeout
> 1000) {
122 LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
123 return ERROR_JTAG_DEVICE_ERROR
;
131 static int mips32_pracc_exec_read(struct mips32_pracc_context
*ctx
, uint32_t address
)
133 struct mips_ejtag
*ejtag_info
= ctx
->ejtag_info
;
135 uint32_t ejtag_ctrl
, data
;
137 if ((address
>= MIPS32_PRACC_PARAM_IN
)
138 && (address
< MIPS32_PRACC_PARAM_IN
+ ctx
->num_iparam
* 4)) {
139 offset
= (address
- MIPS32_PRACC_PARAM_IN
) / 4;
140 data
= ctx
->local_iparam
[offset
];
141 } else if ((address
>= MIPS32_PRACC_PARAM_OUT
)
142 && (address
< MIPS32_PRACC_PARAM_OUT
+ ctx
->num_oparam
* 4)) {
143 offset
= (address
- MIPS32_PRACC_PARAM_OUT
) / 4;
144 data
= ctx
->local_oparam
[offset
];
145 } else if ((address
>= MIPS32_PRACC_TEXT
)
146 && (address
< MIPS32_PRACC_TEXT
+ ctx
->code_len
* 4)) {
147 offset
= (address
- MIPS32_PRACC_TEXT
) / 4;
148 data
= ctx
->code
[offset
];
149 } else if (address
== MIPS32_PRACC_STACK
) {
150 if (ctx
->stack_offset
<= 0) {
151 LOG_ERROR("Error: Pracc stack out of bounds");
152 return ERROR_JTAG_DEVICE_ERROR
;
154 /* save to our debug stack */
155 data
= ctx
->stack
[--ctx
->stack_offset
];
156 } else if (address
>= 0xFF200000) {
157 /* CPU keeps reading at the end of execution.
158 * If we after 0xF0000000 address range, we can use
159 * one shot jump instruction.
160 * Since this instruction is limited to
161 * 26bit, we need to do some magic to fit it to our needs. */
162 LOG_DEBUG("Reading unexpected address. Jump to 0xFF200200\n");
163 data
= MIPS32_J((0x0FFFFFFF & 0xFF200200) >> 2);
165 LOG_ERROR("Error reading unexpected address 0x%8.8" PRIx32
"", address
);
166 return ERROR_JTAG_DEVICE_ERROR
;
169 /* Send the data out */
170 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_DATA
);
171 mips_ejtag_drscan_32_out(ctx
->ejtag_info
, data
);
173 /* Clear the access pending bit (let the processor eat!) */
174 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
175 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_CONTROL
);
176 mips_ejtag_drscan_32_out(ctx
->ejtag_info
, ejtag_ctrl
);
178 return jtag_execute_queue();
181 static int mips32_pracc_exec_write(struct mips32_pracc_context
*ctx
, uint32_t address
)
183 uint32_t ejtag_ctrl
, data
;
185 struct mips_ejtag
*ejtag_info
= ctx
->ejtag_info
;
188 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_DATA
);
189 retval
= mips_ejtag_drscan_32(ctx
->ejtag_info
, &data
);
190 if (retval
!= ERROR_OK
)
193 /* Clear access pending bit */
194 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
195 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_CONTROL
);
196 mips_ejtag_drscan_32_out(ctx
->ejtag_info
, ejtag_ctrl
);
198 retval
= jtag_execute_queue();
199 if (retval
!= ERROR_OK
)
202 if ((address
>= MIPS32_PRACC_PARAM_OUT
)
203 && (address
< MIPS32_PRACC_PARAM_OUT
+ ctx
->num_oparam
* 4)) {
204 offset
= (address
- MIPS32_PRACC_PARAM_OUT
) / 4;
205 ctx
->local_oparam
[offset
] = data
;
206 } else if (address
== MIPS32_PRACC_STACK
) {
207 if (ctx
->stack_offset
>= 32) {
208 LOG_ERROR("Error: Pracc stack out of bounds");
209 return ERROR_JTAG_DEVICE_ERROR
;
211 /* save data onto our stack */
212 ctx
->stack
[ctx
->stack_offset
++] = data
;
214 LOG_ERROR("Error writing unexpected address 0x%8.8" PRIx32
"", address
);
215 return ERROR_JTAG_DEVICE_ERROR
;
221 int mips32_pracc_exec(struct mips_ejtag
*ejtag_info
, int code_len
, const uint32_t *code
,
222 int num_param_in
, uint32_t *param_in
, int num_param_out
, uint32_t *param_out
, int cycle
)
226 struct mips32_pracc_context ctx
;
230 ctx
.local_iparam
= param_in
;
231 ctx
.local_oparam
= param_out
;
232 ctx
.num_iparam
= num_param_in
;
233 ctx
.num_oparam
= num_param_out
;
235 ctx
.code_len
= code_len
;
236 ctx
.ejtag_info
= ejtag_info
;
237 ctx
.stack_offset
= 0;
240 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
241 if (retval
!= ERROR_OK
)
245 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
246 retval
= mips_ejtag_drscan_32(ejtag_info
, &address
);
247 if (retval
!= ERROR_OK
)
250 /* Check for read or write */
251 if (ejtag_ctrl
& EJTAG_CTRL_PRNW
) {
252 retval
= mips32_pracc_exec_write(&ctx
, address
);
253 if (retval
!= ERROR_OK
)
256 /* Check to see if its reading at the debug vector. The first pass through
257 * the module is always read at the vector, so the first one we allow. When
258 * the second read from the vector occurs we are done and just exit. */
259 if ((address
== MIPS32_PRACC_TEXT
) && (pass
++))
262 retval
= mips32_pracc_exec_read(&ctx
, address
);
263 if (retval
!= ERROR_OK
)
271 /* stack sanity check */
272 if (ctx
.stack_offset
!= 0)
273 LOG_DEBUG("Pracc Stack not zero");
278 inline void pracc_queue_init(struct pracc_queue_info
*ctx
)
280 ctx
->retval
= ERROR_OK
;
282 ctx
->store_count
= 0;
284 ctx
->pracc_list
= malloc(2 * ctx
->max_code
* sizeof(uint32_t));
285 if (ctx
->pracc_list
== NULL
) {
286 LOG_ERROR("Out of memory");
287 ctx
->retval
= ERROR_FAIL
;
291 inline void pracc_add(struct pracc_queue_info
*ctx
, uint32_t addr
, uint32_t instr
)
293 ctx
->pracc_list
[ctx
->max_code
+ ctx
->code_count
] = addr
;
294 ctx
->pracc_list
[ctx
->code_count
++] = instr
;
299 inline void pracc_queue_free(struct pracc_queue_info
*ctx
)
301 if (ctx
->code_count
> ctx
->max_code
) /* Only for internal check, will be erased */
302 LOG_ERROR("Internal error, code count: %d > max code: %d", ctx
->code_count
, ctx
->max_code
);
303 if (ctx
->pracc_list
!= NULL
)
304 free(ctx
->pracc_list
);
307 int mips32_pracc_queue_exec(struct mips_ejtag
*ejtag_info
, struct pracc_queue_info
*ctx
, uint32_t *buf
)
309 if (ejtag_info
->mode
== 0)
310 return mips32_pracc_exec(ejtag_info
, ctx
->code_count
, ctx
->pracc_list
, 0, NULL
,
311 ctx
->store_count
, buf
, ctx
->code_count
- 1);
321 } *scan_in
= malloc(sizeof(union scan_in
) * (ctx
->code_count
+ ctx
->store_count
));
322 if (scan_in
== NULL
) {
323 LOG_ERROR("Out of memory");
327 unsigned num_clocks
=
328 ((uint64_t)(ejtag_info
->scan_delay
) * jtag_get_speed_khz() + 500000) / 1000000;
330 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
331 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ALL
);
334 for (int i
= 0; i
!= 2 * ctx
->code_count
; i
++) {
336 if (i
& 1u) { /* Check store address from previous instruction, if not the first */
337 if (i
< 2 || 0 == ctx
->pracc_list
[ctx
->max_code
+ (i
/ 2) - 1])
340 data
= ctx
->pracc_list
[i
/ 2];
342 jtag_add_clocks(num_clocks
);
343 mips_ejtag_add_scan_96(ejtag_info
, ejtag_ctrl
, data
, scan_in
[scan_count
++].scan_96
);
346 int retval
= jtag_execute_queue(); /* execute queued scans */
347 if (retval
!= ERROR_OK
)
350 uint32_t fetch_addr
= MIPS32_PRACC_TEXT
; /* start address */
352 for (int i
= 0; i
!= 2 * ctx
->code_count
; i
++) { /* verify every pracc access */
353 uint32_t store_addr
= 0;
354 if (i
& 1u) { /* Read store addres from previous instruction, if not the first */
355 store_addr
= ctx
->pracc_list
[ctx
->max_code
+ (i
/ 2) - 1];
356 if (i
< 2 || 0 == store_addr
)
360 ejtag_ctrl
= buf_get_u32(scan_in
[scan_count
].scan_32
.ctrl
, 0, 32);
361 if (!(ejtag_ctrl
& EJTAG_CTRL_PRACC
)) {
362 LOG_ERROR("Error: access not pending count: %d", scan_count
);
367 uint32_t addr
= buf_get_u32(scan_in
[scan_count
].scan_32
.addr
, 0, 32);
369 if (store_addr
!= 0) {
370 if (!(ejtag_ctrl
& EJTAG_CTRL_PRNW
)) {
371 LOG_ERROR("Not a store/write access, count: %d", scan_count
);
375 if (addr
!= store_addr
) {
376 LOG_ERROR("Store address mismatch, read: %" PRIx32
" expected: %" PRIx32
" count: %d",
377 addr
, store_addr
, scan_count
);
381 int buf_index
= (addr
- MIPS32_PRACC_PARAM_OUT
) / 4;
382 buf
[buf_index
] = buf_get_u32(scan_in
[scan_count
].scan_32
.data
, 0, 32);
385 if (ejtag_ctrl
& EJTAG_CTRL_PRNW
) {
386 LOG_ERROR("Not a fetch/read access, count: %d", scan_count
);
390 if (addr
!= fetch_addr
) {
391 LOG_ERROR("Fetch addr mismatch, read: %" PRIx32
" expected: %" PRIx32
" count: %d",
392 addr
, fetch_addr
, scan_count
);
405 int mips32_pracc_read_u32(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint32_t *buf
)
407 struct pracc_queue_info ctx
= {.max_code
= 9};
408 pracc_queue_init(&ctx
);
409 if (ctx
.retval
!= ERROR_OK
)
412 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */
413 pracc_add(&ctx
, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR
)); /* $15 = MIPS32_PRACC_BASE_ADDR */
414 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16((addr
+ 0x8000)))); /* load $8 with modified upper address */
415 pracc_add(&ctx
, 0, MIPS32_LW(8, LOWER16(addr
), 8)); /* lw $8, LOWER16(addr)($8) */
416 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
,
417 MIPS32_SW(8, PRACC_OUT_OFFSET
, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */
418 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 of $8 */
419 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 of $8 */
420 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
421 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
423 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, buf
);
425 pracc_queue_free(&ctx
);
429 int mips32_pracc_read_mem(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int size
, int count
, void *buf
)
431 if (count
== 1 && size
== 4)
432 return mips32_pracc_read_u32(ejtag_info
, addr
, (uint32_t *)buf
);
434 uint32_t *data
= NULL
;
435 struct pracc_queue_info ctx
= {.max_code
= 256 * 3 + 9 + 1}; /* alloc memory for the worst case */
436 pracc_queue_init(&ctx
);
437 if (ctx
.retval
!= ERROR_OK
)
441 data
= malloc(256 * sizeof(uint32_t));
443 LOG_ERROR("Out of memory");
448 uint32_t *buf32
= buf
;
449 uint16_t *buf16
= buf
;
455 int this_round_count
= (count
> 256) ? 256 : count
;
456 uint32_t last_upper_base_addr
= UPPER16((addr
+ 0x8000));
458 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 31, 0)); /* save $15 in DeSave */
459 pracc_add(&ctx
, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR
)); /* $15 = MIPS32_PRACC_BASE_ADDR */
460 pracc_add(&ctx
, 0, MIPS32_LUI(9, last_upper_base_addr
)); /* load the upper memory address in $9 */
462 for (int i
= 0; i
!= this_round_count
; i
++) { /* Main code loop */
463 uint32_t upper_base_addr
= UPPER16((addr
+ 0x8000));
464 if (last_upper_base_addr
!= upper_base_addr
) { /* if needed, change upper address in $9 */
465 pracc_add(&ctx
, 0, MIPS32_LUI(9, upper_base_addr
));
466 last_upper_base_addr
= upper_base_addr
;
470 pracc_add(&ctx
, 0, MIPS32_LW(8, LOWER16(addr
), 9)); /* load from memory to $8 */
472 pracc_add(&ctx
, 0, MIPS32_LHU(8, LOWER16(addr
), 9));
474 pracc_add(&ctx
, 0, MIPS32_LBU(8, LOWER16(addr
), 9));
476 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ i
* 4,
477 MIPS32_SW(8, PRACC_OUT_OFFSET
+ i
* 4, 15)); /* store $8 at param out */
480 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of reg 8 */
481 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of reg 8 */
482 pracc_add(&ctx
, 0, MIPS32_LUI(9, UPPER16(ejtag_info
->reg9
))); /* restore upper 16 bits of reg 9 */
483 pracc_add(&ctx
, 0, MIPS32_ORI(9, 9, LOWER16(ejtag_info
->reg9
))); /* restore lower 16 bits of reg 9 */
485 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
486 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
489 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, buf32
);
490 if (ctx
.retval
!= ERROR_OK
)
492 buf32
+= this_round_count
;
494 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, data
);
495 if (ctx
.retval
!= ERROR_OK
)
498 uint32_t *data_p
= data
;
499 for (int i
= 0; i
!= this_round_count
; i
++) {
501 *buf16
++ = *data_p
++;
506 count
-= this_round_count
;
509 pracc_queue_free(&ctx
);
515 int mips32_cp0_read(struct mips_ejtag
*ejtag_info
, uint32_t *val
, uint32_t cp0_reg
, uint32_t cp0_sel
)
517 struct pracc_queue_info ctx
= {.max_code
= 8};
518 pracc_queue_init(&ctx
);
519 if (ctx
.retval
!= ERROR_OK
)
522 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */
523 pracc_add(&ctx
, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR
)); /* $15 = MIPS32_PRACC_BASE_ADDR */
524 pracc_add(&ctx
, 0, MIPS32_MFC0(8, 0, 0) | (cp0_reg
<< 11) | cp0_sel
); /* move COP0 [cp0_reg select] to $8 */
525 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
,
526 MIPS32_SW(8, PRACC_OUT_OFFSET
, 15)); /* store $8 to pracc_out */
527 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
528 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of $8 */
529 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
530 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of $8 */
532 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, val
);
534 pracc_queue_free(&ctx
);
538 * Note that our input parametes cp0_reg and cp0_sel
539 * are numbers (not gprs) which make part of mfc0 instruction opcode.
541 * These are not fix, but can be different for each mips32_cp0_read() function call,
542 * and that is why we must insert them directly into opcode,
543 * i.e. we can not pass it on EJTAG microprogram stack (via param_in),
544 * and put them into the gprs later from MIPS32_PRACC_STACK
545 * because mfc0 do not use gpr as a parameter for the cp0_reg and select part,
546 * but plain (immediate) number.
548 * MIPS32_MTC0 is implemented via MIPS32_R_INST macro.
549 * In order to insert our parameters, we must change rd and funct fields.
551 * code[2] |= (cp0_reg << 11) | cp0_sel; change rd and funct of MIPS32_R_INST macro
555 int mips32_cp0_write(struct mips_ejtag
*ejtag_info
, uint32_t val
, uint32_t cp0_reg
, uint32_t cp0_sel
)
557 struct pracc_queue_info ctx
= {.max_code
= 6};
558 pracc_queue_init(&ctx
);
559 if (ctx
.retval
!= ERROR_OK
)
562 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 31, 0)); /* move $15 to COP0 DeSave */
563 pracc_add(&ctx
, 0, MIPS32_LUI(15, UPPER16(val
))); /* Load val to $15 */
564 pracc_add(&ctx
, 0, MIPS32_ORI(15, 15, LOWER16(val
)));
566 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 0, 0) | (cp0_reg
<< 11) | cp0_sel
); /* write cp0 reg / sel */
568 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
569 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
571 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
573 pracc_queue_free(&ctx
);
577 * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro.
578 * In order to insert our parameters, we must change rd and funct fields.
579 * code[3] |= (cp0_reg << 11) | cp0_sel; change rd and funct fields of MIPS32_R_INST macro
584 * \b mips32_pracc_sync_cache
586 * Synchronize Caches to Make Instruction Writes Effective
587 * (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set,
588 * Document Number: MD00086, Revision 2.00, June 9, 2003)
590 * When the instruction stream is written, the SYNCI instruction should be used
591 * in conjunction with other instructions to make the newly-written instructions effective.
594 * A program that loads another program into memory is actually writing the D- side cache.
595 * The instructions it has loaded can't be executed until they reach the I-cache.
597 * After the instructions have been written, the loader should arrange
598 * to write back any containing D-cache line and invalidate any locations
599 * already in the I-cache.
601 * You can do that with cache instructions, but those instructions are only available in kernel mode,
602 * and a loader writing instructions for the use of its own process need not be privileged software.
604 * In the latest MIPS32/64 CPUs, MIPS provides the synci instruction,
605 * which does the whole job for a cache-line-sized chunk of the memory you just loaded:
606 * That is, it arranges a D-cache write-back and an I-cache invalidate.
608 * To employ synci at user level, you need to know the size of a cache line,
609 * and that can be obtained with a rdhwr SYNCI_Step
610 * from one of the standard “hardware registers”.
612 static int mips32_pracc_sync_cache(struct mips_ejtag
*ejtag_info
,
613 uint32_t start_addr
, uint32_t end_addr
)
615 static const uint32_t code
[] = {
617 MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
618 MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK
)), /* $15 = MIPS32_PRACC_STACK */
619 MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK
)),
620 MIPS32_SW(8, 0, 15), /* sw $8,($15) */
621 MIPS32_SW(9, 0, 15), /* sw $9,($15) */
622 MIPS32_SW(10, 0, 15), /* sw $10,($15) */
623 MIPS32_SW(11, 0, 15), /* sw $11,($15) */
625 MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN
)), /* $8 = MIPS32_PRACC_PARAM_IN */
626 MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN
)),
627 MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
628 MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
630 MIPS32_RDHWR(11, MIPS32_SYNCI_STEP
), /* $11 = MIPS32_SYNCI_STEP */
631 MIPS32_BEQ(11, 0, 6), /* beq $11, $0, end */
634 MIPS32_SYNCI(0, 9), /* synci 0($9) */
635 MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */
636 MIPS32_BNE(8, 0, NEG16(3)), /* bne $8, $0, synci_loop */
637 MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */
640 MIPS32_LW(11, 0, 15), /* lw $11,($15) */
641 MIPS32_LW(10, 0, 15), /* lw $10,($15) */
642 MIPS32_LW(9, 0, 15), /* lw $9,($15) */
643 MIPS32_LW(8, 0, 15), /* lw $8,($15) */
644 MIPS32_B(NEG16(24)), /* b start */
645 MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
648 /* TODO remove array */
649 uint32_t *param_in
= malloc(2 * sizeof(uint32_t));
651 param_in
[0] = start_addr
;
652 param_in
[1] = end_addr
;
654 retval
= mips32_pracc_exec(ejtag_info
, ARRAY_SIZE(code
), code
, 2, param_in
, 0, NULL
, 1);
662 * \b mips32_pracc_clean_invalidate_cache
664 * Writeback D$ and Invalidate I$
665 * so that the instructions written can be visible to CPU
667 static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag
*ejtag_info
,
668 uint32_t start_addr
, uint32_t end_addr
)
670 static const uint32_t code
[] = {
672 MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
673 MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK
)), /* $15 = MIPS32_PRACC_STACK */
674 MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK
)),
675 MIPS32_SW(8, 0, 15), /* sw $8,($15) */
676 MIPS32_SW(9, 0, 15), /* sw $9,($15) */
677 MIPS32_SW(10, 0, 15), /* sw $10,($15) */
678 MIPS32_SW(11, 0, 15), /* sw $11,($15) */
680 MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN
)), /* $8 = MIPS32_PRACC_PARAM_IN */
681 MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN
)),
682 MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
683 MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
684 MIPS32_LW(11, 8, 8), /* Load write clsiz to $11 */
687 MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */
688 MIPS32_BGTZ(8, 6), /* bgtz $8, end */
691 MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK
, 0, 9), /* cache Hit_Writeback_D, 0($9) */
692 MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE
, 0, 9), /* cache Hit_Invalidate_I, 0($9) */
694 MIPS32_ADDU(9, 9, 11), /* $9 += $11 */
696 MIPS32_B(NEG16(7)), /* b cache_loop */
699 MIPS32_LW(11, 0, 15), /* lw $11,($15) */
700 MIPS32_LW(10, 0, 15), /* lw $10,($15) */
701 MIPS32_LW(9, 0, 15), /* lw $9,($15) */
702 MIPS32_LW(8, 0, 15), /* lw $8,($15) */
703 MIPS32_B(NEG16(25)), /* b start */
704 MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
708 * Find cache line size in bytes
713 mips32_cp0_read(ejtag_info
, &conf
, 16, 1);
714 dl
= (conf
& MIPS32_CONFIG1_DL_MASK
) >> MIPS32_CONFIG1_DL_SHIFT
;
716 /* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... */
719 /* TODO remove array */
720 uint32_t *param_in
= malloc(3 * sizeof(uint32_t));
722 param_in
[0] = start_addr
;
723 param_in
[1] = end_addr
;
726 retval
= mips32_pracc_exec(ejtag_info
, ARRAY_SIZE(code
), code
, 3, param_in
, 0, NULL
, 1);
733 static int mips32_pracc_write_mem_generic(struct mips_ejtag
*ejtag_info
,
734 uint32_t addr
, int size
, int count
, const void *buf
)
736 struct pracc_queue_info ctx
= {.max_code
= 128 * 3 + 6 + 1}; /* alloc memory for the worst case */
737 pracc_queue_init(&ctx
);
738 if (ctx
.retval
!= ERROR_OK
)
741 const uint32_t *buf32
= buf
;
742 const uint16_t *buf16
= buf
;
743 const uint8_t *buf8
= buf
;
748 int this_round_count
= (count
> 128) ? 128 : count
;
749 uint32_t last_upper_base_addr
= UPPER16((addr
+ 0x8000));
751 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 31, 0)); /* save $15 in DeSave */
752 pracc_add(&ctx
, 0, MIPS32_LUI(15, last_upper_base_addr
)); /* load $15 with memory base address */
754 for (int i
= 0; i
!= this_round_count
; i
++) {
755 uint32_t upper_base_addr
= UPPER16((addr
+ 0x8000));
756 if (last_upper_base_addr
!= upper_base_addr
) {
757 pracc_add(&ctx
, 0, MIPS32_LUI(15, upper_base_addr
)); /* if needed, change upper address in $15*/
758 last_upper_base_addr
= upper_base_addr
;
761 if (size
== 4) { /* for word writes check if one half word is 0 and load it accordingly */
762 if (LOWER16(*buf32
) == 0)
763 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(*buf32
))); /* load only upper value */
764 else if (UPPER16(*buf32
) == 0)
765 pracc_add(&ctx
, 0, MIPS32_ORI(8, 0, LOWER16(*buf32
))); /* load only lower */
767 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(*buf32
))); /* load upper and lower */
768 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(*buf32
)));
770 pracc_add(&ctx
, 0, MIPS32_SW(8, LOWER16(addr
), 15)); /* store word to memory */
773 } else if (size
== 2) {
774 pracc_add(&ctx
, 0, MIPS32_ORI(8, 0, *buf16
)); /* load lower value */
775 pracc_add(&ctx
, 0, MIPS32_SH(8, LOWER16(addr
), 15)); /* store half word to memory */
779 pracc_add(&ctx
, 0, MIPS32_ORI(8, 0, *buf8
)); /* load lower value */
780 pracc_add(&ctx
, 0, MIPS32_SB(8, LOWER16(addr
), 15)); /* store byte to memory */
786 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of reg 8 */
787 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of reg 8 */
789 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
790 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
792 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
793 if (ctx
.retval
!= ERROR_OK
)
795 count
-= this_round_count
;
798 pracc_queue_free(&ctx
);
802 int mips32_pracc_write_mem(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int size
, int count
, const void *buf
)
804 int retval
= mips32_pracc_write_mem_generic(ejtag_info
, addr
, size
, count
, buf
);
805 if (retval
!= ERROR_OK
)
809 * If we are in the cachable regoion and cache is activated,
810 * we must clean D$ + invalidate I$ after we did the write,
811 * so that changes do not continue to live only in D$, but to be
812 * replicated in I$ also (maybe we wrote the istructions)
817 if ((KSEGX(addr
) == KSEG1
) || ((addr
>= 0xff200000) && (addr
<= 0xff3fffff)))
818 return retval
; /*Nothing to do*/
820 mips32_cp0_read(ejtag_info
, &conf
, 16, 0);
822 switch (KSEGX(addr
)) {
824 cached
= (conf
& MIPS32_CONFIG0_KU_MASK
) >> MIPS32_CONFIG0_KU_SHIFT
;
827 cached
= (conf
& MIPS32_CONFIG0_K0_MASK
) >> MIPS32_CONFIG0_K0_SHIFT
;
831 cached
= (conf
& MIPS32_CONFIG0_K23_MASK
) >> MIPS32_CONFIG0_K23_SHIFT
;
839 * Check cachablitiy bits coherency algorithm -
840 * is the region cacheable or uncached.
841 * If cacheable we have to synchronize the cache
844 uint32_t start_addr
, end_addr
;
848 end_addr
= addr
+ count
* size
;
850 /** select cache synchronisation mechanism based on Architecture Release */
851 rel
= (conf
& MIPS32_CONFIG0_AR_MASK
) >> MIPS32_CONFIG0_AR_SHIFT
;
853 case MIPS32_ARCH_REL1
:
854 /* MIPS32/64 Release 1 - we must use cache instruction */
855 mips32_pracc_clean_invalidate_cache(ejtag_info
, start_addr
, end_addr
);
857 case MIPS32_ARCH_REL2
:
858 /* MIPS32/64 Release 2 - we can use synci instruction */
859 mips32_pracc_sync_cache(ejtag_info
, start_addr
, end_addr
);
870 int mips32_pracc_write_regs(struct mips_ejtag
*ejtag_info
, uint32_t *regs
)
872 static const uint32_t cp0_write_code
[] = {
873 MIPS32_MTC0(1, 12, 0), /* move $1 to status */
874 MIPS32_MTLO(1), /* move $1 to lo */
875 MIPS32_MTHI(1), /* move $1 to hi */
876 MIPS32_MTC0(1, 8, 0), /* move $1 to badvaddr */
877 MIPS32_MTC0(1, 13, 0), /* move $1 to cause*/
878 MIPS32_MTC0(1, 24, 0), /* move $1 to depc (pc) */
881 struct pracc_queue_info ctx
= {.max_code
= 37 * 2 + 6 + 1};
882 pracc_queue_init(&ctx
);
883 if (ctx
.retval
!= ERROR_OK
)
886 /* load registers 2 to 31 with lui and ori instructions, check if some instructions can be saved */
887 for (int i
= 2; i
< 32; i
++) {
888 if (LOWER16((regs
[i
])) == 0) /* if lower half word is 0, lui instruction only */
889 pracc_add(&ctx
, 0, MIPS32_LUI(i
, UPPER16((regs
[i
]))));
890 else if (UPPER16((regs
[i
])) == 0) /* if upper half word is 0, ori with $0 only*/
891 pracc_add(&ctx
, 0, MIPS32_ORI(i
, 0, LOWER16((regs
[i
]))));
892 else { /* default, load with lui and ori instructions */
893 pracc_add(&ctx
, 0, MIPS32_LUI(i
, UPPER16((regs
[i
]))));
894 pracc_add(&ctx
, 0, MIPS32_ORI(i
, i
, LOWER16((regs
[i
]))));
898 for (int i
= 0; i
!= 6; i
++) {
899 pracc_add(&ctx
, 0, MIPS32_LUI(1, UPPER16((regs
[i
+ 32])))); /* load CPO value in $1, with lui and ori */
900 pracc_add(&ctx
, 0, MIPS32_ORI(1, 1, LOWER16((regs
[i
+ 32]))));
901 pracc_add(&ctx
, 0, cp0_write_code
[i
]); /* write value from $1 to CPO register */
904 pracc_add(&ctx
, 0, MIPS32_LUI(1, UPPER16((regs
[1])))); /* load upper half word in $1 */
905 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
906 pracc_add(&ctx
, 0, MIPS32_ORI(1, 1, LOWER16((regs
[1])))); /* load lower half word in $1 */
908 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
910 ejtag_info
->reg8
= regs
[8];
911 ejtag_info
->reg9
= regs
[9];
913 pracc_queue_free(&ctx
);
917 int mips32_pracc_read_regs(struct mips_ejtag
*ejtag_info
, uint32_t *regs
)
919 static int cp0_read_code
[] = {
920 MIPS32_MFC0(8, 12, 0), /* move status to $8 */
921 MIPS32_MFLO(8), /* move lo to $8 */
922 MIPS32_MFHI(8), /* move hi to $8 */
923 MIPS32_MFC0(8, 8, 0), /* move badvaddr to $8 */
924 MIPS32_MFC0(8, 13, 0), /* move cause to $8 */
925 MIPS32_MFC0(8, 24, 0), /* move depc (pc) to $8 */
928 struct pracc_queue_info ctx
= {.max_code
= 48};
929 pracc_queue_init(&ctx
);
930 if (ctx
.retval
!= ERROR_OK
)
933 pracc_add(&ctx
, 0, MIPS32_MTC0(1, 31, 0)); /* move $1 to COP0 DeSave */
934 pracc_add(&ctx
, 0, MIPS32_LUI(1, PRACC_UPPER_BASE_ADDR
)); /* $1 = MIP32_PRACC_BASE_ADDR */
936 for (int i
= 2; i
!= 32; i
++) /* store GPR's 2 to 31 */
937 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ (i
* 4),
938 MIPS32_SW(i
, PRACC_OUT_OFFSET
+ (i
* 4), 1));
940 for (int i
= 0; i
!= 6; i
++) {
941 pracc_add(&ctx
, 0, cp0_read_code
[i
]); /* load COP0 needed registers to $8 */
942 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ (i
+ 32) * 4, /* store $8 at PARAM OUT */
943 MIPS32_SW(8, PRACC_OUT_OFFSET
+ (i
+ 32) * 4, 1));
945 pracc_add(&ctx
, 0, MIPS32_MFC0(8, 31, 0)); /* move DeSave to $8, reg1 value */
946 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ 4, /* store reg1 value from $8 to param out */
947 MIPS32_SW(8, PRACC_OUT_OFFSET
+ 4, 1));
949 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
950 pracc_add(&ctx
, 0, MIPS32_MFC0(1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */
952 if (ejtag_info
->mode
== 0)
953 ctx
.store_count
++; /* Needed by legacy code, due to offset from reg0 */
955 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, regs
);
957 ejtag_info
->reg8
= regs
[8]; /* reg8 is saved but not restored, next called function should restore it */
958 ejtag_info
->reg9
= regs
[9];
960 pracc_queue_free(&ctx
);
964 /* fastdata upload/download requires an initialized working area
965 * to load the download code; it should not be called otherwise
966 * fetch order from the fastdata area
971 int mips32_pracc_fastdata_xfer(struct mips_ejtag
*ejtag_info
, struct working_area
*source
,
972 int write_t
, uint32_t addr
, int count
, uint32_t *buf
)
974 uint32_t handler_code
[] = {
975 /* caution when editing, table is modified below */
976 /* r15 points to the start of this code */
977 MIPS32_SW(8, MIPS32_FASTDATA_HANDLER_SIZE
- 4, 15),
978 MIPS32_SW(9, MIPS32_FASTDATA_HANDLER_SIZE
- 8, 15),
979 MIPS32_SW(10, MIPS32_FASTDATA_HANDLER_SIZE
- 12, 15),
980 MIPS32_SW(11, MIPS32_FASTDATA_HANDLER_SIZE
- 16, 15),
981 /* start of fastdata area in t0 */
982 MIPS32_LUI(8, UPPER16(MIPS32_PRACC_FASTDATA_AREA
)),
983 MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA
)),
984 MIPS32_LW(9, 0, 8), /* start addr in t1 */
985 MIPS32_LW(10, 0, 8), /* end addr to t2 */
987 /* 8 */ MIPS32_LW(11, 0, 0), /* lw t3,[t8 | r9] */
988 /* 9 */ MIPS32_SW(11, 0, 0), /* sw t3,[r9 | r8] */
989 MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */
990 MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */
992 MIPS32_LW(8, MIPS32_FASTDATA_HANDLER_SIZE
- 4, 15),
993 MIPS32_LW(9, MIPS32_FASTDATA_HANDLER_SIZE
- 8, 15),
994 MIPS32_LW(10, MIPS32_FASTDATA_HANDLER_SIZE
- 12, 15),
995 MIPS32_LW(11, MIPS32_FASTDATA_HANDLER_SIZE
- 16, 15),
997 MIPS32_LUI(15, UPPER16(MIPS32_PRACC_TEXT
)),
998 MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_TEXT
)),
999 MIPS32_JR(15), /* jr start */
1000 MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
1003 uint32_t jmp_code
[] = {
1004 MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
1005 /* 1 */ MIPS32_LUI(15, 0), /* addr of working area added below */
1006 /* 2 */ MIPS32_ORI(15, 15, 0), /* addr of working area added below */
1007 MIPS32_JR(15), /* jump to ram program */
1012 uint32_t val
, ejtag_ctrl
, address
;
1014 if (source
->size
< MIPS32_FASTDATA_HANDLER_SIZE
)
1015 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1018 handler_code
[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */
1019 handler_code
[9] = MIPS32_SW(11, 0, 9); /* store data to RAM @ r9 */
1021 handler_code
[8] = MIPS32_LW(11, 0, 9); /* load data from RAM @ r9 */
1022 handler_code
[9] = MIPS32_SW(11, 0, 8); /* store data to probe at fastdata area */
1025 /* write program into RAM */
1026 if (write_t
!= ejtag_info
->fast_access_save
) {
1027 mips32_pracc_write_mem_generic(ejtag_info
, source
->address
, 4, ARRAY_SIZE(handler_code
), handler_code
);
1028 /* save previous operation to speed to any consecutive read/writes */
1029 ejtag_info
->fast_access_save
= write_t
;
1032 LOG_DEBUG("%s using 0x%.8" PRIx32
" for write handler", __func__
, source
->address
);
1034 jmp_code
[1] |= UPPER16(source
->address
);
1035 jmp_code
[2] |= LOWER16(source
->address
);
1037 for (i
= 0; i
< (int) ARRAY_SIZE(jmp_code
); i
++) {
1038 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
1039 if (retval
!= ERROR_OK
)
1042 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
1043 mips_ejtag_drscan_32_out(ejtag_info
, jmp_code
[i
]);
1045 /* Clear the access pending bit (let the processor eat!) */
1046 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
1047 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
1048 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
1051 /* wait PrAcc pending bit for FASTDATA write */
1052 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
1053 if (retval
!= ERROR_OK
)
1056 /* next fetch to dmseg should be in FASTDATA_AREA, check */
1058 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
1059 retval
= mips_ejtag_drscan_32(ejtag_info
, &address
);
1060 if (retval
!= ERROR_OK
)
1063 if (address
!= MIPS32_PRACC_FASTDATA_AREA
)
1066 /* Send the load start address */
1068 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_FASTDATA
);
1069 mips_ejtag_fastdata_scan(ejtag_info
, 1, &val
);
1071 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
1072 if (retval
!= ERROR_OK
)
1075 /* Send the load end address */
1076 val
= addr
+ (count
- 1) * 4;
1077 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_FASTDATA
);
1078 mips_ejtag_fastdata_scan(ejtag_info
, 1, &val
);
1080 unsigned num_clocks
= 0; /* like in legacy code */
1081 if (ejtag_info
->mode
!= 0)
1082 num_clocks
= ((uint64_t)(ejtag_info
->scan_delay
) * jtag_get_speed_khz() + 500000) / 1000000;
1084 for (i
= 0; i
< count
; i
++) {
1085 jtag_add_clocks(num_clocks
);
1086 retval
= mips_ejtag_fastdata_scan(ejtag_info
, write_t
, buf
++);
1087 if (retval
!= ERROR_OK
)
1091 retval
= jtag_execute_queue();
1092 if (retval
!= ERROR_OK
) {
1093 LOG_ERROR("fastdata load failed");
1097 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
1098 if (retval
!= ERROR_OK
)
1102 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
1103 retval
= mips_ejtag_drscan_32(ejtag_info
, &address
);
1104 if (retval
!= ERROR_OK
)
1107 if (address
!= MIPS32_PRACC_TEXT
)
1108 LOG_ERROR("mini program did not return to start");
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then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)