1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
28 #include "mips_ejtag.h"
29 #include "mips32_dmaacc.h"
31 void mips_ejtag_set_instr(struct mips_ejtag
*ejtag_info
, uint32_t new_instr
)
33 assert(ejtag_info
->tap
!= NULL
);
34 struct jtag_tap
*tap
= ejtag_info
->tap
;
36 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
) {
38 struct scan_field field
;
39 field
.num_bits
= tap
->ir_length
;
43 buf_set_u32(t
, 0, field
.num_bits
, new_instr
);
45 field
.in_value
= NULL
;
47 jtag_add_ir_scan(tap
, &field
, TAP_IDLE
);
51 int mips_ejtag_get_idcode(struct mips_ejtag
*ejtag_info
)
53 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IDCODE
);
55 ejtag_info
->idcode
= 0;
56 return mips_ejtag_drscan_32(ejtag_info
, &ejtag_info
->idcode
);
59 int mips_ejtag_get_impcode(struct mips_ejtag
*ejtag_info
)
61 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_IMPCODE
);
63 ejtag_info
->impcode
= 0;
64 return mips_ejtag_drscan_32(ejtag_info
, &ejtag_info
->impcode
);
67 void mips_ejtag_add_scan_96(struct mips_ejtag
*ejtag_info
, uint32_t ctrl
, uint32_t data
, uint8_t *in_scan_buf
)
69 assert(ejtag_info
->tap
!= NULL
);
70 struct jtag_tap
*tap
= ejtag_info
->tap
;
72 struct scan_field field
;
75 /* processor access "all" register 96 bit */
78 field
.out_value
= out_scan
;
79 buf_set_u32(out_scan
, 0, 32, ctrl
);
80 buf_set_u32(out_scan
+ 4, 0, 32, data
);
81 buf_set_u32(out_scan
+ 8, 0, 32, 0);
83 field
.in_value
= in_scan_buf
;
85 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
90 void mips_ejtag_drscan_32_queued(struct mips_ejtag
*ejtag_info
, uint32_t data_out
, uint8_t *data_in
)
92 assert(ejtag_info
->tap
!= NULL
);
93 struct jtag_tap
*tap
= ejtag_info
->tap
;
95 struct scan_field field
;
99 field
.out_value
= scan_out
;
100 buf_set_u32(scan_out
, 0, field
.num_bits
, data_out
);
102 field
.in_value
= data_in
;
103 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
108 int mips_ejtag_drscan_32(struct mips_ejtag
*ejtag_info
, uint32_t *data
)
111 mips_ejtag_drscan_32_queued(ejtag_info
, *data
, scan_in
);
113 int retval
= jtag_execute_queue();
114 if (retval
!= ERROR_OK
) {
115 LOG_ERROR("register read failed");
119 *data
= buf_get_u32(scan_in
, 0, 32);
123 void mips_ejtag_drscan_32_out(struct mips_ejtag
*ejtag_info
, uint32_t data
)
125 mips_ejtag_drscan_32_queued(ejtag_info
, data
, NULL
);
128 int mips_ejtag_drscan_8(struct mips_ejtag
*ejtag_info
, uint8_t *data
)
130 assert(ejtag_info
->tap
!= NULL
);
131 struct jtag_tap
*tap
= ejtag_info
->tap
;
133 struct scan_field field
;
136 field
.out_value
= data
;
137 field
.in_value
= data
;
139 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
141 int retval
= jtag_execute_queue();
142 if (retval
!= ERROR_OK
) {
143 LOG_ERROR("register read failed");
149 void mips_ejtag_drscan_8_out(struct mips_ejtag
*ejtag_info
, uint8_t data
)
151 assert(ejtag_info
->tap
!= NULL
);
152 struct jtag_tap
*tap
= ejtag_info
->tap
;
154 struct scan_field field
;
157 field
.out_value
= &data
;
158 field
.in_value
= NULL
;
160 jtag_add_dr_scan(tap
, 1, &field
, TAP_IDLE
);
163 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
164 int mips_ejtag_config_step(struct mips_ejtag
*ejtag_info
, int enable_step
)
166 struct pracc_queue_info ctx
= {.ejtag_info
= ejtag_info
};
167 pracc_queue_init(&ctx
);
169 pracc_add(&ctx
, 0, MIPS32_MFC0(ctx
.isa
, 8, 23, 0)); /* move COP0 Debug to $8 */
170 pracc_add(&ctx
, 0, MIPS32_ORI(ctx
.isa
, 8, 8, 0x0100)); /* set SSt bit in debug reg */
172 pracc_add(&ctx
, 0, MIPS32_XORI(ctx
.isa
, 8, 8, 0x0100)); /* clear SSt bit in debug reg */
174 pracc_add(&ctx
, 0, MIPS32_MTC0(ctx
.isa
, 8, 23, 0)); /* move $8 to COP0 Debug */
175 pracc_add(&ctx
, 0, MIPS32_LUI(ctx
.isa
, 8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of $8 */
176 pracc_add(&ctx
, 0, MIPS32_B(ctx
.isa
, NEG16((ctx
.code_count
+ 1) << ctx
.isa
))); /* jump to start */
177 pracc_add(&ctx
, 0, MIPS32_ORI(ctx
.isa
, 8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of $8 */
179 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
, 1);
180 pracc_queue_free(&ctx
);
185 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
186 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
187 * For example bcm7401 and others. At leas on some
188 * CPUs, DebugMode wont start if this bit is not removed.
190 static int disable_dcr_mp(struct mips_ejtag
*ejtag_info
)
195 retval
= mips32_dmaacc_read_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
196 if (retval
!= ERROR_OK
)
199 dcr
&= ~EJTAG_DCR_MP
;
200 retval
= mips32_dmaacc_write_mem(ejtag_info
, EJTAG_DCR
, 4, 1, &dcr
);
201 if (retval
!= ERROR_OK
)
205 LOG_ERROR("Failed to remove DCR MPbit!");
209 int mips_ejtag_enter_debug(struct mips_ejtag
*ejtag_info
)
212 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
214 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
215 if (disable_dcr_mp(ejtag_info
) != ERROR_OK
)
219 /* set debug break bit */
220 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_JTAGBRK
;
221 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
223 /* break bit will be cleared by hardware */
224 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
225 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
226 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32
"", ejtag_ctrl
);
227 if ((ejtag_ctrl
& EJTAG_CTRL_BRKST
) == 0)
232 LOG_ERROR("Failed to enter Debug Mode!");
236 int mips_ejtag_exit_debug(struct mips_ejtag
*ejtag_info
)
238 pa_list pracc_list
= {.instr
= MIPS32_DRET(ejtag_info
->isa
), .addr
= 0};
239 struct pracc_queue_info ctx
= {.max_code
= 1, .pracc_list
= &pracc_list
, .code_count
= 1, .store_count
= 0};
241 /* execute our dret instruction */
242 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
, 0); /* shift out instr, omit last check */
244 /* pic32mx workaround, false pending at low core clock */
245 jtag_add_sleep(1000);
249 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
252 static void mips_ejtag_init_mmr(struct mips_ejtag
*ejtag_info
)
254 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
) {
255 ejtag_info
->ejtag_ibs_addr
= EJTAG_V20_IBS
;
256 ejtag_info
->ejtag_iba0_addr
= EJTAG_V20_IBA0
;
257 ejtag_info
->ejtag_ibc_offs
= EJTAG_V20_IBC_OFFS
;
258 ejtag_info
->ejtag_ibm_offs
= EJTAG_V20_IBM_OFFS
;
260 ejtag_info
->ejtag_dbs_addr
= EJTAG_V20_DBS
;
261 ejtag_info
->ejtag_dba0_addr
= EJTAG_V20_DBA0
;
262 ejtag_info
->ejtag_dbc_offs
= EJTAG_V20_DBC_OFFS
;
263 ejtag_info
->ejtag_dbm_offs
= EJTAG_V20_DBM_OFFS
;
264 ejtag_info
->ejtag_dbv_offs
= EJTAG_V20_DBV_OFFS
;
266 ejtag_info
->ejtag_iba_step_size
= EJTAG_V20_IBAn_STEP
;
267 ejtag_info
->ejtag_dba_step_size
= EJTAG_V20_DBAn_STEP
;
269 ejtag_info
->ejtag_ibs_addr
= EJTAG_V25_IBS
;
270 ejtag_info
->ejtag_iba0_addr
= EJTAG_V25_IBA0
;
271 ejtag_info
->ejtag_ibm_offs
= EJTAG_V25_IBM_OFFS
;
272 ejtag_info
->ejtag_ibasid_offs
= EJTAG_V25_IBASID_OFFS
;
273 ejtag_info
->ejtag_ibc_offs
= EJTAG_V25_IBC_OFFS
;
275 ejtag_info
->ejtag_dbs_addr
= EJTAG_V25_DBS
;
276 ejtag_info
->ejtag_dba0_addr
= EJTAG_V25_DBA0
;
277 ejtag_info
->ejtag_dbm_offs
= EJTAG_V25_DBM_OFFS
;
278 ejtag_info
->ejtag_dbasid_offs
= EJTAG_V25_DBASID_OFFS
;
279 ejtag_info
->ejtag_dbc_offs
= EJTAG_V25_DBC_OFFS
;
280 ejtag_info
->ejtag_dbv_offs
= EJTAG_V25_DBV_OFFS
;
282 ejtag_info
->ejtag_iba_step_size
= EJTAG_V25_IBAn_STEP
;
283 ejtag_info
->ejtag_dba_step_size
= EJTAG_V25_DBAn_STEP
;
287 static void ejtag_v20_print_imp(struct mips_ejtag
*ejtag_info
)
289 LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
290 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP
) ? " SDBBP_SPECIAL2" : " SDBBP",
291 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT
) ? " EADDR>32bit" : " EADDR=32bit",
292 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK
) ? " COMPLEX_BREAK" : "",
293 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH
) ? " DCACHE_COH" : " DCACHE_NOT_COH",
294 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH
) ? " ICACHE_COH" : " ICACHE_NOT_COH",
295 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB
) ? " noPB" : " PB",
296 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB
) ? " noDB" : " DB",
297 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB
) ? " noIB" : " IB");
298 LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8
,
299 (uint8_t)((ejtag_info
->impcode
>> EJTAG_V20_IMP_BCHANNELS_SHIFT
) &
300 EJTAG_V20_IMP_BCHANNELS_MASK
));
303 static void ejtag_v26_print_imp(struct mips_ejtag
*ejtag_info
)
305 LOG_DEBUG("EJTAG v2.6: features:%s%s",
306 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K
) ? " R3k" : " R4k",
307 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT
) ? " DINT" : "");
310 static void ejtag_main_print_imp(struct mips_ejtag
*ejtag_info
)
312 LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
313 EJTAG_IMP_HAS(EJTAG_IMP_ASID8
) ? " ASID_8" : "",
314 EJTAG_IMP_HAS(EJTAG_IMP_ASID6
) ? " ASID_6" : "",
315 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16
) ? " MIPS16" : "",
316 EJTAG_IMP_HAS(EJTAG_IMP_NODMA
) ? " noDMA" : " DMA",
317 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64
) ? " MIPS64" : " MIPS32");
319 switch (ejtag_info
->ejtag_version
) {
320 case EJTAG_VERSION_20
:
321 ejtag_v20_print_imp(ejtag_info
);
323 case EJTAG_VERSION_25
:
324 case EJTAG_VERSION_26
:
325 case EJTAG_VERSION_31
:
326 case EJTAG_VERSION_41
:
327 case EJTAG_VERSION_51
:
328 ejtag_v26_print_imp(ejtag_info
);
335 int mips_ejtag_init(struct mips_ejtag
*ejtag_info
)
337 int retval
= mips_ejtag_get_impcode(ejtag_info
);
338 if (retval
!= ERROR_OK
) {
339 LOG_ERROR("impcode read failed");
343 /* get ejtag version */
344 ejtag_info
->ejtag_version
= ((ejtag_info
->impcode
>> 29) & 0x07);
346 switch (ejtag_info
->ejtag_version
) {
347 case EJTAG_VERSION_20
:
348 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
350 case EJTAG_VERSION_25
:
351 LOG_DEBUG("EJTAG: Version 2.5 Detected");
353 case EJTAG_VERSION_26
:
354 LOG_DEBUG("EJTAG: Version 2.6 Detected");
356 case EJTAG_VERSION_31
:
357 LOG_DEBUG("EJTAG: Version 3.1 Detected");
359 case EJTAG_VERSION_41
:
360 LOG_DEBUG("EJTAG: Version 4.1 Detected");
362 case EJTAG_VERSION_51
:
363 LOG_DEBUG("EJTAG: Version 5.1 Detected");
366 LOG_DEBUG("EJTAG: Unknown Version Detected");
369 ejtag_main_print_imp(ejtag_info
);
371 if ((ejtag_info
->impcode
& EJTAG_IMP_NODMA
) == 0) {
372 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
373 "workaround current broken code.");
374 ejtag_info
->impcode
|= EJTAG_IMP_NODMA
;
377 ejtag_info
->ejtag_ctrl
= EJTAG_CTRL_PRACC
| EJTAG_CTRL_PROBEN
;
379 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
)
380 ejtag_info
->ejtag_ctrl
|= EJTAG_CTRL_ROCC
| EJTAG_CTRL_SETDEV
;
382 ejtag_info
->fast_access_save
= -1;
384 mips_ejtag_init_mmr(ejtag_info
);
389 int mips_ejtag_fastdata_scan(struct mips_ejtag
*ejtag_info
, int write_t
, uint32_t *data
)
391 assert(ejtag_info
->tap
!= NULL
);
392 struct jtag_tap
*tap
= ejtag_info
->tap
;
394 struct scan_field fields
[2];
396 /* fastdata 1-bit register */
397 fields
[0].num_bits
= 1;
400 fields
[0].out_value
= &spracc
;
401 fields
[0].in_value
= NULL
;
403 /* processor access data register 32 bit */
404 fields
[1].num_bits
= 32;
406 uint8_t t
[4] = {0, 0, 0, 0};
407 fields
[1].out_value
= t
;
410 fields
[1].in_value
= NULL
;
411 buf_set_u32(t
, 0, 32, *data
);
413 fields
[1].in_value
= (uint8_t *) data
;
415 jtag_add_dr_scan(tap
, 2, fields
, TAP_IDLE
);
417 if (!write_t
&& data
)
418 jtag_add_callback(mips_le_to_h_u32
,
419 (jtag_callback_data_t
) data
);
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