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mips32, pic32 use uint8_t in 8 bit scan function
[openocd.git] / src / target / mips_ejtag.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
22
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "mips32.h"
28 #include "mips_ejtag.h"
29 #include "mips32_dmaacc.h"
30
31 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
32 {
33 struct jtag_tap *tap;
34
35 tap = ejtag_info->tap;
36 assert(tap != NULL);
37
38 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
39 struct scan_field field;
40 uint8_t t[4];
41
42 field.num_bits = tap->ir_length;
43 field.out_value = t;
44 buf_set_u32(t, 0, field.num_bits, new_instr);
45 field.in_value = NULL;
46
47 jtag_add_ir_scan(tap, &field, TAP_IDLE);
48 }
49 }
50
51 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
52 {
53 struct scan_field field;
54 uint8_t r[4];
55
56 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
57
58 field.num_bits = 32;
59 field.out_value = NULL;
60 field.in_value = r;
61
62 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
63
64 int retval;
65 retval = jtag_execute_queue();
66 if (retval != ERROR_OK) {
67 LOG_ERROR("register read failed");
68 return retval;
69 }
70
71 *idcode = buf_get_u32(field.in_value, 0, 32);
72
73 return ERROR_OK;
74 }
75
76 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
77 {
78 struct scan_field field;
79 uint8_t r[4];
80
81 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
82
83 field.num_bits = 32;
84 field.out_value = NULL;
85 field.in_value = r;
86
87 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
88
89 int retval;
90 retval = jtag_execute_queue();
91 if (retval != ERROR_OK) {
92 LOG_ERROR("register read failed");
93 return retval;
94 }
95
96 *impcode = buf_get_u32(field.in_value, 0, 32);
97
98 return ERROR_OK;
99 }
100
101 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
102 {
103 assert(ejtag_info->tap != NULL);
104 struct jtag_tap *tap = ejtag_info->tap;
105
106 struct scan_field field;
107 uint8_t out_scan[12];
108
109 /* processor access "all" register 96 bit */
110 field.num_bits = 96;
111
112 field.out_value = out_scan;
113 buf_set_u32(out_scan, 0, 32, ctrl);
114 buf_set_u32(out_scan + 4, 0, 32, data);
115 buf_set_u32(out_scan + 8, 0, 32, 0);
116
117 field.in_value = in_scan_buf;
118
119 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
120
121 keep_alive();
122 }
123
124 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
125 {
126 struct jtag_tap *tap;
127 tap = ejtag_info->tap;
128 assert(tap != NULL);
129
130 struct scan_field field;
131 uint8_t t[4], r[4];
132 int retval;
133
134 field.num_bits = 32;
135 field.out_value = t;
136 buf_set_u32(t, 0, field.num_bits, *data);
137 field.in_value = r;
138
139 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
140
141 retval = jtag_execute_queue();
142 if (retval != ERROR_OK) {
143 LOG_ERROR("register read failed");
144 return retval;
145 }
146
147 *data = buf_get_u32(field.in_value, 0, 32);
148
149 keep_alive();
150
151 return ERROR_OK;
152 }
153
154 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
155 {
156 uint8_t t[4];
157 struct jtag_tap *tap;
158 tap = ejtag_info->tap;
159 assert(tap != NULL);
160
161 struct scan_field field;
162
163 field.num_bits = 32;
164 field.out_value = t;
165 buf_set_u32(t, 0, field.num_bits, data);
166
167 field.in_value = NULL;
168
169 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
170 }
171
172 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
173 {
174 assert(ejtag_info->tap != NULL);
175 struct jtag_tap *tap = ejtag_info->tap;
176
177 struct scan_field field;
178 field.num_bits = 8;
179
180 field.out_value = data;
181 field.in_value = data;
182
183 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
184
185 int retval = jtag_execute_queue();
186 if (retval != ERROR_OK) {
187 LOG_ERROR("register read failed");
188 return retval;
189 }
190 return ERROR_OK;
191 }
192
193 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
194 {
195 struct jtag_tap *tap;
196 tap = ejtag_info->tap;
197 assert(tap != NULL);
198
199 struct scan_field field;
200
201 field.num_bits = 8;
202 field.out_value = &data;
203 field.in_value = NULL;
204
205 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
206 }
207
208 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
209 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
210 {
211 struct pracc_queue_info ctx = {.max_code = 7};
212 pracc_queue_init(&ctx);
213 if (ctx.retval != ERROR_OK)
214 goto exit;
215
216 pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
217 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
218 if (!enable_step)
219 pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
220
221 pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
222 pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
223 pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
224 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
225
226 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
227 exit:
228 pracc_queue_free(&ctx);
229 return ctx.retval;
230 }
231
232 /*
233 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
234 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
235 * For example bcm7401 and others. At leas on some
236 * CPUs, DebugMode wont start if this bit is not removed.
237 */
238 static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
239 {
240 uint32_t dcr;
241 int retval;
242
243 retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
244 if (retval != ERROR_OK)
245 goto error;
246
247 dcr &= ~EJTAG_DCR_MP;
248 retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
249 if (retval != ERROR_OK)
250 goto error;
251 return ERROR_OK;
252 error:
253 LOG_ERROR("Failed to remove DCR MPbit!");
254 return retval;
255 }
256
257 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
258 {
259 uint32_t ejtag_ctrl;
260 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
261
262 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
263 if (disable_dcr_mp(ejtag_info) != ERROR_OK)
264 goto error;
265 }
266
267 /* set debug break bit */
268 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
269 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
270
271 /* break bit will be cleared by hardware */
272 ejtag_ctrl = ejtag_info->ejtag_ctrl;
273 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
274 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
275 if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
276 goto error;
277
278 return ERROR_OK;
279 error:
280 LOG_ERROR("Failed to enter Debug Mode!");
281 return ERROR_FAIL;
282 }
283
284 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
285 {
286 uint32_t pracc_list[] = {MIPS32_DRET, 0};
287 struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = pracc_list, .code_count = 1, .store_count = 0};
288
289 /* execute our dret instruction */
290 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
291
292 /* pic32mx workaround, false pending at low core clock */
293 jtag_add_sleep(1000);
294 return ctx.retval;
295 }
296
297 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
298 * on EJTAG version.
299 */
300 static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
301 {
302 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
303 ejtag_info->ejtag_ibs_addr = EJTAG_V20_IBS;
304 ejtag_info->ejtag_iba0_addr = EJTAG_V20_IBA0;
305 ejtag_info->ejtag_ibc_offs = EJTAG_V20_IBC_OFFS;
306 ejtag_info->ejtag_ibm_offs = EJTAG_V20_IBM_OFFS;
307
308 ejtag_info->ejtag_dbs_addr = EJTAG_V20_DBS;
309 ejtag_info->ejtag_dba0_addr = EJTAG_V20_DBA0;
310 ejtag_info->ejtag_dbc_offs = EJTAG_V20_DBC_OFFS;
311 ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS;
312 ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS;
313
314 ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
315 ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
316 } else {
317 ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS;
318 ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0;
319 ejtag_info->ejtag_ibm_offs = EJTAG_V25_IBM_OFFS;
320 ejtag_info->ejtag_ibasid_offs = EJTAG_V25_IBASID_OFFS;
321 ejtag_info->ejtag_ibc_offs = EJTAG_V25_IBC_OFFS;
322
323 ejtag_info->ejtag_dbs_addr = EJTAG_V25_DBS;
324 ejtag_info->ejtag_dba0_addr = EJTAG_V25_DBA0;
325 ejtag_info->ejtag_dbm_offs = EJTAG_V25_DBM_OFFS;
326 ejtag_info->ejtag_dbasid_offs = EJTAG_V25_DBASID_OFFS;
327 ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS;
328 ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS;
329
330 ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
331 ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
332 }
333 }
334
335 static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
336 {
337 LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
338 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
339 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
340 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
341 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
342 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
343 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
344 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
345 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
346 LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
347 (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
348 EJTAG_V20_IMP_BCHANNELS_MASK));
349 }
350
351 static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
352 {
353 LOG_DEBUG("EJTAG v2.6: features:%s%s",
354 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
355 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
356 }
357
358 static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
359 {
360 LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
361 EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
362 EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
363 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
364 EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
365 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64) ? " MIPS64" : " MIPS32");
366
367 switch (ejtag_info->ejtag_version) {
368 case EJTAG_VERSION_20:
369 ejtag_v20_print_imp(ejtag_info);
370 break;
371 case EJTAG_VERSION_25:
372 case EJTAG_VERSION_26:
373 case EJTAG_VERSION_31:
374 case EJTAG_VERSION_41:
375 case EJTAG_VERSION_51:
376 ejtag_v26_print_imp(ejtag_info);
377 break;
378 default:
379 break;
380 }
381 }
382
383 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
384 {
385 int retval;
386
387 retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
388 if (retval != ERROR_OK)
389 return retval;
390 LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
391
392 /* get ejtag version */
393 ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
394
395 switch (ejtag_info->ejtag_version) {
396 case EJTAG_VERSION_20:
397 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
398 break;
399 case EJTAG_VERSION_25:
400 LOG_DEBUG("EJTAG: Version 2.5 Detected");
401 break;
402 case EJTAG_VERSION_26:
403 LOG_DEBUG("EJTAG: Version 2.6 Detected");
404 break;
405 case EJTAG_VERSION_31:
406 LOG_DEBUG("EJTAG: Version 3.1 Detected");
407 break;
408 case EJTAG_VERSION_41:
409 LOG_DEBUG("EJTAG: Version 4.1 Detected");
410 break;
411 case EJTAG_VERSION_51:
412 LOG_DEBUG("EJTAG: Version 5.1 Detected");
413 break;
414 default:
415 LOG_DEBUG("EJTAG: Unknown Version Detected");
416 break;
417 }
418 ejtag_main_print_imp(ejtag_info);
419
420 if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
421 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
422 "workaround current broken code.");
423 ejtag_info->impcode |= EJTAG_IMP_NODMA;
424 }
425
426 ejtag_info->ejtag_ctrl = EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN;
427
428 if (ejtag_info->ejtag_version != EJTAG_VERSION_20)
429 ejtag_info->ejtag_ctrl |= EJTAG_CTRL_ROCC | EJTAG_CTRL_SETDEV;
430
431 ejtag_info->fast_access_save = -1;
432
433 mips_ejtag_init_mmr(ejtag_info);
434
435 return ERROR_OK;
436 }
437
438 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
439 {
440 struct jtag_tap *tap;
441
442 tap = ejtag_info->tap;
443 assert(tap != NULL);
444
445 struct scan_field fields[2];
446 uint8_t spracc = 0;
447 uint8_t t[4] = {0, 0, 0, 0};
448
449 /* fastdata 1-bit register */
450 fields[0].num_bits = 1;
451 fields[0].out_value = &spracc;
452 fields[0].in_value = NULL;
453
454 /* processor access data register 32 bit */
455 fields[1].num_bits = 32;
456 fields[1].out_value = t;
457
458 if (write_t) {
459 fields[1].in_value = NULL;
460 buf_set_u32(t, 0, 32, *data);
461 } else
462 fields[1].in_value = (uint8_t *) data;
463
464 jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
465
466 if (!write_t && data)
467 jtag_add_callback(mips_le_to_h_u32,
468 (jtag_callback_data_t) data);
469
470 keep_alive();
471
472 return ERROR_OK;
473 }
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