1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
37 /* forward declarations */
38 int mips_m4k_poll(target_t
*target
);
39 int mips_m4k_halt(struct target_s
*target
);
40 int mips_m4k_soft_reset_halt(struct target_s
*target
);
41 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
42 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
43 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
44 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
45 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
);
46 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int mips_m4k_quit(void);
48 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
);
50 int mips_m4k_examine(struct target_s
*target
);
51 int mips_m4k_assert_reset(target_t
*target
);
52 int mips_m4k_deassert_reset(target_t
*target
);
54 target_type_t mips_m4k_target
=
58 .poll
= mips_m4k_poll
,
59 .arch_state
= mips32_arch_state
,
61 .target_request_data
= NULL
,
63 .halt
= mips_m4k_halt
,
64 .resume
= mips_m4k_resume
,
65 .step
= mips_m4k_step
,
67 .assert_reset
= mips_m4k_assert_reset
,
68 .deassert_reset
= mips_m4k_deassert_reset
,
69 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
71 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
73 .read_memory
= mips_m4k_read_memory
,
74 .write_memory
= mips_m4k_write_memory
,
75 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
76 .checksum_memory
= NULL
,
77 .blank_check_memory
= NULL
,
79 .run_algorithm
= mips32_run_algorithm
,
81 .add_breakpoint
= mips_m4k_add_breakpoint
,
82 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
83 .add_watchpoint
= mips_m4k_add_watchpoint
,
84 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
86 .register_commands
= mips_m4k_register_commands
,
87 .target_create
= mips_m4k_target_create
,
88 .init_target
= mips_m4k_init_target
,
89 .examine
= mips_m4k_examine
,
93 int mips_m4k_examine_debug_reason(target_t
*target
)
98 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
99 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
101 /* get info about inst breakpoint support */
102 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
104 if (break_status
& 0x1f)
106 /* we have halted on a breakpoint */
107 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
109 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
112 /* get info about data breakpoint support */
113 if ((retval
= target_read_u32(target
, 0xFF302000, &break_status
)) != ERROR_OK
)
115 if (break_status
& 0x1f)
117 /* we have halted on a breakpoint */
118 if ((retval
= target_write_u32(target
, 0xFF302000, 0)) != ERROR_OK
)
120 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
127 int mips_m4k_debug_entry(target_t
*target
)
129 mips32_common_t
*mips32
= target
->arch_info
;
130 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
133 /* read debug register */
134 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
136 /* make sure break uit configured */
137 mips32_configure_break_unit(target
);
139 /* attempt to find halt reason */
140 mips_m4k_examine_debug_reason(target
);
142 /* clear single step if active */
143 if (debug_reg
& EJTAG_DEBUG_DSS
)
145 /* stopped due to single step - clear step bit */
146 mips_ejtag_config_step(ejtag_info
, 0);
149 mips32_save_context(target
);
151 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
152 *(u32
*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
153 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
158 int mips_m4k_poll(target_t
*target
)
161 mips32_common_t
*mips32
= target
->arch_info
;
162 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
163 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
165 /* read ejtag control reg */
166 jtag_add_end_state(TAP_IDLE
);
167 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
168 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
170 /* clear this bit before handling polling
171 * as after reset registers will read zero */
172 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
174 /* we have detected a reset, clear flag
175 * otherwise ejtag will not work */
176 jtag_add_end_state(TAP_IDLE
);
177 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
179 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
180 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
181 LOG_DEBUG("Reset Detected");
184 /* check for processor halted */
185 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
187 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
189 jtag_add_end_state(TAP_IDLE
);
190 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
192 target
->state
= TARGET_HALTED
;
194 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
197 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
199 else if (target
->state
== TARGET_DEBUG_RUNNING
)
201 target
->state
= TARGET_HALTED
;
203 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
206 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
211 target
->state
= TARGET_RUNNING
;
214 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
219 int mips_m4k_halt(struct target_s
*target
)
221 mips32_common_t
*mips32
= target
->arch_info
;
222 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
224 LOG_DEBUG("target->state: %s",
225 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
227 if (target
->state
== TARGET_HALTED
)
229 LOG_DEBUG("target was already halted");
233 if (target
->state
== TARGET_UNKNOWN
)
235 LOG_WARNING("target was in unknown state when halt was requested");
238 if (target
->state
== TARGET_RESET
)
240 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
242 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
243 return ERROR_TARGET_FAILURE
;
247 /* we came here in a reset_halt or reset_init sequence
248 * debug entry was already prepared in mips32_prepare_reset_halt()
250 target
->debug_reason
= DBG_REASON_DBGRQ
;
256 /* break processor */
257 mips_ejtag_enter_debug(ejtag_info
);
259 target
->debug_reason
= DBG_REASON_DBGRQ
;
264 int mips_m4k_assert_reset(target_t
*target
)
266 mips32_common_t
*mips32
= target
->arch_info
;
267 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
269 LOG_DEBUG("target->state: %s",
270 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
272 if (!(jtag_reset_config
& RESET_HAS_SRST
))
274 LOG_ERROR("Can't assert SRST");
278 if (target
->reset_halt
)
280 /* use hardware to catch reset */
281 jtag_add_end_state(TAP_IDLE
);
282 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
286 jtag_add_end_state(TAP_IDLE
);
287 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
290 if (strcmp(target
->variant
, "ejtag_srst") == 0)
292 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
293 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
294 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
295 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
299 /* here we should issue a srst only, but we may have to assert trst as well */
300 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
302 jtag_add_reset(1, 1);
306 jtag_add_reset(0, 1);
310 target
->state
= TARGET_RESET
;
311 jtag_add_sleep(50000);
313 mips32_invalidate_core_regs(target
);
315 if (target
->reset_halt
)
318 if ((retval
= target_halt(target
))!=ERROR_OK
)
325 int mips_m4k_deassert_reset(target_t
*target
)
327 LOG_DEBUG("target->state: %s",
328 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
330 /* deassert reset lines */
331 jtag_add_reset(0, 0);
336 int mips_m4k_soft_reset_halt(struct target_s
*target
)
342 int mips_m4k_single_step_core(target_t
*target
)
344 mips32_common_t
*mips32
= target
->arch_info
;
345 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
347 /* configure single step mode */
348 mips_ejtag_config_step(ejtag_info
, 1);
350 /* exit debug mode */
351 mips_ejtag_exit_debug(ejtag_info
, 1);
353 mips_m4k_debug_entry(target
);
358 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
360 mips32_common_t
*mips32
= target
->arch_info
;
361 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
362 breakpoint_t
*breakpoint
= NULL
;
365 if (target
->state
!= TARGET_HALTED
)
367 LOG_WARNING("target not halted");
368 return ERROR_TARGET_NOT_HALTED
;
371 if (!debug_execution
)
373 target_free_all_working_areas(target
);
374 mips_m4k_enable_breakpoints(target
);
375 mips_m4k_enable_watchpoints(target
);
378 /* current = 1: continue on current pc, otherwise continue at <address> */
381 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
382 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
383 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
386 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
388 mips32_restore_context(target
);
390 /* the front-end may request us not to handle breakpoints */
391 if (handle_breakpoints
)
393 /* Single step past breakpoint at current address */
394 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
396 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
397 mips_m4k_unset_breakpoint(target
, breakpoint
);
398 mips_m4k_single_step_core(target
);
399 mips_m4k_set_breakpoint(target
, breakpoint
);
403 /* exit debug mode - enable interrupts if required */
404 mips_ejtag_exit_debug(ejtag_info
, !debug_execution
);
405 target
->debug_reason
= DBG_REASON_NOTHALTED
;
407 /* registers are now invalid */
408 mips32_invalidate_core_regs(target
);
410 if (!debug_execution
)
412 target
->state
= TARGET_RUNNING
;
413 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
414 LOG_DEBUG("target resumed at 0x%x", resume_pc
);
418 target
->state
= TARGET_DEBUG_RUNNING
;
419 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
420 LOG_DEBUG("target debug resumed at 0x%x", resume_pc
);
426 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
428 /* get pointers to arch-specific information */
429 mips32_common_t
*mips32
= target
->arch_info
;
430 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
431 breakpoint_t
*breakpoint
= NULL
;
433 if (target
->state
!= TARGET_HALTED
)
435 LOG_WARNING("target not halted");
436 return ERROR_TARGET_NOT_HALTED
;
439 /* current = 1: continue on current pc, otherwise continue at <address> */
441 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
443 /* the front-end may request us not to handle breakpoints */
444 if (handle_breakpoints
)
445 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
446 mips_m4k_unset_breakpoint(target
, breakpoint
);
448 /* restore context */
449 mips32_restore_context(target
);
451 /* configure single step mode */
452 mips_ejtag_config_step(ejtag_info
, 1);
454 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
456 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
458 /* exit debug mode */
459 mips_ejtag_exit_debug(ejtag_info
, 1);
461 /* registers are now invalid */
462 mips32_invalidate_core_regs(target
);
465 mips_m4k_set_breakpoint(target
, breakpoint
);
467 LOG_DEBUG("target stepped ");
469 mips_m4k_debug_entry(target
);
470 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
475 void mips_m4k_enable_breakpoints(struct target_s
*target
)
477 breakpoint_t
*breakpoint
= target
->breakpoints
;
479 /* set any pending breakpoints */
482 if (breakpoint
->set
== 0)
483 mips_m4k_set_breakpoint(target
, breakpoint
);
484 breakpoint
= breakpoint
->next
;
488 int mips_m4k_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
490 mips32_common_t
*mips32
= target
->arch_info
;
491 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
495 LOG_WARNING("breakpoint already set");
499 if (breakpoint
->type
== BKPT_HARD
)
503 while(comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
505 if (bp_num
>= mips32
->num_inst_bpoints
)
507 LOG_DEBUG("ERROR Can not find free FP Comparator");
508 LOG_WARNING("ERROR Can not find free FP Comparator");
511 breakpoint
->set
= bp_num
+ 1;
512 comparator_list
[bp_num
].used
= 1;
513 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
514 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
515 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
516 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
517 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num
, comparator_list
[bp_num
].bp_value
);
519 else if (breakpoint
->type
== BKPT_SOFT
)
527 int mips_m4k_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
529 /* get pointers to arch-specific information */
530 mips32_common_t
*mips32
= target
->arch_info
;
531 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
533 if (!breakpoint
->set
)
535 LOG_WARNING("breakpoint not set");
539 if (breakpoint
->type
== BKPT_HARD
)
541 int bp_num
= breakpoint
->set
- 1;
542 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
544 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
547 comparator_list
[bp_num
].used
= 0;
548 comparator_list
[bp_num
].bp_value
= 0;
549 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
560 int mips_m4k_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
562 mips32_common_t
*mips32
= target
->arch_info
;
564 if (mips32
->num_inst_bpoints_avail
< 1)
566 LOG_INFO("no hardware breakpoint available");
567 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
570 /* default to hardware for now */
571 breakpoint
->type
= BKPT_HARD
;
573 mips32
->num_inst_bpoints_avail
--;
574 mips_m4k_set_breakpoint(target
, breakpoint
);
579 int mips_m4k_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
581 /* get pointers to arch-specific information */
582 mips32_common_t
*mips32
= target
->arch_info
;
584 if (target
->state
!= TARGET_HALTED
)
586 LOG_WARNING("target not halted");
587 return ERROR_TARGET_NOT_HALTED
;
592 mips_m4k_unset_breakpoint(target
, breakpoint
);
595 if (breakpoint
->type
== BKPT_HARD
)
596 mips32
->num_inst_bpoints_avail
++;
601 int mips_m4k_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
607 int mips_m4k_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
613 int mips_m4k_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
619 int mips_m4k_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
625 void mips_m4k_enable_watchpoints(struct target_s
*target
)
627 watchpoint_t
*watchpoint
= target
->watchpoints
;
629 /* set any pending watchpoints */
632 if (watchpoint
->set
== 0)
633 mips_m4k_set_watchpoint(target
, watchpoint
);
634 watchpoint
= watchpoint
->next
;
638 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
640 mips32_common_t
*mips32
= target
->arch_info
;
641 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
643 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
645 if (target
->state
!= TARGET_HALTED
)
647 LOG_WARNING("target not halted");
648 return ERROR_TARGET_NOT_HALTED
;
651 /* sanitize arguments */
652 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
653 return ERROR_INVALID_ARGUMENTS
;
655 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
656 return ERROR_TARGET_UNALIGNED_ACCESS
;
663 /* if noDMA off, use DMAACC mode for memory read */
664 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
665 return mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
667 return mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
669 LOG_ERROR("BUG: we shouldn't get here");
677 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
679 mips32_common_t
*mips32
= target
->arch_info
;
680 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
682 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
684 if (target
->state
!= TARGET_HALTED
)
686 LOG_WARNING("target not halted");
687 return ERROR_TARGET_NOT_HALTED
;
690 /* sanitize arguments */
691 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
692 return ERROR_INVALID_ARGUMENTS
;
694 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
695 return ERROR_TARGET_UNALIGNED_ACCESS
;
702 /* if noDMA off, use DMAACC mode for memory write */
703 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
704 mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
706 mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
709 LOG_ERROR("BUG: we shouldn't get here");
717 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
)
721 retval
= mips32_register_commands(cmd_ctx
);
725 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
727 mips32_build_reg_cache(target
);
732 int mips_m4k_quit(void)
737 int mips_m4k_init_arch_info(target_t
*target
, mips_m4k_common_t
*mips_m4k
, jtag_tap_t
*tap
)
739 mips32_common_t
*mips32
= &mips_m4k
->mips32_common
;
741 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
743 /* initialize mips4k specific info */
744 mips32_init_arch_info(target
, mips32
, tap
);
745 mips32
->arch_info
= mips_m4k
;
750 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
)
752 mips_m4k_common_t
*mips_m4k
= calloc(1,sizeof(mips_m4k_common_t
));
754 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
759 int mips_m4k_examine(struct target_s
*target
)
762 mips32_common_t
*mips32
= target
->arch_info
;
763 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
766 if (!target
->type
->examined
)
768 mips_ejtag_get_idcode(ejtag_info
, &idcode
, NULL
);
770 if (((idcode
>> 1) & 0x7FF) == 0x29)
772 /* we are using a pic32mx so select ejtag port
773 * as it is not selected by default */
774 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
775 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
779 /* init rest of ejtag interface */
780 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
783 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
789 int mips_m4k_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
791 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
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