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[openocd.git] / src / target / mips_m4k.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 * *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
25
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "breakpoints.h"
31 #include "mips32.h"
32 #include "mips_m4k.h"
33 #include "mips32_dmaacc.h"
34 #include "target_type.h"
35 #include "register.h"
36
37 static void mips_m4k_enable_breakpoints(struct target *target);
38 static void mips_m4k_enable_watchpoints(struct target *target);
39 static int mips_m4k_set_breakpoint(struct target *target,
40 struct breakpoint *breakpoint);
41 static int mips_m4k_unset_breakpoint(struct target *target,
42 struct breakpoint *breakpoint);
43 static int mips_m4k_internal_restore(struct target *target, int current,
44 uint32_t address, int handle_breakpoints,
45 int debug_execution);
46 static int mips_m4k_halt(struct target *target);
47 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
48 uint32_t count, const uint8_t *buffer);
49
50 static int mips_m4k_examine_debug_reason(struct target *target)
51 {
52 struct mips32_common *mips32 = target_to_mips32(target);
53 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
54 uint32_t break_status;
55 int retval;
56
57 if ((target->debug_reason != DBG_REASON_DBGRQ)
58 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
59 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
60 /* get info about inst breakpoint support */
61 retval = target_read_u32(target,
62 ejtag_info->ejtag_ibs_addr, &break_status);
63 if (retval != ERROR_OK)
64 return retval;
65 if (break_status & 0x1f) {
66 /* we have halted on a breakpoint */
67 retval = target_write_u32(target,
68 ejtag_info->ejtag_ibs_addr, 0);
69 if (retval != ERROR_OK)
70 return retval;
71 target->debug_reason = DBG_REASON_BREAKPOINT;
72 }
73 }
74
75 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
76 /* get info about data breakpoint support */
77 retval = target_read_u32(target,
78 ejtag_info->ejtag_dbs_addr, &break_status);
79 if (retval != ERROR_OK)
80 return retval;
81 if (break_status & 0x1f) {
82 /* we have halted on a breakpoint */
83 retval = target_write_u32(target,
84 ejtag_info->ejtag_dbs_addr, 0);
85 if (retval != ERROR_OK)
86 return retval;
87 target->debug_reason = DBG_REASON_WATCHPOINT;
88 }
89 }
90 }
91
92 return ERROR_OK;
93 }
94
95 static int mips_m4k_debug_entry(struct target *target)
96 {
97 struct mips32_common *mips32 = target_to_mips32(target);
98 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
99
100 mips32_save_context(target);
101
102 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
103 mips_ejtag_config_step(ejtag_info, 0);
104
105 /* make sure break unit configured */
106 mips32_configure_break_unit(target);
107
108 /* attempt to find halt reason */
109 mips_m4k_examine_debug_reason(target);
110
111 /* default to mips32 isa, it will be changed below if required */
112 mips32->isa_mode = MIPS32_ISA_MIPS32;
113
114 if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
115 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
116
117 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
118 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
119 target_state_name(target));
120
121 return ERROR_OK;
122 }
123
124 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
125 {
126 struct target_list *head;
127 struct target *curr;
128
129 head = target->head;
130 while (head != (struct target_list *)NULL) {
131 curr = head->target;
132 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
133 return curr;
134 head = head->next;
135 }
136 return target;
137 }
138
139 static int mips_m4k_halt_smp(struct target *target)
140 {
141 int retval = ERROR_OK;
142 struct target_list *head;
143 struct target *curr;
144 head = target->head;
145 while (head != (struct target_list *)NULL) {
146 int ret = ERROR_OK;
147 curr = head->target;
148 if ((curr != target) && (curr->state != TARGET_HALTED))
149 ret = mips_m4k_halt(curr);
150
151 if (ret != ERROR_OK) {
152 LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
153 retval = ret;
154 }
155 head = head->next;
156 }
157 return retval;
158 }
159
160 static int update_halt_gdb(struct target *target)
161 {
162 int retval = ERROR_OK;
163 if (target->gdb_service->core[0] == -1) {
164 target->gdb_service->target = target;
165 target->gdb_service->core[0] = target->coreid;
166 retval = mips_m4k_halt_smp(target);
167 }
168 return retval;
169 }
170
171 static int mips_m4k_poll(struct target *target)
172 {
173 int retval = ERROR_OK;
174 struct mips32_common *mips32 = target_to_mips32(target);
175 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
176 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
177 enum target_state prev_target_state = target->state;
178
179 /* toggle to another core is done by gdb as follow */
180 /* maint packet J core_id */
181 /* continue */
182 /* the next polling trigger an halt event sent to gdb */
183 if ((target->state == TARGET_HALTED) && (target->smp) &&
184 (target->gdb_service) &&
185 (target->gdb_service->target == NULL)) {
186 target->gdb_service->target =
187 get_mips_m4k(target, target->gdb_service->core[1]);
188 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
189 return retval;
190 }
191
192 /* read ejtag control reg */
193 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
194 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
195 if (retval != ERROR_OK)
196 return retval;
197
198 ejtag_info->isa = (ejtag_ctrl & EJTAG_CTRL_DBGISA) ? 1 : 0;
199
200 /* clear this bit before handling polling
201 * as after reset registers will read zero */
202 if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
203 /* we have detected a reset, clear flag
204 * otherwise ejtag will not work */
205 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
206
207 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
208 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
209 if (retval != ERROR_OK)
210 return retval;
211 LOG_DEBUG("Reset Detected");
212 }
213
214 /* check for processor halted */
215 if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
216 if ((target->state != TARGET_HALTED)
217 && (target->state != TARGET_DEBUG_RUNNING)) {
218 if (target->state == TARGET_UNKNOWN)
219 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
220
221 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
222 * (maybe put on by HALT-ing the board in the previous session).
223 *
224 * Force enable debug entry for this session.
225 */
226 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
227 target->state = TARGET_HALTED;
228 retval = mips_m4k_debug_entry(target);
229 if (retval != ERROR_OK)
230 return retval;
231
232 if (target->smp &&
233 ((prev_target_state == TARGET_RUNNING)
234 || (prev_target_state == TARGET_RESET))) {
235 retval = update_halt_gdb(target);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
240 } else if (target->state == TARGET_DEBUG_RUNNING) {
241 target->state = TARGET_HALTED;
242
243 retval = mips_m4k_debug_entry(target);
244 if (retval != ERROR_OK)
245 return retval;
246
247 if (target->smp) {
248 retval = update_halt_gdb(target);
249 if (retval != ERROR_OK)
250 return retval;
251 }
252
253 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
254 }
255 } else
256 target->state = TARGET_RUNNING;
257
258 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
259
260 return ERROR_OK;
261 }
262
263 static int mips_m4k_halt(struct target *target)
264 {
265 struct mips32_common *mips32 = target_to_mips32(target);
266 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
267
268 LOG_DEBUG("target->state: %s", target_state_name(target));
269
270 if (target->state == TARGET_HALTED) {
271 LOG_DEBUG("target was already halted");
272 return ERROR_OK;
273 }
274
275 if (target->state == TARGET_UNKNOWN)
276 LOG_WARNING("target was in unknown state when halt was requested");
277
278 if (target->state == TARGET_RESET) {
279 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
280 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
281 return ERROR_TARGET_FAILURE;
282 } else {
283 /* we came here in a reset_halt or reset_init sequence
284 * debug entry was already prepared in mips_m4k_assert_reset()
285 */
286 target->debug_reason = DBG_REASON_DBGRQ;
287
288 return ERROR_OK;
289 }
290 }
291
292 /* break processor */
293 mips_ejtag_enter_debug(ejtag_info);
294
295 target->debug_reason = DBG_REASON_DBGRQ;
296
297 return ERROR_OK;
298 }
299
300 static int mips_m4k_assert_reset(struct target *target)
301 {
302 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
303 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
304
305 /* TODO: apply hw reset signal in not examined state */
306 if (!(target_was_examined(target))) {
307 LOG_WARNING("Reset is not asserted because the target is not examined.");
308 LOG_WARNING("Use a reset button or power cycle the target.");
309 return ERROR_TARGET_NOT_EXAMINED;
310 }
311
312 LOG_DEBUG("target->state: %s",
313 target_state_name(target));
314
315 enum reset_types jtag_reset_config = jtag_get_reset_config();
316
317 /* some cores support connecting while srst is asserted
318 * use that mode is it has been configured */
319
320 bool srst_asserted = false;
321
322 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
323 (jtag_reset_config & RESET_SRST_NO_GATING)) {
324 jtag_add_reset(0, 1);
325 srst_asserted = true;
326 }
327
328
329 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
330 if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
331 if (target->reset_halt) {
332 /* use hardware to catch reset */
333 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
334 } else
335 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
336 }
337
338 if (jtag_reset_config & RESET_HAS_SRST) {
339 /* here we should issue a srst only, but we may have to assert trst as well */
340 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
341 jtag_add_reset(1, 1);
342 else if (!srst_asserted)
343 jtag_add_reset(0, 1);
344 } else {
345 if (mips_m4k->is_pic32mx) {
346 LOG_DEBUG("Using MTAP reset to reset processor...");
347
348 /* use microchip specific MTAP reset */
349 mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
350 mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
351
352 mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
353 mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
354 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
355 } else {
356 /* use ejtag reset - not supported by all cores */
357 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
358 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
359 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
360 mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
361 }
362 }
363
364 target->state = TARGET_RESET;
365 jtag_add_sleep(50000);
366
367 register_cache_invalidate(mips_m4k->mips32.core_cache);
368
369 if (target->reset_halt) {
370 int retval = target_halt(target);
371 if (retval != ERROR_OK)
372 return retval;
373 }
374
375 return ERROR_OK;
376 }
377
378 static int mips_m4k_deassert_reset(struct target *target)
379 {
380 LOG_DEBUG("target->state: %s", target_state_name(target));
381
382 /* deassert reset lines */
383 jtag_add_reset(0, 0);
384
385 return ERROR_OK;
386 }
387
388 static int mips_m4k_single_step_core(struct target *target)
389 {
390 struct mips32_common *mips32 = target_to_mips32(target);
391 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
392
393 /* configure single step mode */
394 mips_ejtag_config_step(ejtag_info, 1);
395
396 /* disable interrupts while stepping */
397 mips32_enable_interrupts(target, 0);
398
399 /* exit debug mode */
400 mips_ejtag_exit_debug(ejtag_info);
401
402 mips_m4k_debug_entry(target);
403
404 return ERROR_OK;
405 }
406
407 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
408 {
409 int retval = ERROR_OK;
410 struct target_list *head;
411 struct target *curr;
412
413 head = target->head;
414 while (head != (struct target_list *)NULL) {
415 int ret = ERROR_OK;
416 curr = head->target;
417 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
418 /* resume current address , not in step mode */
419 ret = mips_m4k_internal_restore(curr, 1, address,
420 handle_breakpoints, 0);
421
422 if (ret != ERROR_OK) {
423 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
424 curr->coreid, address);
425 retval = ret;
426 }
427 }
428 head = head->next;
429 }
430 return retval;
431 }
432
433 static int mips_m4k_internal_restore(struct target *target, int current,
434 uint32_t address, int handle_breakpoints, int debug_execution)
435 {
436 struct mips32_common *mips32 = target_to_mips32(target);
437 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
438 struct breakpoint *breakpoint = NULL;
439 uint32_t resume_pc;
440
441 if (target->state != TARGET_HALTED) {
442 LOG_WARNING("target not halted");
443 return ERROR_TARGET_NOT_HALTED;
444 }
445
446 if (!debug_execution) {
447 target_free_all_working_areas(target);
448 mips_m4k_enable_breakpoints(target);
449 mips_m4k_enable_watchpoints(target);
450 }
451
452 /* current = 1: continue on current pc, otherwise continue at <address> */
453 if (!current) {
454 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
455 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
456 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
457 }
458
459 if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
460 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
461
462 if (!current)
463 resume_pc = address;
464 else
465 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
466
467 mips32_restore_context(target);
468
469 /* the front-end may request us not to handle breakpoints */
470 if (handle_breakpoints) {
471 /* Single step past breakpoint at current address */
472 breakpoint = breakpoint_find(target, resume_pc);
473 if (breakpoint) {
474 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
475 breakpoint->address);
476 mips_m4k_unset_breakpoint(target, breakpoint);
477 mips_m4k_single_step_core(target);
478 mips_m4k_set_breakpoint(target, breakpoint);
479 }
480 }
481
482 /* enable interrupts if we are running */
483 mips32_enable_interrupts(target, !debug_execution);
484
485 /* exit debug mode */
486 mips_ejtag_exit_debug(ejtag_info);
487 target->debug_reason = DBG_REASON_NOTHALTED;
488
489 /* registers are now invalid */
490 register_cache_invalidate(mips32->core_cache);
491
492 if (!debug_execution) {
493 target->state = TARGET_RUNNING;
494 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
495 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
496 } else {
497 target->state = TARGET_DEBUG_RUNNING;
498 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
499 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
500 }
501
502 return ERROR_OK;
503 }
504
505 static int mips_m4k_resume(struct target *target, int current,
506 target_addr_t address, int handle_breakpoints, int debug_execution)
507 {
508 int retval = ERROR_OK;
509
510 /* dummy resume for smp toggle in order to reduce gdb impact */
511 if ((target->smp) && (target->gdb_service->core[1] != -1)) {
512 /* simulate a start and halt of target */
513 target->gdb_service->target = NULL;
514 target->gdb_service->core[0] = target->gdb_service->core[1];
515 /* fake resume at next poll we play the target core[1], see poll*/
516 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
517 return retval;
518 }
519
520 retval = mips_m4k_internal_restore(target, current, address,
521 handle_breakpoints,
522 debug_execution);
523
524 if (retval == ERROR_OK && target->smp) {
525 target->gdb_service->core[0] = -1;
526 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
527 }
528
529 return retval;
530 }
531
532 static int mips_m4k_step(struct target *target, int current,
533 target_addr_t address, int handle_breakpoints)
534 {
535 /* get pointers to arch-specific information */
536 struct mips32_common *mips32 = target_to_mips32(target);
537 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
538 struct breakpoint *breakpoint = NULL;
539
540 if (target->state != TARGET_HALTED) {
541 LOG_WARNING("target not halted");
542 return ERROR_TARGET_NOT_HALTED;
543 }
544
545 /* current = 1: continue on current pc, otherwise continue at <address> */
546 if (!current) {
547 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
548 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
549 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
550 }
551
552 /* the front-end may request us not to handle breakpoints */
553 if (handle_breakpoints) {
554 breakpoint = breakpoint_find(target,
555 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
556 if (breakpoint)
557 mips_m4k_unset_breakpoint(target, breakpoint);
558 }
559
560 /* restore context */
561 mips32_restore_context(target);
562
563 /* configure single step mode */
564 mips_ejtag_config_step(ejtag_info, 1);
565
566 target->debug_reason = DBG_REASON_SINGLESTEP;
567
568 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
569
570 /* disable interrupts while stepping */
571 mips32_enable_interrupts(target, 0);
572
573 /* exit debug mode */
574 mips_ejtag_exit_debug(ejtag_info);
575
576 /* registers are now invalid */
577 register_cache_invalidate(mips32->core_cache);
578
579 LOG_DEBUG("target stepped ");
580 mips_m4k_debug_entry(target);
581
582 if (breakpoint)
583 mips_m4k_set_breakpoint(target, breakpoint);
584
585 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
586
587 return ERROR_OK;
588 }
589
590 static void mips_m4k_enable_breakpoints(struct target *target)
591 {
592 struct breakpoint *breakpoint = target->breakpoints;
593
594 /* set any pending breakpoints */
595 while (breakpoint) {
596 if (breakpoint->set == 0)
597 mips_m4k_set_breakpoint(target, breakpoint);
598 breakpoint = breakpoint->next;
599 }
600 }
601
602 static int mips_m4k_set_breakpoint(struct target *target,
603 struct breakpoint *breakpoint)
604 {
605 struct mips32_common *mips32 = target_to_mips32(target);
606 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
607 struct mips32_comparator *comparator_list = mips32->inst_break_list;
608 int retval;
609
610 if (breakpoint->set) {
611 LOG_WARNING("breakpoint already set");
612 return ERROR_OK;
613 }
614
615 if (breakpoint->type == BKPT_HARD) {
616 int bp_num = 0;
617
618 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
619 bp_num++;
620 if (bp_num >= mips32->num_inst_bpoints) {
621 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
622 breakpoint->unique_id);
623 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
624 }
625 breakpoint->set = bp_num + 1;
626 comparator_list[bp_num].used = 1;
627 comparator_list[bp_num].bp_value = breakpoint->address;
628
629 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
630 * Warning: there is no IB ASID registers in 2.0.
631 * Do not set it! :) */
632 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
633 comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
634
635 target_write_u32(target, comparator_list[bp_num].reg_address,
636 comparator_list[bp_num].bp_value);
637 target_write_u32(target, comparator_list[bp_num].reg_address +
638 ejtag_info->ejtag_ibm_offs, 0x00000000);
639 target_write_u32(target, comparator_list[bp_num].reg_address +
640 ejtag_info->ejtag_ibc_offs, 1);
641 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
642 breakpoint->unique_id,
643 bp_num, comparator_list[bp_num].bp_value);
644 } else if (breakpoint->type == BKPT_SOFT) {
645 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
646 if (breakpoint->length == 4) {
647 uint32_t verify = 0xffffffff;
648
649 retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
650 breakpoint->orig_instr);
651 if (retval != ERROR_OK)
652 return retval;
653 retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP(ejtag_info->isa));
654 if (retval != ERROR_OK)
655 return retval;
656
657 retval = target_read_u32(target, breakpoint->address, &verify);
658 if (retval != ERROR_OK)
659 return retval;
660 if (verify != MIPS32_SDBBP(ejtag_info->isa)) {
661 LOG_ERROR("Unable to set 32-bit breakpoint at address " TARGET_ADDR_FMT
662 " - check that memory is read/writable", breakpoint->address);
663 return ERROR_OK;
664 }
665 } else {
666 uint16_t verify = 0xffff;
667
668 retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
669 breakpoint->orig_instr);
670 if (retval != ERROR_OK)
671 return retval;
672 retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP(ejtag_info->isa));
673 if (retval != ERROR_OK)
674 return retval;
675
676 retval = target_read_u16(target, breakpoint->address, &verify);
677 if (retval != ERROR_OK)
678 return retval;
679 if (verify != MIPS16_SDBBP(ejtag_info->isa)) {
680 LOG_ERROR("Unable to set 16-bit breakpoint at address " TARGET_ADDR_FMT
681 " - check that memory is read/writable", breakpoint->address);
682 return ERROR_OK;
683 }
684 }
685
686 breakpoint->set = 20; /* Any nice value but 0 */
687 }
688
689 return ERROR_OK;
690 }
691
692 static int mips_m4k_unset_breakpoint(struct target *target,
693 struct breakpoint *breakpoint)
694 {
695 /* get pointers to arch-specific information */
696 struct mips32_common *mips32 = target_to_mips32(target);
697 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
698 struct mips32_comparator *comparator_list = mips32->inst_break_list;
699 int retval;
700
701 if (!breakpoint->set) {
702 LOG_WARNING("breakpoint not set");
703 return ERROR_OK;
704 }
705
706 if (breakpoint->type == BKPT_HARD) {
707 int bp_num = breakpoint->set - 1;
708 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
709 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
710 breakpoint->unique_id);
711 return ERROR_OK;
712 }
713 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
714 breakpoint->unique_id,
715 bp_num);
716 comparator_list[bp_num].used = 0;
717 comparator_list[bp_num].bp_value = 0;
718 target_write_u32(target, comparator_list[bp_num].reg_address +
719 ejtag_info->ejtag_ibc_offs, 0);
720
721 } else {
722 /* restore original instruction (kept in target endianness) */
723 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
724 if (breakpoint->length == 4) {
725 uint32_t current_instr;
726
727 /* check that user program has not modified breakpoint instruction */
728 retval = target_read_memory(target, breakpoint->address, 4, 1,
729 (uint8_t *)&current_instr);
730 if (retval != ERROR_OK)
731 return retval;
732
733 /**
734 * target_read_memory() gets us data in _target_ endianess.
735 * If we want to use this data on the host for comparisons with some macros
736 * we must first transform it to _host_ endianess using target_buffer_get_u32().
737 */
738 current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
739
740 if (current_instr == MIPS32_SDBBP(ejtag_info->isa)) {
741 retval = target_write_memory(target, breakpoint->address, 4, 1,
742 breakpoint->orig_instr);
743 if (retval != ERROR_OK)
744 return retval;
745 }
746 } else {
747 uint16_t current_instr;
748
749 /* check that user program has not modified breakpoint instruction */
750 retval = target_read_memory(target, breakpoint->address, 2, 1,
751 (uint8_t *)&current_instr);
752 if (retval != ERROR_OK)
753 return retval;
754 current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
755 if (current_instr == MIPS16_SDBBP(ejtag_info->isa)) {
756 retval = target_write_memory(target, breakpoint->address, 2, 1,
757 breakpoint->orig_instr);
758 if (retval != ERROR_OK)
759 return retval;
760 }
761 }
762 }
763 breakpoint->set = 0;
764
765 return ERROR_OK;
766 }
767
768 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
769 {
770 struct mips32_common *mips32 = target_to_mips32(target);
771
772 if (breakpoint->type == BKPT_HARD) {
773 if (mips32->num_inst_bpoints_avail < 1) {
774 LOG_INFO("no hardware breakpoint available");
775 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
776 }
777
778 mips32->num_inst_bpoints_avail--;
779 }
780
781 return mips_m4k_set_breakpoint(target, breakpoint);
782 }
783
784 static int mips_m4k_remove_breakpoint(struct target *target,
785 struct breakpoint *breakpoint)
786 {
787 /* get pointers to arch-specific information */
788 struct mips32_common *mips32 = target_to_mips32(target);
789
790 if (target->state != TARGET_HALTED) {
791 LOG_WARNING("target not halted");
792 return ERROR_TARGET_NOT_HALTED;
793 }
794
795 if (breakpoint->set)
796 mips_m4k_unset_breakpoint(target, breakpoint);
797
798 if (breakpoint->type == BKPT_HARD)
799 mips32->num_inst_bpoints_avail++;
800
801 return ERROR_OK;
802 }
803
804 static int mips_m4k_set_watchpoint(struct target *target,
805 struct watchpoint *watchpoint)
806 {
807 struct mips32_common *mips32 = target_to_mips32(target);
808 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
809 struct mips32_comparator *comparator_list = mips32->data_break_list;
810 int wp_num = 0;
811 /*
812 * watchpoint enabled, ignore all byte lanes in value register
813 * and exclude both load and store accesses from watchpoint
814 * condition evaluation
815 */
816 int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
817 (0xff << EJTAG_DBCn_BLM_SHIFT);
818
819 if (watchpoint->set) {
820 LOG_WARNING("watchpoint already set");
821 return ERROR_OK;
822 }
823
824 while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
825 wp_num++;
826 if (wp_num >= mips32->num_data_bpoints) {
827 LOG_ERROR("Can not find free FP Comparator");
828 return ERROR_FAIL;
829 }
830
831 if (watchpoint->length != 4) {
832 LOG_ERROR("Only watchpoints of length 4 are supported");
833 return ERROR_TARGET_UNALIGNED_ACCESS;
834 }
835
836 if (watchpoint->address % 4) {
837 LOG_ERROR("Watchpoints address should be word aligned");
838 return ERROR_TARGET_UNALIGNED_ACCESS;
839 }
840
841 switch (watchpoint->rw) {
842 case WPT_READ:
843 enable &= ~EJTAG_DBCn_NOLB;
844 break;
845 case WPT_WRITE:
846 enable &= ~EJTAG_DBCn_NOSB;
847 break;
848 case WPT_ACCESS:
849 enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
850 break;
851 default:
852 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
853 }
854
855 watchpoint->set = wp_num + 1;
856 comparator_list[wp_num].used = 1;
857 comparator_list[wp_num].bp_value = watchpoint->address;
858
859 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
860 * There is as well no ASID register support. */
861 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
862 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
863 else
864 target_write_u32(target, comparator_list[wp_num].reg_address +
865 ejtag_info->ejtag_dbasid_offs, 0x00000000);
866
867 target_write_u32(target, comparator_list[wp_num].reg_address,
868 comparator_list[wp_num].bp_value);
869 target_write_u32(target, comparator_list[wp_num].reg_address +
870 ejtag_info->ejtag_dbm_offs, 0x00000000);
871
872 target_write_u32(target, comparator_list[wp_num].reg_address +
873 ejtag_info->ejtag_dbc_offs, enable);
874 /* TODO: probably this value is ignored on 2.0 */
875 target_write_u32(target, comparator_list[wp_num].reg_address +
876 ejtag_info->ejtag_dbv_offs, 0);
877 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
878
879 return ERROR_OK;
880 }
881
882 static int mips_m4k_unset_watchpoint(struct target *target,
883 struct watchpoint *watchpoint)
884 {
885 /* get pointers to arch-specific information */
886 struct mips32_common *mips32 = target_to_mips32(target);
887 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
888 struct mips32_comparator *comparator_list = mips32->data_break_list;
889
890 if (!watchpoint->set) {
891 LOG_WARNING("watchpoint not set");
892 return ERROR_OK;
893 }
894
895 int wp_num = watchpoint->set - 1;
896 if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
897 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
898 return ERROR_OK;
899 }
900 comparator_list[wp_num].used = 0;
901 comparator_list[wp_num].bp_value = 0;
902 target_write_u32(target, comparator_list[wp_num].reg_address +
903 ejtag_info->ejtag_dbc_offs, 0);
904 watchpoint->set = 0;
905
906 return ERROR_OK;
907 }
908
909 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
910 {
911 struct mips32_common *mips32 = target_to_mips32(target);
912
913 if (mips32->num_data_bpoints_avail < 1) {
914 LOG_INFO("no hardware watchpoints available");
915 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
916 }
917
918 mips32->num_data_bpoints_avail--;
919
920 mips_m4k_set_watchpoint(target, watchpoint);
921 return ERROR_OK;
922 }
923
924 static int mips_m4k_remove_watchpoint(struct target *target,
925 struct watchpoint *watchpoint)
926 {
927 /* get pointers to arch-specific information */
928 struct mips32_common *mips32 = target_to_mips32(target);
929
930 if (target->state != TARGET_HALTED) {
931 LOG_WARNING("target not halted");
932 return ERROR_TARGET_NOT_HALTED;
933 }
934
935 if (watchpoint->set)
936 mips_m4k_unset_watchpoint(target, watchpoint);
937
938 mips32->num_data_bpoints_avail++;
939
940 return ERROR_OK;
941 }
942
943 static void mips_m4k_enable_watchpoints(struct target *target)
944 {
945 struct watchpoint *watchpoint = target->watchpoints;
946
947 /* set any pending watchpoints */
948 while (watchpoint) {
949 if (watchpoint->set == 0)
950 mips_m4k_set_watchpoint(target, watchpoint);
951 watchpoint = watchpoint->next;
952 }
953 }
954
955 static int mips_m4k_read_memory(struct target *target, target_addr_t address,
956 uint32_t size, uint32_t count, uint8_t *buffer)
957 {
958 struct mips32_common *mips32 = target_to_mips32(target);
959 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
960
961 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
962 address, size, count);
963
964 if (target->state != TARGET_HALTED) {
965 LOG_WARNING("target not halted");
966 return ERROR_TARGET_NOT_HALTED;
967 }
968
969 /* sanitize arguments */
970 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
971 return ERROR_COMMAND_SYNTAX_ERROR;
972
973 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
974 return ERROR_TARGET_UNALIGNED_ACCESS;
975
976 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
977 void *t = NULL;
978
979 if (size > 1) {
980 t = malloc(count * size * sizeof(uint8_t));
981 if (t == NULL) {
982 LOG_ERROR("Out of memory");
983 return ERROR_FAIL;
984 }
985 } else
986 t = buffer;
987
988 /* if noDMA off, use DMAACC mode for memory read */
989 int retval;
990 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
991 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
992 else
993 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
994
995 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
996 /* endianness, but byte array should represent target endianness */
997 if (ERROR_OK == retval) {
998 switch (size) {
999 case 4:
1000 target_buffer_set_u32_array(target, buffer, count, t);
1001 break;
1002 case 2:
1003 target_buffer_set_u16_array(target, buffer, count, t);
1004 break;
1005 }
1006 }
1007
1008 if ((size > 1) && (t != NULL))
1009 free(t);
1010
1011 return retval;
1012 }
1013
1014 static int mips_m4k_write_memory(struct target *target, target_addr_t address,
1015 uint32_t size, uint32_t count, const uint8_t *buffer)
1016 {
1017 struct mips32_common *mips32 = target_to_mips32(target);
1018 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1019
1020 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1021 address, size, count);
1022
1023 if (target->state != TARGET_HALTED) {
1024 LOG_WARNING("target not halted");
1025 return ERROR_TARGET_NOT_HALTED;
1026 }
1027
1028 if (size == 4 && count > 32) {
1029 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1030 if (retval == ERROR_OK)
1031 return ERROR_OK;
1032 LOG_WARNING("Falling back to non-bulk write");
1033 }
1034
1035 /* sanitize arguments */
1036 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1037 return ERROR_COMMAND_SYNTAX_ERROR;
1038
1039 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1040 return ERROR_TARGET_UNALIGNED_ACCESS;
1041
1042 /** correct endianess if we have word or hword access */
1043 void *t = NULL;
1044 if (size > 1) {
1045 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1046 /* endianness, but byte array represents target endianness */
1047 t = malloc(count * size * sizeof(uint8_t));
1048 if (t == NULL) {
1049 LOG_ERROR("Out of memory");
1050 return ERROR_FAIL;
1051 }
1052
1053 switch (size) {
1054 case 4:
1055 target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1056 break;
1057 case 2:
1058 target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1059 break;
1060 }
1061 buffer = t;
1062 }
1063
1064 /* if noDMA off, use DMAACC mode for memory write */
1065 int retval;
1066 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1067 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1068 else
1069 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1070
1071 if (t != NULL)
1072 free(t);
1073
1074 if (ERROR_OK != retval)
1075 return retval;
1076
1077 return ERROR_OK;
1078 }
1079
1080 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1081 struct target *target)
1082 {
1083 mips32_build_reg_cache(target);
1084
1085 return ERROR_OK;
1086 }
1087
1088 static int mips_m4k_init_arch_info(struct target *target,
1089 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1090 {
1091 struct mips32_common *mips32 = &mips_m4k->mips32;
1092
1093 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1094
1095 /* initialize mips4k specific info */
1096 mips32_init_arch_info(target, mips32, tap);
1097 mips32->arch_info = mips_m4k;
1098
1099 return ERROR_OK;
1100 }
1101
1102 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1103 {
1104 struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1105
1106 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1107
1108 return ERROR_OK;
1109 }
1110
1111 static int mips_m4k_examine(struct target *target)
1112 {
1113 int retval;
1114 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1115 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1116 uint32_t idcode = 0;
1117
1118 if (!target_was_examined(target)) {
1119 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1120 if (retval != ERROR_OK)
1121 return retval;
1122 ejtag_info->idcode = idcode;
1123
1124 if (((idcode >> 1) & 0x7FF) == 0x29) {
1125 /* we are using a pic32mx so select ejtag port
1126 * as it is not selected by default */
1127 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1128 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1129 mips_m4k->is_pic32mx = true;
1130 }
1131 }
1132
1133 /* init rest of ejtag interface */
1134 retval = mips_ejtag_init(ejtag_info);
1135 if (retval != ERROR_OK)
1136 return retval;
1137
1138 retval = mips32_examine(target);
1139 if (retval != ERROR_OK)
1140 return retval;
1141
1142 return ERROR_OK;
1143 }
1144
1145 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
1146 uint32_t count, const uint8_t *buffer)
1147 {
1148 struct mips32_common *mips32 = target_to_mips32(target);
1149 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1150 struct working_area *fast_data_area;
1151 int retval;
1152 int write_t = 1;
1153
1154 LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1155 address, count);
1156
1157 /* check alignment */
1158 if (address & 0x3u)
1159 return ERROR_TARGET_UNALIGNED_ACCESS;
1160
1161 if (mips32->fast_data_area == NULL) {
1162 /* Get memory for block write handler
1163 * we preserve this area between calls and gain a speed increase
1164 * of about 3kb/sec when writing flash
1165 * this will be released/nulled by the system when the target is resumed or reset */
1166 retval = target_alloc_working_area(target,
1167 MIPS32_FASTDATA_HANDLER_SIZE,
1168 &mips32->fast_data_area);
1169 if (retval != ERROR_OK) {
1170 LOG_ERROR("No working area available");
1171 return retval;
1172 }
1173
1174 /* reset fastadata state so the algo get reloaded */
1175 ejtag_info->fast_access_save = -1;
1176 }
1177
1178 fast_data_area = mips32->fast_data_area;
1179
1180 if (address <= fast_data_area->address + fast_data_area->size &&
1181 fast_data_area->address <= address + count) {
1182 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
1183 "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1184 fast_data_area->address, address, address + count);
1185 LOG_ERROR("Change work-area-phys or load_image address!");
1186 return ERROR_FAIL;
1187 }
1188
1189 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1190 /* but byte array represents target endianness */
1191 uint32_t *t = NULL;
1192 t = malloc(count * sizeof(uint32_t));
1193 if (t == NULL) {
1194 LOG_ERROR("Out of memory");
1195 return ERROR_FAIL;
1196 }
1197
1198 target_buffer_get_u32_array(target, buffer, count, t);
1199
1200 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1201 count, t);
1202
1203 if (t != NULL)
1204 free(t);
1205
1206 if (retval != ERROR_OK)
1207 LOG_ERROR("Fastdata access Failed");
1208
1209 return retval;
1210 }
1211
1212 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1213 struct mips_m4k_common *mips_m4k)
1214 {
1215 if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1216 command_print(cmd_ctx, "target is not an MIPS_M4K");
1217 return ERROR_TARGET_INVALID;
1218 }
1219 return ERROR_OK;
1220 }
1221
1222 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1223 {
1224 int retval;
1225 struct target *target = get_current_target(CMD_CTX);
1226 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1227 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1228
1229 retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1230 if (retval != ERROR_OK)
1231 return retval;
1232
1233 if (target->state != TARGET_HALTED) {
1234 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1235 return ERROR_OK;
1236 }
1237
1238 /* two or more argument, access a single register/select (write if third argument is given) */
1239 if (CMD_ARGC < 2)
1240 return ERROR_COMMAND_SYNTAX_ERROR;
1241 else {
1242 uint32_t cp0_reg, cp0_sel;
1243 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1244 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1245
1246 if (CMD_ARGC == 2) {
1247 uint32_t value;
1248 retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1249 if (retval != ERROR_OK) {
1250 command_print(CMD_CTX,
1251 "couldn't access reg %" PRIi32,
1252 cp0_reg);
1253 return ERROR_OK;
1254 }
1255 command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1256 cp0_reg, cp0_sel, value);
1257
1258 } else if (CMD_ARGC == 3) {
1259 uint32_t value;
1260 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1261 retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1262 if (retval != ERROR_OK) {
1263 command_print(CMD_CTX,
1264 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1265 cp0_reg, cp0_sel);
1266 return ERROR_OK;
1267 }
1268 command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1269 cp0_reg, cp0_sel, value);
1270 }
1271 }
1272
1273 return ERROR_OK;
1274 }
1275
1276 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1277 {
1278 struct target *target = get_current_target(CMD_CTX);
1279 /* check target is an smp target */
1280 struct target_list *head;
1281 struct target *curr;
1282 head = target->head;
1283 target->smp = 0;
1284 if (head != (struct target_list *)NULL) {
1285 while (head != (struct target_list *)NULL) {
1286 curr = head->target;
1287 curr->smp = 0;
1288 head = head->next;
1289 }
1290 /* fixes the target display to the debugger */
1291 target->gdb_service->target = target;
1292 }
1293 return ERROR_OK;
1294 }
1295
1296 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1297 {
1298 struct target *target = get_current_target(CMD_CTX);
1299 struct target_list *head;
1300 struct target *curr;
1301 head = target->head;
1302 if (head != (struct target_list *)NULL) {
1303 target->smp = 1;
1304 while (head != (struct target_list *)NULL) {
1305 curr = head->target;
1306 curr->smp = 1;
1307 head = head->next;
1308 }
1309 }
1310 return ERROR_OK;
1311 }
1312
1313 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1314 {
1315 struct target *target = get_current_target(CMD_CTX);
1316 int retval = ERROR_OK;
1317 struct target_list *head;
1318 head = target->head;
1319 if (head != (struct target_list *)NULL) {
1320 if (CMD_ARGC == 1) {
1321 int coreid = 0;
1322 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1323 if (ERROR_OK != retval)
1324 return retval;
1325 target->gdb_service->core[1] = coreid;
1326
1327 }
1328 command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
1329 , target->gdb_service->core[1]);
1330 }
1331 return ERROR_OK;
1332 }
1333
1334 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1335 {
1336 struct target *target = get_current_target(CMD_CTX);
1337 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1338 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1339
1340 if (CMD_ARGC == 1)
1341 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1342 else if (CMD_ARGC > 1)
1343 return ERROR_COMMAND_SYNTAX_ERROR;
1344
1345 command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1346 if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
1347 ejtag_info->mode = 0;
1348 command_print(CMD_CTX, "running in legacy mode");
1349 } else {
1350 ejtag_info->mode = 1;
1351 command_print(CMD_CTX, "running in fast queued mode");
1352 }
1353
1354 return ERROR_OK;
1355 }
1356
1357 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1358 {
1359 .name = "cp0",
1360 .handler = mips_m4k_handle_cp0_command,
1361 .mode = COMMAND_EXEC,
1362 .usage = "regnum [value]",
1363 .help = "display/modify cp0 register",
1364 },
1365 {
1366 .name = "smp_off",
1367 .handler = mips_m4k_handle_smp_off_command,
1368 .mode = COMMAND_EXEC,
1369 .help = "Stop smp handling",
1370 .usage = "",},
1371
1372 {
1373 .name = "smp_on",
1374 .handler = mips_m4k_handle_smp_on_command,
1375 .mode = COMMAND_EXEC,
1376 .help = "Restart smp handling",
1377 .usage = "",
1378 },
1379 {
1380 .name = "smp_gdb",
1381 .handler = mips_m4k_handle_smp_gdb_command,
1382 .mode = COMMAND_EXEC,
1383 .help = "display/fix current core played to gdb",
1384 .usage = "",
1385 },
1386 {
1387 .name = "scan_delay",
1388 .handler = mips_m4k_handle_scan_delay_command,
1389 .mode = COMMAND_ANY,
1390 .help = "display/set scan delay in nano seconds",
1391 .usage = "[value]",
1392 },
1393 COMMAND_REGISTRATION_DONE
1394 };
1395
1396 const struct command_registration mips_m4k_command_handlers[] = {
1397 {
1398 .chain = mips32_command_handlers,
1399 },
1400 {
1401 .name = "mips_m4k",
1402 .mode = COMMAND_ANY,
1403 .help = "mips_m4k command group",
1404 .usage = "",
1405 .chain = mips_m4k_exec_command_handlers,
1406 },
1407 COMMAND_REGISTRATION_DONE
1408 };
1409
1410 struct target_type mips_m4k_target = {
1411 .name = "mips_m4k",
1412
1413 .poll = mips_m4k_poll,
1414 .arch_state = mips32_arch_state,
1415
1416 .halt = mips_m4k_halt,
1417 .resume = mips_m4k_resume,
1418 .step = mips_m4k_step,
1419
1420 .assert_reset = mips_m4k_assert_reset,
1421 .deassert_reset = mips_m4k_deassert_reset,
1422
1423 .get_gdb_reg_list = mips32_get_gdb_reg_list,
1424
1425 .read_memory = mips_m4k_read_memory,
1426 .write_memory = mips_m4k_write_memory,
1427 .checksum_memory = mips32_checksum_memory,
1428 .blank_check_memory = mips32_blank_check_memory,
1429
1430 .run_algorithm = mips32_run_algorithm,
1431
1432 .add_breakpoint = mips_m4k_add_breakpoint,
1433 .remove_breakpoint = mips_m4k_remove_breakpoint,
1434 .add_watchpoint = mips_m4k_add_watchpoint,
1435 .remove_watchpoint = mips_m4k_remove_watchpoint,
1436
1437 .commands = mips_m4k_command_handlers,
1438 .target_create = mips_m4k_target_create,
1439 .init_target = mips_m4k_init_target,
1440 .examine = mips_m4k_examine,
1441 };
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