1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include <helper/log.h>
24 #include <helper/binarybuffer.h>
26 #include "nds32_aice.h"
27 #include "nds32_tlb.h"
28 #include "nds32_disassembler.h"
30 struct nds32_edm_operation nds32_edm_ops
[NDS32_EDM_OPERATION_MAX_NUM
];
31 uint32_t nds32_edm_ops_num
;
33 const char *nds32_debug_type_name
[11] = {
36 "HARDWARE BREAKPOINT",
37 "DATA ADDR WATCHPOINT PRECISE",
38 "DATA VALUE WATCHPOINT PRECISE",
39 "DATA VALUE WATCHPOINT IMPRECISE",
41 "HARDWARE SINGLE STEP",
42 "DATA ADDR WATCHPOINT NEXT PRECISE",
43 "DATA VALUE WATCHPOINT NEXT PRECISE",
44 "LOAD STORE GLOBAL STOP",
47 static const int nds32_lm_size_table
[16] = {
61 static const int nds32_line_size_table
[6] = {
70 static int nds32_get_core_reg(struct reg
*reg
)
73 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
74 struct target
*target
= reg_arch_info
->target
;
75 struct nds32
*nds32
= target_to_nds32(target
);
76 struct aice_port_s
*aice
= target_to_aice(target
);
78 if (target
->state
!= TARGET_HALTED
) {
79 LOG_ERROR("Target not halted");
80 return ERROR_TARGET_NOT_HALTED
;
84 uint32_t val
= buf_get_u32(reg_arch_info
->value
, 0, 32);
85 LOG_DEBUG("reading register(cached) %" PRIi32
"(%s), value: 0x%8.8" PRIx32
,
86 reg_arch_info
->num
, reg
->name
, val
);
90 int mapped_regnum
= nds32
->register_map(nds32
, reg_arch_info
->num
);
92 if (reg_arch_info
->enable
== false) {
93 buf_set_u32(reg_arch_info
->value
, 0, 32, NDS32_REGISTER_DISABLE
);
97 if ((nds32
->fpu_enable
== false)
98 && (nds32_reg_type(mapped_regnum
) == NDS32_REG_TYPE_FPU
)) {
100 } else if ((nds32
->audio_enable
== false)
101 && (nds32_reg_type(mapped_regnum
) == NDS32_REG_TYPE_AUMR
)) {
104 retval
= aice_read_register(aice
, mapped_regnum
, &val
);
106 buf_set_u32(reg_arch_info
->value
, 0, 32, val
);
108 LOG_DEBUG("reading register %" PRIi32
"(%s), value: 0x%8.8" PRIx32
,
109 reg_arch_info
->num
, reg
->name
, val
);
112 if (retval
== ERROR_OK
) {
120 static int nds32_get_core_reg_64(struct reg
*reg
)
123 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
124 struct target
*target
= reg_arch_info
->target
;
125 struct nds32
*nds32
= target_to_nds32(target
);
126 struct aice_port_s
*aice
= target_to_aice(target
);
128 if (target
->state
!= TARGET_HALTED
) {
129 LOG_ERROR("Target not halted");
130 return ERROR_TARGET_NOT_HALTED
;
136 if (reg_arch_info
->enable
== false) {
137 buf_set_u64(reg_arch_info
->value
, 0, 64, NDS32_REGISTER_DISABLE
);
141 if ((nds32
->fpu_enable
== false)
142 && ((reg_arch_info
->num
>= FD0
) && (reg_arch_info
->num
<= FD31
))) {
145 retval
= aice_read_reg_64(aice
, reg_arch_info
->num
, &val
);
147 buf_set_u64(reg_arch_info
->value
, 0, 64, val
);
150 if (retval
== ERROR_OK
) {
158 static int nds32_update_psw(struct nds32
*nds32
)
161 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
163 nds32_get_mapped_reg(nds32
, IR0
, &value_ir0
);
165 /* Save data memory endian */
166 if ((value_ir0
>> 5) & 0x1) {
167 nds32
->data_endian
= TARGET_BIG_ENDIAN
;
168 aice_set_data_endian(aice
, AICE_BIG_ENDIAN
);
170 nds32
->data_endian
= TARGET_LITTLE_ENDIAN
;
171 aice_set_data_endian(aice
, AICE_LITTLE_ENDIAN
);
174 /* Save translation status */
175 nds32
->memory
.address_translation
= ((value_ir0
>> 7) & 0x1) ? true : false;
180 static int nds32_update_mmu_info(struct nds32
*nds32
)
184 /* Update MMU control status */
185 nds32_get_mapped_reg(nds32
, MR0
, &value
);
186 nds32
->mmu_config
.default_min_page_size
= value
& 0x1;
187 nds32
->mmu_config
.multiple_page_size_in_use
= (value
>> 10) & 0x1;
192 static int nds32_update_cache_info(struct nds32
*nds32
)
196 if (nds32_get_mapped_reg(nds32
, MR8
, &value
) == ERROR_OK
) {
198 nds32
->memory
.icache
.enable
= true;
200 nds32
->memory
.icache
.enable
= false;
203 nds32
->memory
.dcache
.enable
= true;
205 nds32
->memory
.dcache
.enable
= false;
207 nds32
->memory
.icache
.enable
= false;
208 nds32
->memory
.dcache
.enable
= false;
214 static int nds32_update_lm_info(struct nds32
*nds32
)
216 struct nds32_memory
*memory
= &(nds32
->memory
);
220 nds32_get_mapped_reg(nds32
, MR6
, &value_mr6
);
222 memory
->ilm_enable
= true;
224 memory
->ilm_enable
= false;
226 if (memory
->ilm_align_ver
== 0) { /* 1MB aligned */
227 memory
->ilm_start
= value_mr6
& 0xFFF00000;
228 memory
->ilm_end
= memory
->ilm_start
+ memory
->ilm_size
;
229 } else if (memory
->ilm_align_ver
== 1) { /* aligned to local memory size */
230 memory
->ilm_start
= value_mr6
& 0xFFFFFC00;
231 memory
->ilm_end
= memory
->ilm_start
+ memory
->ilm_size
;
233 memory
->ilm_start
= -1;
234 memory
->ilm_end
= -1;
237 nds32_get_mapped_reg(nds32
, MR7
, &value_mr7
);
239 memory
->dlm_enable
= true;
241 memory
->dlm_enable
= false;
243 if (memory
->dlm_align_ver
== 0) { /* 1MB aligned */
244 memory
->dlm_start
= value_mr7
& 0xFFF00000;
245 memory
->dlm_end
= memory
->dlm_start
+ memory
->dlm_size
;
246 } else if (memory
->dlm_align_ver
== 1) { /* aligned to local memory size */
247 memory
->dlm_start
= value_mr7
& 0xFFFFFC00;
248 memory
->dlm_end
= memory
->dlm_start
+ memory
->dlm_size
;
250 memory
->dlm_start
= -1;
251 memory
->dlm_end
= -1;
258 * If fpu/audio is disabled, to access fpu/audio registers will cause
259 * exceptions. So, we need to check if fpu/audio is enabled or not as
260 * target is halted. If fpu/audio is disabled, as users access fpu/audio
261 * registers, OpenOCD will return fake value 0 instead of accessing
262 * registers through DIM.
264 static int nds32_check_extension(struct nds32
*nds32
)
268 nds32_get_mapped_reg(nds32
, FUCPR
, &value
);
269 if (value
== NDS32_REGISTER_DISABLE
) {
270 nds32
->fpu_enable
= false;
271 nds32
->audio_enable
= false;
276 nds32
->fpu_enable
= true;
278 nds32
->fpu_enable
= false;
280 if (value
& 0x80000000)
281 nds32
->audio_enable
= true;
283 nds32
->audio_enable
= false;
288 static int nds32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
290 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
291 struct target
*target
= reg_arch_info
->target
;
292 struct nds32
*nds32
= target_to_nds32(target
);
293 struct aice_port_s
*aice
= target_to_aice(target
);
294 uint32_t value
= buf_get_u32(buf
, 0, 32);
296 if (target
->state
!= TARGET_HALTED
) {
297 LOG_ERROR("Target not halted");
298 return ERROR_TARGET_NOT_HALTED
;
301 int mapped_regnum
= nds32
->register_map(nds32
, reg_arch_info
->num
);
303 /* ignore values that will generate exception */
304 if (nds32_reg_exception(mapped_regnum
, value
))
307 LOG_DEBUG("writing register %" PRIi32
"(%s) with value 0x%8.8" PRIx32
,
308 reg_arch_info
->num
, reg
->name
, value
);
310 if ((nds32
->fpu_enable
== false) &&
311 (nds32_reg_type(mapped_regnum
) == NDS32_REG_TYPE_FPU
)) {
313 buf_set_u32(reg
->value
, 0, 32, 0);
314 } else if ((nds32
->audio_enable
== false) &&
315 (nds32_reg_type(mapped_regnum
) == NDS32_REG_TYPE_AUMR
)) {
317 buf_set_u32(reg
->value
, 0, 32, 0);
319 buf_set_u32(reg
->value
, 0, 32, value
);
320 uint32_t val
= buf_get_u32(reg_arch_info
->value
, 0, 32);
321 aice_write_register(aice
, mapped_regnum
, val
);
323 /* After set value to registers, read the value from target
324 * to avoid W1C inconsistency. */
325 aice_read_register(aice
, mapped_regnum
, &val
);
326 buf_set_u32(reg_arch_info
->value
, 0, 32, val
);
332 /* update registers to take effect right now */
333 if (mapped_regnum
== IR0
) {
334 nds32_update_psw(nds32
);
335 } else if (mapped_regnum
== MR0
) {
336 nds32_update_mmu_info(nds32
);
337 } else if ((mapped_regnum
== MR6
) || (mapped_regnum
== MR7
)) {
338 /* update lm information */
339 nds32_update_lm_info(nds32
);
340 } else if (mapped_regnum
== MR8
) {
341 nds32_update_cache_info(nds32
);
342 } else if (mapped_regnum
== FUCPR
) {
343 /* update audio/fpu setting */
344 nds32_check_extension(nds32
);
350 static int nds32_set_core_reg_64(struct reg
*reg
, uint8_t *buf
)
352 struct nds32_reg
*reg_arch_info
= reg
->arch_info
;
353 struct target
*target
= reg_arch_info
->target
;
354 struct nds32
*nds32
= target_to_nds32(target
);
355 uint32_t low_part
= buf_get_u32(buf
, 0, 32);
356 uint32_t high_part
= buf_get_u32(buf
, 32, 32);
358 if (target
->state
!= TARGET_HALTED
) {
359 LOG_ERROR("Target not halted");
360 return ERROR_TARGET_NOT_HALTED
;
363 if ((nds32
->fpu_enable
== false) &&
364 ((reg_arch_info
->num
>= FD0
) && (reg_arch_info
->num
<= FD31
))) {
366 buf_set_u32(reg
->value
, 0, 32, 0);
367 buf_set_u32(reg
->value
, 32, 32, 0);
372 buf_set_u32(reg
->value
, 0, 32, low_part
);
373 buf_set_u32(reg
->value
, 32, 32, high_part
);
382 static const struct reg_arch_type nds32_reg_access_type
= {
383 .get
= nds32_get_core_reg
,
384 .set
= nds32_set_core_reg
,
387 static const struct reg_arch_type nds32_reg_access_type_64
= {
388 .get
= nds32_get_core_reg_64
,
389 .set
= nds32_set_core_reg_64
,
392 static struct reg_cache
*nds32_build_reg_cache(struct target
*target
,
395 struct reg_cache
*cache
= calloc(sizeof(struct reg_cache
), 1);
396 struct reg
*reg_list
= calloc(TOTAL_REG_NUM
, sizeof(struct reg
));
397 struct nds32_reg
*reg_arch_info
= calloc(TOTAL_REG_NUM
, sizeof(struct nds32_reg
));
400 if (!cache
|| !reg_list
|| !reg_arch_info
) {
407 cache
->name
= "Andes registers";
409 cache
->reg_list
= reg_list
;
412 for (i
= 0; i
< TOTAL_REG_NUM
; i
++) {
413 reg_arch_info
[i
].num
= i
;
414 reg_arch_info
[i
].target
= target
;
415 reg_arch_info
[i
].nds32
= nds32
;
416 reg_arch_info
[i
].enable
= false;
418 reg_list
[i
].name
= nds32_reg_simple_name(i
);
419 reg_list
[i
].number
= reg_arch_info
[i
].num
;
420 reg_list
[i
].size
= nds32_reg_size(i
);
421 reg_list
[i
].arch_info
= ®_arch_info
[i
];
423 reg_list
[i
].reg_data_type
= calloc(sizeof(struct reg_data_type
), 1);
425 if (reg_arch_info
[i
].num
>= FD0
&& reg_arch_info
[i
].num
<= FD31
) {
426 reg_list
[i
].value
= reg_arch_info
[i
].value
;
427 reg_list
[i
].type
= &nds32_reg_access_type_64
;
429 reg_list
[i
].reg_data_type
->type
= REG_TYPE_IEEE_DOUBLE
;
430 reg_list
[i
].reg_data_type
->id
= "ieee_double";
431 reg_list
[i
].group
= "float";
433 reg_list
[i
].value
= reg_arch_info
[i
].value
;
434 reg_list
[i
].type
= &nds32_reg_access_type
;
435 reg_list
[i
].group
= "general";
437 if ((reg_arch_info
[i
].num
>= FS0
) && (reg_arch_info
[i
].num
<= FS31
)) {
438 reg_list
[i
].reg_data_type
->type
= REG_TYPE_IEEE_SINGLE
;
439 reg_list
[i
].reg_data_type
->id
= "ieee_single";
440 reg_list
[i
].group
= "float";
441 } else if ((reg_arch_info
[i
].num
== FPCSR
) ||
442 (reg_arch_info
[i
].num
== FPCFG
)) {
443 reg_list
[i
].group
= "float";
444 } else if ((reg_arch_info
[i
].num
== R28
) ||
445 (reg_arch_info
[i
].num
== R29
) ||
446 (reg_arch_info
[i
].num
== R31
)) {
447 reg_list
[i
].reg_data_type
->type
= REG_TYPE_DATA_PTR
;
448 reg_list
[i
].reg_data_type
->id
= "data_ptr";
449 } else if ((reg_arch_info
[i
].num
== R30
) ||
450 (reg_arch_info
[i
].num
== PC
)) {
451 reg_list
[i
].reg_data_type
->type
= REG_TYPE_CODE_PTR
;
452 reg_list
[i
].reg_data_type
->id
= "code_ptr";
454 reg_list
[i
].reg_data_type
->type
= REG_TYPE_UINT32
;
455 reg_list
[i
].reg_data_type
->id
= "uint32";
459 if (reg_arch_info
[i
].num
>= R16
&& reg_arch_info
[i
].num
<= R25
)
460 reg_list
[i
].caller_save
= true;
462 reg_list
[i
].caller_save
= false;
464 reg_list
[i
].feature
= malloc(sizeof(struct reg_feature
));
466 if (reg_arch_info
[i
].num
>= R0
&& reg_arch_info
[i
].num
<= IFC_LP
)
467 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.core";
468 else if (reg_arch_info
[i
].num
>= CR0
&& reg_arch_info
[i
].num
<= SECUR0
)
469 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.system";
470 else if (reg_arch_info
[i
].num
>= D0L24
&& reg_arch_info
[i
].num
<= CBE3
)
471 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.audio";
472 else if (reg_arch_info
[i
].num
>= FPCSR
&& reg_arch_info
[i
].num
<= FD31
)
473 reg_list
[i
].feature
->name
= "org.gnu.gdb.nds32.fpu";
478 nds32
->core_cache
= cache
;
483 static int nds32_reg_cache_init(struct target
*target
, struct nds32
*nds32
)
485 struct reg_cache
*cache
;
487 cache
= nds32_build_reg_cache(target
, nds32
);
491 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
496 static struct reg
*nds32_reg_current(struct nds32
*nds32
, unsigned regnum
)
500 r
= nds32
->core_cache
->reg_list
+ regnum
;
505 int nds32_full_context(struct nds32
*nds32
)
507 uint32_t value
, value_ir0
;
509 /* save $pc & $psw */
510 nds32_get_mapped_reg(nds32
, PC
, &value
);
511 nds32_get_mapped_reg(nds32
, IR0
, &value_ir0
);
513 nds32_update_psw(nds32
);
514 nds32_update_mmu_info(nds32
);
515 nds32_update_cache_info(nds32
);
516 nds32_update_lm_info(nds32
);
518 nds32_check_extension(nds32
);
523 /* get register value internally */
524 int nds32_get_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t *value
)
526 struct reg_cache
*reg_cache
= nds32
->core_cache
;
529 if (regnum
> reg_cache
->num_regs
)
532 r
= nds32_reg_current(nds32
, regnum
);
534 if (r
->type
->get(r
) != ERROR_OK
)
537 *value
= buf_get_u32(r
->value
, 0, 32);
542 /** set register internally */
543 int nds32_set_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t value
)
545 struct reg_cache
*reg_cache
= nds32
->core_cache
;
547 uint8_t set_value
[4];
549 if (regnum
> reg_cache
->num_regs
)
552 r
= nds32_reg_current(nds32
, regnum
);
554 buf_set_u32(set_value
, 0, 32, value
);
556 return r
->type
->set(r
, set_value
);
559 /** get general register list */
560 static int nds32_get_general_reg_list(struct nds32
*nds32
,
561 struct reg
**reg_list
[], int *reg_list_size
)
563 struct reg
*reg_current
;
567 /** freed in gdb_server.c */
568 *reg_list
= malloc(sizeof(struct reg
*) * (IFC_LP
- R0
+ 1));
571 for (i
= R0
; i
< IFC_LP
+ 1; i
++) {
572 reg_current
= nds32_reg_current(nds32
, i
);
573 if (((struct nds32_reg
*)reg_current
->arch_info
)->enable
) {
574 (*reg_list
)[current_idx
] = reg_current
;
578 *reg_list_size
= current_idx
;
583 /** get all register list */
584 static int nds32_get_all_reg_list(struct nds32
*nds32
,
585 struct reg
**reg_list
[], int *reg_list_size
)
587 struct reg_cache
*reg_cache
= nds32
->core_cache
;
588 struct reg
*reg_current
;
591 *reg_list_size
= reg_cache
->num_regs
;
593 /** freed in gdb_server.c */
594 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
596 for (i
= 0; i
< reg_cache
->num_regs
; i
++) {
597 reg_current
= nds32_reg_current(nds32
, i
);
598 reg_current
->exist
= ((struct nds32_reg
*)
599 reg_current
->arch_info
)->enable
;
600 (*reg_list
)[i
] = reg_current
;
606 /** get all register list */
607 int nds32_get_gdb_reg_list(struct target
*target
,
608 struct reg
**reg_list
[], int *reg_list_size
,
609 enum target_register_class reg_class
)
611 struct nds32
*nds32
= target_to_nds32(target
);
615 return nds32_get_all_reg_list(nds32
, reg_list
, reg_list_size
);
616 case REG_CLASS_GENERAL
:
617 return nds32_get_general_reg_list(nds32
, reg_list
, reg_list_size
);
625 static int nds32_select_memory_mode(struct target
*target
, uint32_t address
,
626 uint32_t length
, uint32_t *end_address
)
628 struct nds32
*nds32
= target_to_nds32(target
);
629 struct aice_port_s
*aice
= target_to_aice(target
);
630 struct nds32_memory
*memory
= &(nds32
->memory
);
631 struct nds32_edm
*edm
= &(nds32
->edm
);
632 uint32_t dlm_start
, dlm_end
;
633 uint32_t ilm_start
, ilm_end
;
634 uint32_t address_end
= address
+ length
;
636 /* init end_address */
637 *end_address
= address_end
;
639 if (memory
->access_channel
== NDS_MEMORY_ACC_CPU
)
642 if (edm
->access_control
== false) {
643 LOG_DEBUG("EDM does not support ACC_CTL");
647 if (edm
->direct_access_local_memory
== false) {
648 LOG_DEBUG("EDM does not support DALM");
649 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
653 if (memory
->mode
!= NDS_MEMORY_SELECT_AUTO
) {
654 LOG_DEBUG("Memory mode is not AUTO");
658 /* set default mode */
659 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
661 if ((memory
->ilm_base
!= 0) && (memory
->ilm_enable
== true)) {
662 ilm_start
= memory
->ilm_start
;
663 ilm_end
= memory
->ilm_end
;
665 /* case 1, address < ilm_start */
666 if (address
< ilm_start
) {
667 if (ilm_start
< address_end
) {
668 /* update end_address to split non-ILM from ILM */
669 *end_address
= ilm_start
;
672 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
673 } else if ((ilm_start
<= address
) && (address
< ilm_end
)) {
674 /* case 2, ilm_start <= address < ilm_end */
675 if (ilm_end
< address_end
) {
676 /* update end_address to split non-ILM from ILM */
677 *end_address
= ilm_end
;
680 aice_memory_mode(aice
, NDS_MEMORY_SELECT_ILM
);
681 } else { /* case 3, ilm_end <= address */
683 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
688 LOG_DEBUG("ILM is not enabled");
691 if ((memory
->dlm_base
!= 0) && (memory
->dlm_enable
== true)) {
692 dlm_start
= memory
->dlm_start
;
693 dlm_end
= memory
->dlm_end
;
695 /* case 1, address < dlm_start */
696 if (address
< dlm_start
) {
697 if (dlm_start
< address_end
) {
698 /* update end_address to split non-DLM from DLM */
699 *end_address
= dlm_start
;
702 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
703 } else if ((dlm_start
<= address
) && (address
< dlm_end
)) {
704 /* case 2, dlm_start <= address < dlm_end */
705 if (dlm_end
< address_end
) {
706 /* update end_address to split non-DLM from DLM */
707 *end_address
= dlm_end
;
710 aice_memory_mode(aice
, NDS_MEMORY_SELECT_DLM
);
711 } else { /* case 3, dlm_end <= address */
713 aice_memory_mode(aice
, NDS_MEMORY_SELECT_MEM
);
718 LOG_DEBUG("DLM is not enabled");
724 int nds32_read_buffer(struct target
*target
, uint32_t address
,
725 uint32_t size
, uint8_t *buffer
)
727 struct nds32
*nds32
= target_to_nds32(target
);
728 struct nds32_memory
*memory
= &(nds32
->memory
);
730 if ((memory
->access_channel
== NDS_MEMORY_ACC_CPU
) &&
731 (target
->state
!= TARGET_HALTED
)) {
732 LOG_WARNING("target was not halted");
733 return ERROR_TARGET_NOT_HALTED
;
736 LOG_DEBUG("READ BUFFER: ADDR %08" PRIx32
" SIZE %08" PRIx32
,
740 int retval
= ERROR_OK
;
741 struct aice_port_s
*aice
= target_to_aice(target
);
742 uint32_t end_address
;
744 if (((address
% 2) == 0) && (size
== 2)) {
745 nds32_select_memory_mode(target
, address
, 2, &end_address
);
746 return aice_read_mem_unit(aice
, address
, 2, 1, buffer
);
749 /* handle unaligned head bytes */
751 uint32_t unaligned
= 4 - (address
% 4);
753 if (unaligned
> size
)
756 nds32_select_memory_mode(target
, address
, unaligned
, &end_address
);
757 retval
= aice_read_mem_unit(aice
, address
, 1, unaligned
, buffer
);
758 if (retval
!= ERROR_OK
)
762 address
+= unaligned
;
766 /* handle aligned words */
768 int aligned
= size
- (size
% 4);
772 nds32_select_memory_mode(target
, address
, aligned
, &end_address
);
774 read_len
= end_address
- address
;
777 retval
= aice_read_mem_bulk(aice
, address
, read_len
, buffer
);
779 retval
= aice_read_mem_unit(aice
, address
, 4, read_len
/ 4, buffer
);
781 if (retval
!= ERROR_OK
)
789 } while (aligned
!= 0);
792 /*prevent byte access when possible (avoid AHB access limitations in some cases)*/
794 int aligned
= size
- (size
% 2);
795 nds32_select_memory_mode(target
, address
, aligned
, &end_address
);
796 retval
= aice_read_mem_unit(aice
, address
, 2, aligned
/ 2, buffer
);
797 if (retval
!= ERROR_OK
)
804 /* handle tail writes of less than 4 bytes */
806 nds32_select_memory_mode(target
, address
, size
, &end_address
);
807 retval
= aice_read_mem_unit(aice
, address
, 1, size
, buffer
);
808 if (retval
!= ERROR_OK
)
815 int nds32_read_memory(struct target
*target
, uint32_t address
,
816 uint32_t size
, uint32_t count
, uint8_t *buffer
)
818 struct aice_port_s
*aice
= target_to_aice(target
);
820 return aice_read_mem_unit(aice
, address
, size
, count
, buffer
);
823 int nds32_read_phys_memory(struct target
*target
, target_addr_t address
,
824 uint32_t size
, uint32_t count
, uint8_t *buffer
)
826 struct aice_port_s
*aice
= target_to_aice(target
);
827 struct nds32
*nds32
= target_to_nds32(target
);
828 struct nds32_memory
*memory
= &(nds32
->memory
);
829 enum nds_memory_access orig_channel
;
832 /* switch to BUS access mode to skip MMU */
833 orig_channel
= memory
->access_channel
;
834 memory
->access_channel
= NDS_MEMORY_ACC_BUS
;
835 aice_memory_access(aice
, memory
->access_channel
);
837 /* The input address is physical address. No need to do address translation. */
838 result
= aice_read_mem_unit(aice
, address
, size
, count
, buffer
);
840 /* restore to origin access mode */
841 memory
->access_channel
= orig_channel
;
842 aice_memory_access(aice
, memory
->access_channel
);
847 int nds32_write_buffer(struct target
*target
, uint32_t address
,
848 uint32_t size
, const uint8_t *buffer
)
850 struct nds32
*nds32
= target_to_nds32(target
);
851 struct nds32_memory
*memory
= &(nds32
->memory
);
853 if ((memory
->access_channel
== NDS_MEMORY_ACC_CPU
) &&
854 (target
->state
!= TARGET_HALTED
)) {
855 LOG_WARNING("target was not halted");
856 return ERROR_TARGET_NOT_HALTED
;
859 LOG_DEBUG("WRITE BUFFER: ADDR %08" PRIx32
" SIZE %08" PRIx32
,
863 struct aice_port_s
*aice
= target_to_aice(target
);
864 int retval
= ERROR_OK
;
865 uint32_t end_address
;
867 if (((address
% 2) == 0) && (size
== 2)) {
868 nds32_select_memory_mode(target
, address
, 2, &end_address
);
869 return aice_write_mem_unit(aice
, address
, 2, 1, buffer
);
872 /* handle unaligned head bytes */
874 uint32_t unaligned
= 4 - (address
% 4);
876 if (unaligned
> size
)
879 nds32_select_memory_mode(target
, address
, unaligned
, &end_address
);
880 retval
= aice_write_mem_unit(aice
, address
, 1, unaligned
, buffer
);
881 if (retval
!= ERROR_OK
)
885 address
+= unaligned
;
889 /* handle aligned words */
891 int aligned
= size
- (size
% 4);
895 nds32_select_memory_mode(target
, address
, aligned
, &end_address
);
897 write_len
= end_address
- address
;
899 retval
= aice_write_mem_bulk(aice
, address
, write_len
, buffer
);
901 retval
= aice_write_mem_unit(aice
, address
, 4, write_len
/ 4, buffer
);
902 if (retval
!= ERROR_OK
)
906 address
+= write_len
;
908 aligned
-= write_len
;
910 } while (aligned
!= 0);
913 /* handle tail writes of less than 4 bytes */
915 nds32_select_memory_mode(target
, address
, size
, &end_address
);
916 retval
= aice_write_mem_unit(aice
, address
, 1, size
, buffer
);
917 if (retval
!= ERROR_OK
)
924 int nds32_write_memory(struct target
*target
, uint32_t address
,
925 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
927 struct aice_port_s
*aice
= target_to_aice(target
);
929 return aice_write_mem_unit(aice
, address
, size
, count
, buffer
);
932 int nds32_write_phys_memory(struct target
*target
, target_addr_t address
,
933 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
935 struct aice_port_s
*aice
= target_to_aice(target
);
936 struct nds32
*nds32
= target_to_nds32(target
);
937 struct nds32_memory
*memory
= &(nds32
->memory
);
938 enum nds_memory_access orig_channel
;
941 /* switch to BUS access mode to skip MMU */
942 orig_channel
= memory
->access_channel
;
943 memory
->access_channel
= NDS_MEMORY_ACC_BUS
;
944 aice_memory_access(aice
, memory
->access_channel
);
946 /* The input address is physical address. No need to do address translation. */
947 result
= aice_write_mem_unit(aice
, address
, size
, count
, buffer
);
949 /* restore to origin access mode */
950 memory
->access_channel
= orig_channel
;
951 aice_memory_access(aice
, memory
->access_channel
);
956 int nds32_mmu(struct target
*target
, int *enabled
)
958 if (target
->state
!= TARGET_HALTED
) {
959 LOG_ERROR("%s: target not halted", __func__
);
960 return ERROR_TARGET_INVALID
;
963 struct nds32
*nds32
= target_to_nds32(target
);
964 struct nds32_memory
*memory
= &(nds32
->memory
);
965 struct nds32_mmu_config
*mmu_config
= &(nds32
->mmu_config
);
967 if ((mmu_config
->memory_protection
== 2) && (memory
->address_translation
== true))
975 int nds32_arch_state(struct target
*target
)
977 struct nds32
*nds32
= target_to_nds32(target
);
979 if (nds32
->common_magic
!= NDS32_COMMON_MAGIC
) {
980 LOG_ERROR("BUG: called for a non-Andes target");
984 uint32_t value_pc
, value_psw
;
986 nds32_get_mapped_reg(nds32
, PC
, &value_pc
);
987 nds32_get_mapped_reg(nds32
, IR0
, &value_psw
);
989 LOG_USER("target halted due to %s\n"
990 "psw: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"%s",
991 debug_reason_name(target
),
994 nds32
->virtual_hosting
? ", virtual hosting" : "");
996 /* save pc value to pseudo register pc */
997 struct reg
*reg
= register_get_by_name(target
->reg_cache
, "pc", true);
998 buf_set_u32(reg
->value
, 0, 32, value_pc
);
1003 static void nds32_init_must_have_registers(struct nds32
*nds32
)
1005 struct reg_cache
*reg_cache
= nds32
->core_cache
;
1007 /** MUST have general registers */
1008 ((struct nds32_reg
*)reg_cache
->reg_list
[R0
].arch_info
)->enable
= true;
1009 ((struct nds32_reg
*)reg_cache
->reg_list
[R1
].arch_info
)->enable
= true;
1010 ((struct nds32_reg
*)reg_cache
->reg_list
[R2
].arch_info
)->enable
= true;
1011 ((struct nds32_reg
*)reg_cache
->reg_list
[R3
].arch_info
)->enable
= true;
1012 ((struct nds32_reg
*)reg_cache
->reg_list
[R4
].arch_info
)->enable
= true;
1013 ((struct nds32_reg
*)reg_cache
->reg_list
[R5
].arch_info
)->enable
= true;
1014 ((struct nds32_reg
*)reg_cache
->reg_list
[R6
].arch_info
)->enable
= true;
1015 ((struct nds32_reg
*)reg_cache
->reg_list
[R7
].arch_info
)->enable
= true;
1016 ((struct nds32_reg
*)reg_cache
->reg_list
[R8
].arch_info
)->enable
= true;
1017 ((struct nds32_reg
*)reg_cache
->reg_list
[R9
].arch_info
)->enable
= true;
1018 ((struct nds32_reg
*)reg_cache
->reg_list
[R10
].arch_info
)->enable
= true;
1019 ((struct nds32_reg
*)reg_cache
->reg_list
[R15
].arch_info
)->enable
= true;
1020 ((struct nds32_reg
*)reg_cache
->reg_list
[R28
].arch_info
)->enable
= true;
1021 ((struct nds32_reg
*)reg_cache
->reg_list
[R29
].arch_info
)->enable
= true;
1022 ((struct nds32_reg
*)reg_cache
->reg_list
[R30
].arch_info
)->enable
= true;
1023 ((struct nds32_reg
*)reg_cache
->reg_list
[R31
].arch_info
)->enable
= true;
1024 ((struct nds32_reg
*)reg_cache
->reg_list
[PC
].arch_info
)->enable
= true;
1026 /** MUST have configuration system registers */
1027 ((struct nds32_reg
*)reg_cache
->reg_list
[CR0
].arch_info
)->enable
= true;
1028 ((struct nds32_reg
*)reg_cache
->reg_list
[CR1
].arch_info
)->enable
= true;
1029 ((struct nds32_reg
*)reg_cache
->reg_list
[CR2
].arch_info
)->enable
= true;
1030 ((struct nds32_reg
*)reg_cache
->reg_list
[CR3
].arch_info
)->enable
= true;
1031 ((struct nds32_reg
*)reg_cache
->reg_list
[CR4
].arch_info
)->enable
= true;
1033 /** MUST have interrupt system registers */
1034 ((struct nds32_reg
*)reg_cache
->reg_list
[IR0
].arch_info
)->enable
= true;
1035 ((struct nds32_reg
*)reg_cache
->reg_list
[IR1
].arch_info
)->enable
= true;
1036 ((struct nds32_reg
*)reg_cache
->reg_list
[IR3
].arch_info
)->enable
= true;
1037 ((struct nds32_reg
*)reg_cache
->reg_list
[IR4
].arch_info
)->enable
= true;
1038 ((struct nds32_reg
*)reg_cache
->reg_list
[IR6
].arch_info
)->enable
= true;
1039 ((struct nds32_reg
*)reg_cache
->reg_list
[IR9
].arch_info
)->enable
= true;
1040 ((struct nds32_reg
*)reg_cache
->reg_list
[IR11
].arch_info
)->enable
= true;
1041 ((struct nds32_reg
*)reg_cache
->reg_list
[IR14
].arch_info
)->enable
= true;
1042 ((struct nds32_reg
*)reg_cache
->reg_list
[IR15
].arch_info
)->enable
= true;
1044 /** MUST have MMU system registers */
1045 ((struct nds32_reg
*)reg_cache
->reg_list
[MR0
].arch_info
)->enable
= true;
1047 /** MUST have EDM system registers */
1048 ((struct nds32_reg
*)reg_cache
->reg_list
[DR40
].arch_info
)->enable
= true;
1049 ((struct nds32_reg
*)reg_cache
->reg_list
[DR42
].arch_info
)->enable
= true;
1052 static int nds32_init_memory_config(struct nds32
*nds32
)
1054 uint32_t value_cr1
; /* ICM_CFG */
1055 uint32_t value_cr2
; /* DCM_CFG */
1056 struct nds32_memory
*memory
= &(nds32
->memory
);
1058 /* read $cr1 to init instruction memory information */
1059 nds32_get_mapped_reg(nds32
, CR1
, &value_cr1
);
1060 memory
->icache
.set
= value_cr1
& 0x7;
1061 memory
->icache
.way
= (value_cr1
>> 3) & 0x7;
1062 memory
->icache
.line_size
= (value_cr1
>> 6) & 0x7;
1063 memory
->icache
.lock_support
= (value_cr1
>> 9) & 0x1;
1065 memory
->ilm_base
= (value_cr1
>> 10) & 0x7;
1066 memory
->ilm_align_ver
= (value_cr1
>> 13) & 0x3;
1068 /* read $cr2 to init data memory information */
1069 nds32_get_mapped_reg(nds32
, CR2
, &value_cr2
);
1070 memory
->dcache
.set
= value_cr2
& 0x7;
1071 memory
->dcache
.way
= (value_cr2
>> 3) & 0x7;
1072 memory
->dcache
.line_size
= (value_cr2
>> 6) & 0x7;
1073 memory
->dcache
.lock_support
= (value_cr2
>> 9) & 0x1;
1075 memory
->dlm_base
= (value_cr2
>> 10) & 0x7;
1076 memory
->dlm_align_ver
= (value_cr2
>> 13) & 0x3;
1081 static void nds32_init_config(struct nds32
*nds32
)
1086 struct nds32_cpu_version
*cpu_version
= &(nds32
->cpu_version
);
1087 struct nds32_mmu_config
*mmu_config
= &(nds32
->mmu_config
);
1088 struct nds32_misc_config
*misc_config
= &(nds32
->misc_config
);
1090 nds32_get_mapped_reg(nds32
, CR0
, &value_cr0
);
1091 nds32_get_mapped_reg(nds32
, CR3
, &value_cr3
);
1092 nds32_get_mapped_reg(nds32
, CR4
, &value_cr4
);
1094 /* config cpu version */
1095 cpu_version
->performance_extension
= value_cr0
& 0x1;
1096 cpu_version
->_16bit_extension
= (value_cr0
>> 1) & 0x1;
1097 cpu_version
->performance_extension_2
= (value_cr0
>> 2) & 0x1;
1098 cpu_version
->cop_fpu_extension
= (value_cr0
>> 3) & 0x1;
1099 cpu_version
->string_extension
= (value_cr0
>> 4) & 0x1;
1100 cpu_version
->revision
= (value_cr0
>> 16) & 0xFF;
1101 cpu_version
->cpu_id_family
= (value_cr0
>> 24) & 0xF;
1102 cpu_version
->cpu_id_version
= (value_cr0
>> 28) & 0xF;
1105 mmu_config
->memory_protection
= value_cr3
& 0x3;
1106 mmu_config
->memory_protection_version
= (value_cr3
>> 2) & 0x1F;
1107 mmu_config
->fully_associative_tlb
= (value_cr3
>> 7) & 0x1;
1108 if (mmu_config
->fully_associative_tlb
) {
1109 mmu_config
->tlb_size
= (value_cr3
>> 8) & 0x7F;
1111 mmu_config
->tlb_ways
= (value_cr3
>> 8) & 0x7;
1112 mmu_config
->tlb_sets
= (value_cr3
>> 11) & 0x7;
1114 mmu_config
->_8k_page_support
= (value_cr3
>> 15) & 0x1;
1115 mmu_config
->extra_page_size_support
= (value_cr3
>> 16) & 0xFF;
1116 mmu_config
->tlb_lock
= (value_cr3
>> 24) & 0x1;
1117 mmu_config
->hardware_page_table_walker
= (value_cr3
>> 25) & 0x1;
1118 mmu_config
->default_endian
= (value_cr3
>> 26) & 0x1;
1119 mmu_config
->partition_num
= (value_cr3
>> 27) & 0x1;
1120 mmu_config
->invisible_tlb
= (value_cr3
>> 28) & 0x1;
1121 mmu_config
->vlpt
= (value_cr3
>> 29) & 0x1;
1122 mmu_config
->ntme
= (value_cr3
>> 30) & 0x1;
1123 mmu_config
->drde
= (value_cr3
>> 31) & 0x1;
1126 misc_config
->edm
= value_cr4
& 0x1;
1127 misc_config
->local_memory_dma
= (value_cr4
>> 1) & 0x1;
1128 misc_config
->performance_monitor
= (value_cr4
>> 2) & 0x1;
1129 misc_config
->high_speed_memory_port
= (value_cr4
>> 3) & 0x1;
1130 misc_config
->debug_tracer
= (value_cr4
>> 4) & 0x1;
1131 misc_config
->div_instruction
= (value_cr4
>> 5) & 0x1;
1132 misc_config
->mac_instruction
= (value_cr4
>> 6) & 0x1;
1133 misc_config
->audio_isa
= (value_cr4
>> 7) & 0x3;
1134 misc_config
->l2_cache
= (value_cr4
>> 9) & 0x1;
1135 misc_config
->reduce_register
= (value_cr4
>> 10) & 0x1;
1136 misc_config
->addr_24
= (value_cr4
>> 11) & 0x1;
1137 misc_config
->interruption_level
= (value_cr4
>> 12) & 0x1;
1138 misc_config
->baseline_instruction
= (value_cr4
>> 13) & 0x7;
1139 misc_config
->no_dx_register
= (value_cr4
>> 16) & 0x1;
1140 misc_config
->implement_dependant_register
= (value_cr4
>> 17) & 0x1;
1141 misc_config
->implement_dependant_sr_encoding
= (value_cr4
>> 18) & 0x1;
1142 misc_config
->ifc
= (value_cr4
>> 19) & 0x1;
1143 misc_config
->mcu
= (value_cr4
>> 20) & 0x1;
1144 misc_config
->shadow
= (value_cr4
>> 21) & 0x7;
1145 misc_config
->ex9
= (value_cr4
>> 24) & 0x1;
1147 nds32_init_memory_config(nds32
);
1150 static int nds32_init_option_registers(struct nds32
*nds32
)
1152 struct reg_cache
*reg_cache
= nds32
->core_cache
;
1153 struct nds32_cpu_version
*cpu_version
= &(nds32
->cpu_version
);
1154 struct nds32_mmu_config
*mmu_config
= &(nds32
->mmu_config
);
1155 struct nds32_misc_config
*misc_config
= &(nds32
->misc_config
);
1156 struct nds32_memory
*memory_config
= &(nds32
->memory
);
1162 if (((cpu_version
->cpu_id_family
== 0xC) || (cpu_version
->cpu_id_family
== 0xD)) &&
1163 ((cpu_version
->revision
& 0xFC) == 0)) {
1173 if (misc_config
->reduce_register
== false) {
1174 ((struct nds32_reg
*)reg_cache
->reg_list
[R11
].arch_info
)->enable
= true;
1175 ((struct nds32_reg
*)reg_cache
->reg_list
[R12
].arch_info
)->enable
= true;
1176 ((struct nds32_reg
*)reg_cache
->reg_list
[R13
].arch_info
)->enable
= true;
1177 ((struct nds32_reg
*)reg_cache
->reg_list
[R14
].arch_info
)->enable
= true;
1178 ((struct nds32_reg
*)reg_cache
->reg_list
[R16
].arch_info
)->enable
= true;
1179 ((struct nds32_reg
*)reg_cache
->reg_list
[R17
].arch_info
)->enable
= true;
1180 ((struct nds32_reg
*)reg_cache
->reg_list
[R18
].arch_info
)->enable
= true;
1181 ((struct nds32_reg
*)reg_cache
->reg_list
[R19
].arch_info
)->enable
= true;
1182 ((struct nds32_reg
*)reg_cache
->reg_list
[R20
].arch_info
)->enable
= true;
1183 ((struct nds32_reg
*)reg_cache
->reg_list
[R21
].arch_info
)->enable
= true;
1184 ((struct nds32_reg
*)reg_cache
->reg_list
[R22
].arch_info
)->enable
= true;
1185 ((struct nds32_reg
*)reg_cache
->reg_list
[R23
].arch_info
)->enable
= true;
1186 ((struct nds32_reg
*)reg_cache
->reg_list
[R24
].arch_info
)->enable
= true;
1187 ((struct nds32_reg
*)reg_cache
->reg_list
[R25
].arch_info
)->enable
= true;
1188 ((struct nds32_reg
*)reg_cache
->reg_list
[R26
].arch_info
)->enable
= true;
1189 ((struct nds32_reg
*)reg_cache
->reg_list
[R27
].arch_info
)->enable
= true;
1192 if (misc_config
->no_dx_register
== false) {
1193 ((struct nds32_reg
*)reg_cache
->reg_list
[D0LO
].arch_info
)->enable
= true;
1194 ((struct nds32_reg
*)reg_cache
->reg_list
[D0HI
].arch_info
)->enable
= true;
1195 ((struct nds32_reg
*)reg_cache
->reg_list
[D1LO
].arch_info
)->enable
= true;
1196 ((struct nds32_reg
*)reg_cache
->reg_list
[D1HI
].arch_info
)->enable
= true;
1199 if (misc_config
->ex9
)
1200 ((struct nds32_reg
*)reg_cache
->reg_list
[ITB
].arch_info
)->enable
= true;
1202 if (no_cr5
== false)
1203 ((struct nds32_reg
*)reg_cache
->reg_list
[CR5
].arch_info
)->enable
= true;
1205 if (cpu_version
->cop_fpu_extension
) {
1206 ((struct nds32_reg
*)reg_cache
->reg_list
[CR6
].arch_info
)->enable
= true;
1207 ((struct nds32_reg
*)reg_cache
->reg_list
[FPCSR
].arch_info
)->enable
= true;
1208 ((struct nds32_reg
*)reg_cache
->reg_list
[FPCFG
].arch_info
)->enable
= true;
1211 if (mmu_config
->memory_protection
== 1) {
1212 /* Secure MPU has no IPC, IPSW, P_ITYPE */
1213 ((struct nds32_reg
*)reg_cache
->reg_list
[IR1
].arch_info
)->enable
= false;
1214 ((struct nds32_reg
*)reg_cache
->reg_list
[IR9
].arch_info
)->enable
= false;
1217 if (nds32
->privilege_level
!= 0)
1218 ((struct nds32_reg
*)reg_cache
->reg_list
[IR3
].arch_info
)->enable
= false;
1220 if (misc_config
->mcu
== true)
1221 ((struct nds32_reg
*)reg_cache
->reg_list
[IR4
].arch_info
)->enable
= false;
1223 if (misc_config
->interruption_level
== false) {
1224 ((struct nds32_reg
*)reg_cache
->reg_list
[IR2
].arch_info
)->enable
= true;
1225 ((struct nds32_reg
*)reg_cache
->reg_list
[IR5
].arch_info
)->enable
= true;
1226 ((struct nds32_reg
*)reg_cache
->reg_list
[IR10
].arch_info
)->enable
= true;
1227 ((struct nds32_reg
*)reg_cache
->reg_list
[IR12
].arch_info
)->enable
= true;
1228 ((struct nds32_reg
*)reg_cache
->reg_list
[IR13
].arch_info
)->enable
= true;
1230 /* Secure MPU has no IPC, IPSW, P_ITYPE */
1231 if (mmu_config
->memory_protection
!= 1)
1232 ((struct nds32_reg
*)reg_cache
->reg_list
[IR7
].arch_info
)->enable
= true;
1235 if ((cpu_version
->cpu_id_family
== 0x9) ||
1236 (cpu_version
->cpu_id_family
== 0xA) ||
1237 (cpu_version
->cpu_id_family
== 0xC) ||
1238 (cpu_version
->cpu_id_family
== 0xD))
1239 ((struct nds32_reg
*)reg_cache
->reg_list
[IR8
].arch_info
)->enable
= true;
1241 if (misc_config
->shadow
== 1) {
1242 ((struct nds32_reg
*)reg_cache
->reg_list
[IR16
].arch_info
)->enable
= true;
1243 ((struct nds32_reg
*)reg_cache
->reg_list
[IR17
].arch_info
)->enable
= true;
1246 if (misc_config
->ifc
)
1247 ((struct nds32_reg
*)reg_cache
->reg_list
[IFC_LP
].arch_info
)->enable
= true;
1249 if (nds32
->privilege_level
!= 0)
1250 ((struct nds32_reg
*)reg_cache
->reg_list
[MR0
].arch_info
)->enable
= false;
1252 if (mmu_config
->memory_protection
== 1) {
1253 if (mmu_config
->memory_protection_version
== 24)
1254 ((struct nds32_reg
*)reg_cache
->reg_list
[MR4
].arch_info
)->enable
= true;
1256 if (nds32
->privilege_level
== 0) {
1257 if ((mmu_config
->memory_protection_version
== 16) ||
1258 (mmu_config
->memory_protection_version
== 24)) {
1259 ((struct nds32_reg
*)reg_cache
->reg_list
[MR11
].arch_info
)->enable
= true;
1260 ((struct nds32_reg
*)reg_cache
->reg_list
[SECUR0
].arch_info
)->enable
= true;
1261 ((struct nds32_reg
*)reg_cache
->reg_list
[IR20
].arch_info
)->enable
= true;
1262 ((struct nds32_reg
*)reg_cache
->reg_list
[IR22
].arch_info
)->enable
= true;
1263 ((struct nds32_reg
*)reg_cache
->reg_list
[IR24
].arch_info
)->enable
= true;
1264 ((struct nds32_reg
*)reg_cache
->reg_list
[IR30
].arch_info
)->enable
= true;
1266 if (misc_config
->shadow
== 1) {
1267 ((struct nds32_reg
*)reg_cache
->reg_list
[IR21
].arch_info
)->enable
= true;
1268 ((struct nds32_reg
*)reg_cache
->reg_list
[IR23
].arch_info
)->enable
= true;
1269 ((struct nds32_reg
*)reg_cache
->reg_list
[IR25
].arch_info
)->enable
= true;
1273 } else if (mmu_config
->memory_protection
== 2) {
1274 ((struct nds32_reg
*)reg_cache
->reg_list
[MR1
].arch_info
)->enable
= true;
1275 ((struct nds32_reg
*)reg_cache
->reg_list
[MR4
].arch_info
)->enable
= true;
1277 if ((cpu_version
->cpu_id_family
!= 0xA) && (cpu_version
->cpu_id_family
!= 0xC) &&
1278 (cpu_version
->cpu_id_family
!= 0xD))
1279 ((struct nds32_reg
*)reg_cache
->reg_list
[MR5
].arch_info
)->enable
= true;
1282 if (mmu_config
->memory_protection
> 0) {
1283 ((struct nds32_reg
*)reg_cache
->reg_list
[MR2
].arch_info
)->enable
= true;
1284 ((struct nds32_reg
*)reg_cache
->reg_list
[MR3
].arch_info
)->enable
= true;
1287 if (memory_config
->ilm_base
!= 0)
1288 if (nds32
->privilege_level
== 0)
1289 ((struct nds32_reg
*)reg_cache
->reg_list
[MR6
].arch_info
)->enable
= true;
1291 if (memory_config
->dlm_base
!= 0)
1292 if (nds32
->privilege_level
== 0)
1293 ((struct nds32_reg
*)reg_cache
->reg_list
[MR7
].arch_info
)->enable
= true;
1295 if ((memory_config
->icache
.line_size
!= 0) && (memory_config
->dcache
.line_size
!= 0))
1296 ((struct nds32_reg
*)reg_cache
->reg_list
[MR8
].arch_info
)->enable
= true;
1298 if (misc_config
->high_speed_memory_port
)
1299 ((struct nds32_reg
*)reg_cache
->reg_list
[MR9
].arch_info
)->enable
= true;
1302 ((struct nds32_reg
*)reg_cache
->reg_list
[MR10
].arch_info
)->enable
= true;
1304 if (misc_config
->edm
) {
1305 int dr_reg_n
= nds32
->edm
.breakpoint_num
* 5;
1307 for (int i
= 0 ; i
< dr_reg_n
; i
++)
1308 ((struct nds32_reg
*)reg_cache
->reg_list
[DR0
+ i
].arch_info
)->enable
= true;
1310 ((struct nds32_reg
*)reg_cache
->reg_list
[DR41
].arch_info
)->enable
= true;
1311 ((struct nds32_reg
*)reg_cache
->reg_list
[DR43
].arch_info
)->enable
= true;
1312 ((struct nds32_reg
*)reg_cache
->reg_list
[DR44
].arch_info
)->enable
= true;
1313 ((struct nds32_reg
*)reg_cache
->reg_list
[DR45
].arch_info
)->enable
= true;
1316 if (misc_config
->debug_tracer
) {
1317 ((struct nds32_reg
*)reg_cache
->reg_list
[DR46
].arch_info
)->enable
= true;
1318 ((struct nds32_reg
*)reg_cache
->reg_list
[DR47
].arch_info
)->enable
= true;
1321 if (misc_config
->performance_monitor
) {
1322 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR0
].arch_info
)->enable
= true;
1323 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR1
].arch_info
)->enable
= true;
1324 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR2
].arch_info
)->enable
= true;
1325 ((struct nds32_reg
*)reg_cache
->reg_list
[PFR3
].arch_info
)->enable
= true;
1328 if (misc_config
->local_memory_dma
) {
1329 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR0
].arch_info
)->enable
= true;
1330 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR1
].arch_info
)->enable
= true;
1331 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR2
].arch_info
)->enable
= true;
1332 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR3
].arch_info
)->enable
= true;
1333 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR4
].arch_info
)->enable
= true;
1334 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR5
].arch_info
)->enable
= true;
1335 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR6
].arch_info
)->enable
= true;
1336 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR7
].arch_info
)->enable
= true;
1337 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR8
].arch_info
)->enable
= true;
1338 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR9
].arch_info
)->enable
= true;
1339 ((struct nds32_reg
*)reg_cache
->reg_list
[DMAR10
].arch_info
)->enable
= true;
1342 if ((misc_config
->local_memory_dma
|| misc_config
->performance_monitor
) &&
1343 (no_racr0
== false))
1344 ((struct nds32_reg
*)reg_cache
->reg_list
[RACR
].arch_info
)->enable
= true;
1346 if (cpu_version
->cop_fpu_extension
|| (misc_config
->audio_isa
!= 0))
1347 ((struct nds32_reg
*)reg_cache
->reg_list
[FUCPR
].arch_info
)->enable
= true;
1349 if (misc_config
->audio_isa
!= 0) {
1350 if (misc_config
->audio_isa
> 1) {
1351 ((struct nds32_reg
*)reg_cache
->reg_list
[D0L24
].arch_info
)->enable
= true;
1352 ((struct nds32_reg
*)reg_cache
->reg_list
[D1L24
].arch_info
)->enable
= true;
1355 ((struct nds32_reg
*)reg_cache
->reg_list
[I0
].arch_info
)->enable
= true;
1356 ((struct nds32_reg
*)reg_cache
->reg_list
[I1
].arch_info
)->enable
= true;
1357 ((struct nds32_reg
*)reg_cache
->reg_list
[I2
].arch_info
)->enable
= true;
1358 ((struct nds32_reg
*)reg_cache
->reg_list
[I3
].arch_info
)->enable
= true;
1359 ((struct nds32_reg
*)reg_cache
->reg_list
[I4
].arch_info
)->enable
= true;
1360 ((struct nds32_reg
*)reg_cache
->reg_list
[I5
].arch_info
)->enable
= true;
1361 ((struct nds32_reg
*)reg_cache
->reg_list
[I6
].arch_info
)->enable
= true;
1362 ((struct nds32_reg
*)reg_cache
->reg_list
[I7
].arch_info
)->enable
= true;
1363 ((struct nds32_reg
*)reg_cache
->reg_list
[M1
].arch_info
)->enable
= true;
1364 ((struct nds32_reg
*)reg_cache
->reg_list
[M2
].arch_info
)->enable
= true;
1365 ((struct nds32_reg
*)reg_cache
->reg_list
[M3
].arch_info
)->enable
= true;
1366 ((struct nds32_reg
*)reg_cache
->reg_list
[M5
].arch_info
)->enable
= true;
1367 ((struct nds32_reg
*)reg_cache
->reg_list
[M6
].arch_info
)->enable
= true;
1368 ((struct nds32_reg
*)reg_cache
->reg_list
[M7
].arch_info
)->enable
= true;
1369 ((struct nds32_reg
*)reg_cache
->reg_list
[MOD
].arch_info
)->enable
= true;
1370 ((struct nds32_reg
*)reg_cache
->reg_list
[LBE
].arch_info
)->enable
= true;
1371 ((struct nds32_reg
*)reg_cache
->reg_list
[LE
].arch_info
)->enable
= true;
1372 ((struct nds32_reg
*)reg_cache
->reg_list
[LC
].arch_info
)->enable
= true;
1373 ((struct nds32_reg
*)reg_cache
->reg_list
[ADM_VBASE
].arch_info
)->enable
= true;
1374 ((struct nds32_reg
*)reg_cache
->reg_list
[SHFT_CTL0
].arch_info
)->enable
= true;
1375 ((struct nds32_reg
*)reg_cache
->reg_list
[SHFT_CTL1
].arch_info
)->enable
= true;
1378 uint32_t fucpr_backup
;
1379 /* enable fpu and get configuration */
1380 nds32_get_mapped_reg(nds32
, FUCPR
, &fucpr_backup
);
1381 if ((fucpr_backup
& 0x80000000) == 0)
1382 nds32_set_mapped_reg(nds32
, FUCPR
, fucpr_backup
| 0x80000000);
1383 nds32_get_mapped_reg(nds32
, MOD
, &value_mod
);
1384 /* restore origin fucpr value */
1385 if ((fucpr_backup
& 0x80000000) == 0)
1386 nds32_set_mapped_reg(nds32
, FUCPR
, fucpr_backup
);
1388 if ((value_mod
>> 6) & 0x1) {
1389 ((struct nds32_reg
*)reg_cache
->reg_list
[CB_CTL
].arch_info
)->enable
= true;
1390 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB0
].arch_info
)->enable
= true;
1391 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB1
].arch_info
)->enable
= true;
1392 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB2
].arch_info
)->enable
= true;
1393 ((struct nds32_reg
*)reg_cache
->reg_list
[CBB3
].arch_info
)->enable
= true;
1394 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE0
].arch_info
)->enable
= true;
1395 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE1
].arch_info
)->enable
= true;
1396 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE2
].arch_info
)->enable
= true;
1397 ((struct nds32_reg
*)reg_cache
->reg_list
[CBE3
].arch_info
)->enable
= true;
1401 if ((cpu_version
->cpu_id_family
== 0x9) ||
1402 (cpu_version
->cpu_id_family
== 0xA) ||
1403 (cpu_version
->cpu_id_family
== 0xC)) {
1405 ((struct nds32_reg
*)reg_cache
->reg_list
[IDR0
].arch_info
)->enable
= true;
1406 ((struct nds32_reg
*)reg_cache
->reg_list
[IDR1
].arch_info
)->enable
= true;
1408 if ((cpu_version
->cpu_id_family
== 0xC) && (cpu_version
->revision
== 0x0C))
1409 ((struct nds32_reg
*)reg_cache
->reg_list
[IDR0
].arch_info
)->enable
= false;
1413 uint32_t ivb_prog_pri_lvl
;
1414 uint32_t ivb_ivic_ver
;
1416 nds32_get_mapped_reg(nds32
, IR3
, &ir3_value
);
1417 ivb_prog_pri_lvl
= ir3_value
& 0x1;
1418 ivb_ivic_ver
= (ir3_value
>> 11) & 0x3;
1420 if ((ivb_prog_pri_lvl
== 1) || (ivb_ivic_ver
>= 1)) {
1421 ((struct nds32_reg
*)reg_cache
->reg_list
[IR18
].arch_info
)->enable
= true;
1422 ((struct nds32_reg
*)reg_cache
->reg_list
[IR19
].arch_info
)->enable
= true;
1425 if (ivb_ivic_ver
>= 1) {
1426 ((struct nds32_reg
*)reg_cache
->reg_list
[IR26
].arch_info
)->enable
= true;
1427 ((struct nds32_reg
*)reg_cache
->reg_list
[IR27
].arch_info
)->enable
= true;
1428 ((struct nds32_reg
*)reg_cache
->reg_list
[IR28
].arch_info
)->enable
= true;
1429 ((struct nds32_reg
*)reg_cache
->reg_list
[IR29
].arch_info
)->enable
= true;
1435 int nds32_init_register_table(struct nds32
*nds32
)
1437 nds32_init_must_have_registers(nds32
);
1442 int nds32_add_software_breakpoint(struct target
*target
,
1443 struct breakpoint
*breakpoint
)
1446 uint32_t check_data
;
1447 uint32_t break_insn
;
1449 /* check the breakpoint size */
1450 target
->type
->read_buffer(target
, breakpoint
->address
, 4, (uint8_t *)&data
);
1452 /* backup origin instruction
1453 * instruction is big-endian */
1454 if (*(char *)&data
& 0x80) { /* 16-bits instruction */
1455 breakpoint
->length
= 2;
1456 break_insn
= NDS32_BREAK_16
;
1457 } else { /* 32-bits instruction */
1458 breakpoint
->length
= 4;
1459 break_insn
= NDS32_BREAK_32
;
1462 free(breakpoint
->orig_instr
);
1464 breakpoint
->orig_instr
= malloc(breakpoint
->length
);
1465 memcpy(breakpoint
->orig_instr
, &data
, breakpoint
->length
);
1467 /* self-modified code */
1468 target
->type
->write_buffer(target
, breakpoint
->address
, breakpoint
->length
, (const uint8_t *)&break_insn
);
1469 /* write_back & invalidate dcache & invalidate icache */
1470 nds32_cache_sync(target
, breakpoint
->address
, breakpoint
->length
);
1472 /* read back to check */
1473 target
->type
->read_buffer(target
, breakpoint
->address
, breakpoint
->length
, (uint8_t *)&check_data
);
1474 if (memcmp(&check_data
, &break_insn
, breakpoint
->length
) == 0)
1480 int nds32_remove_software_breakpoint(struct target
*target
,
1481 struct breakpoint
*breakpoint
)
1483 uint32_t check_data
;
1484 uint32_t break_insn
;
1486 if (breakpoint
->length
== 2)
1487 break_insn
= NDS32_BREAK_16
;
1488 else if (breakpoint
->length
== 4)
1489 break_insn
= NDS32_BREAK_32
;
1493 target
->type
->read_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1494 (uint8_t *)&check_data
);
1496 /* break instruction is modified */
1497 if (memcmp(&check_data
, &break_insn
, breakpoint
->length
) != 0)
1500 /* self-modified code */
1501 target
->type
->write_buffer(target
, breakpoint
->address
, breakpoint
->length
,
1502 breakpoint
->orig_instr
);
1504 /* write_back & invalidate dcache & invalidate icache */
1505 nds32_cache_sync(target
, breakpoint
->address
, breakpoint
->length
);
1511 * Restore the processor context on an Andes target. The full processor
1512 * context is analyzed to see if any of the registers are dirty on this end, but
1513 * have a valid new value. If this is the case, the processor is changed to the
1514 * appropriate mode and the new register values are written out to the
1515 * processor. If there happens to be a dirty register with an invalid value, an
1516 * error will be logged.
1518 * @param target Pointer to the Andes target to have its context restored
1519 * @return Error status if the target is not halted.
1521 int nds32_restore_context(struct target
*target
)
1523 struct nds32
*nds32
= target_to_nds32(target
);
1524 struct aice_port_s
*aice
= target_to_aice(target
);
1525 struct reg_cache
*reg_cache
= nds32
->core_cache
;
1527 struct nds32_reg
*reg_arch_info
;
1532 if (target
->state
!= TARGET_HALTED
) {
1533 LOG_WARNING("target not halted");
1534 return ERROR_TARGET_NOT_HALTED
;
1537 /* check if there are dirty registers */
1538 for (i
= 0; i
< reg_cache
->num_regs
; i
++) {
1539 reg
= &(reg_cache
->reg_list
[i
]);
1540 if (reg
->dirty
== true) {
1541 if (reg
->valid
== true) {
1543 LOG_DEBUG("examining dirty reg: %s", reg
->name
);
1544 LOG_DEBUG("writing register %d with value 0x%8.8" PRIx32
,
1545 i
, buf_get_u32(reg
->value
, 0, 32));
1547 reg_arch_info
= reg
->arch_info
;
1548 if (reg_arch_info
->num
>= FD0
&& reg_arch_info
->num
<= FD31
) {
1549 uint64_t val
= buf_get_u64(reg_arch_info
->value
, 0, 64);
1550 aice_write_reg_64(aice
, reg_arch_info
->num
, val
);
1552 uint32_t val
= buf_get_u32(reg_arch_info
->value
, 0, 32);
1553 aice_write_register(aice
, reg_arch_info
->num
, val
);
1565 int nds32_edm_config(struct nds32
*nds32
)
1567 struct target
*target
= nds32
->target
;
1568 struct aice_port_s
*aice
= target_to_aice(target
);
1572 aice_read_debug_reg(aice
, NDS_EDM_SR_EDM_CFG
, &edm_cfg
);
1574 nds32
->edm
.version
= (edm_cfg
>> 16) & 0xFFFF;
1575 LOG_INFO("EDM version 0x%04x", nds32
->edm
.version
);
1577 nds32
->edm
.breakpoint_num
= (edm_cfg
& 0x7) + 1;
1579 if ((nds32
->edm
.version
& 0x1000) || (nds32
->edm
.version
>= 0x60))
1580 nds32
->edm
.access_control
= true;
1582 nds32
->edm
.access_control
= false;
1584 if ((edm_cfg
>> 4) & 0x1)
1585 nds32
->edm
.direct_access_local_memory
= true;
1587 nds32
->edm
.direct_access_local_memory
= false;
1589 if (nds32
->edm
.version
<= 0x20)
1590 nds32
->edm
.direct_access_local_memory
= false;
1592 aice_read_debug_reg(aice
, NDS_EDM_SR_EDM_CTL
, &edm_ctl
);
1593 if (edm_ctl
& (0x1 << 29))
1594 nds32
->edm
.support_max_stop
= true;
1596 nds32
->edm
.support_max_stop
= false;
1598 /* set passcode for secure MCU */
1604 int nds32_config(struct nds32
*nds32
)
1606 nds32_init_config(nds32
);
1608 /* init optional system registers according to config registers */
1609 nds32_init_option_registers(nds32
);
1611 /* get max interrupt level */
1612 if (nds32
->misc_config
.interruption_level
)
1613 nds32
->max_interrupt_level
= 2;
1615 nds32
->max_interrupt_level
= 3;
1617 /* get ILM/DLM size from MR6/MR7 */
1618 uint32_t value_mr6
, value_mr7
;
1619 uint32_t size_index
;
1620 nds32_get_mapped_reg(nds32
, MR6
, &value_mr6
);
1621 size_index
= (value_mr6
>> 1) & 0xF;
1622 nds32
->memory
.ilm_size
= nds32_lm_size_table
[size_index
];
1624 nds32_get_mapped_reg(nds32
, MR7
, &value_mr7
);
1625 size_index
= (value_mr7
>> 1) & 0xF;
1626 nds32
->memory
.dlm_size
= nds32_lm_size_table
[size_index
];
1631 int nds32_init_arch_info(struct target
*target
, struct nds32
*nds32
)
1633 target
->arch_info
= nds32
;
1634 nds32
->target
= target
;
1636 nds32
->common_magic
= NDS32_COMMON_MAGIC
;
1637 nds32
->init_arch_info_after_halted
= false;
1638 nds32
->auto_convert_hw_bp
= true;
1639 nds32
->global_stop
= false;
1640 nds32
->soft_reset_halt
= false;
1641 nds32
->edm_passcode
= NULL
;
1642 nds32
->privilege_level
= 0;
1643 nds32
->boot_time
= 1500;
1644 nds32
->reset_halt_as_examine
= false;
1645 nds32
->keep_target_edm_ctl
= false;
1646 nds32
->word_access_mem
= false;
1647 nds32
->virtual_hosting
= true;
1648 nds32
->hit_syscall
= false;
1649 nds32
->active_syscall_id
= NDS32_SYSCALL_UNDEFINED
;
1650 nds32
->virtual_hosting_errno
= 0;
1651 nds32
->virtual_hosting_ctrl_c
= false;
1652 nds32
->attached
= false;
1654 nds32
->syscall_break
.asid
= 0;
1655 nds32
->syscall_break
.length
= 4;
1656 nds32
->syscall_break
.set
= 0;
1657 nds32
->syscall_break
.orig_instr
= NULL
;
1658 nds32
->syscall_break
.next
= NULL
;
1659 nds32
->syscall_break
.unique_id
= 0x515CAll
+ target
->target_number
;
1660 nds32
->syscall_break
.linked_brp
= 0;
1664 if (nds32_reg_cache_init(target
, nds32
) == ERROR_FAIL
)
1667 if (nds32_init_register_table(nds32
) != ERROR_OK
)
1673 int nds32_virtual_to_physical(struct target
*target
, target_addr_t address
, target_addr_t
*physical
)
1675 struct nds32
*nds32
= target_to_nds32(target
);
1677 if (nds32
->memory
.address_translation
== false) {
1678 *physical
= address
;
1682 if (nds32_probe_tlb(nds32
, address
, physical
) == ERROR_OK
)
1685 if (nds32_walk_page_table(nds32
, address
, physical
) == ERROR_OK
)
1691 int nds32_cache_sync(struct target
*target
, target_addr_t address
, uint32_t length
)
1693 struct aice_port_s
*aice
= target_to_aice(target
);
1694 struct nds32
*nds32
= target_to_nds32(target
);
1695 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
1696 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
1697 uint32_t dcache_line_size
= nds32_line_size_table
[dcache
->line_size
];
1698 uint32_t icache_line_size
= nds32_line_size_table
[icache
->line_size
];
1699 uint32_t cur_address
;
1701 uint32_t start_line
, end_line
;
1704 if ((dcache
->line_size
!= 0) && (dcache
->enable
== true)) {
1705 /* address / dcache_line_size */
1706 start_line
= address
>> (dcache
->line_size
+ 2);
1707 /* (address + length - 1) / dcache_line_size */
1708 end_line
= (address
+ length
- 1) >> (dcache
->line_size
+ 2);
1710 for (cur_address
= address
, cur_line
= start_line
;
1711 cur_line
<= end_line
;
1712 cur_address
+= dcache_line_size
, cur_line
++) {
1714 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_VA_WB
, cur_address
);
1715 if (result
!= ERROR_OK
)
1719 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_VA_INVAL
, cur_address
);
1720 if (result
!= ERROR_OK
)
1725 if ((icache
->line_size
!= 0) && (icache
->enable
== true)) {
1726 /* address / icache_line_size */
1727 start_line
= address
>> (icache
->line_size
+ 2);
1728 /* (address + length - 1) / icache_line_size */
1729 end_line
= (address
+ length
- 1) >> (icache
->line_size
+ 2);
1731 for (cur_address
= address
, cur_line
= start_line
;
1732 cur_line
<= end_line
;
1733 cur_address
+= icache_line_size
, cur_line
++) {
1734 /* Because PSW.IT is turned off under debug exception, address MUST
1735 * be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide
1736 * address translation or not. */
1737 target_addr_t physical_addr
;
1738 if (target
->type
->virt2phys(target
, cur_address
, &physical_addr
) == ERROR_FAIL
)
1742 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_VA_INVAL
, physical_addr
);
1743 if (result
!= ERROR_OK
)
1751 uint32_t nds32_nextpc(struct nds32
*nds32
, int current
, uint32_t address
)
1754 nds32_set_mapped_reg(nds32
, PC
, address
);
1756 nds32_get_mapped_reg(nds32
, PC
, &address
);
1761 int nds32_step(struct target
*target
, int current
,
1762 target_addr_t address
, int handle_breakpoints
)
1764 LOG_DEBUG("target->state: %s",
1765 target_state_name(target
));
1767 if (target
->state
!= TARGET_HALTED
) {
1768 LOG_WARNING("target was not halted");
1769 return ERROR_TARGET_NOT_HALTED
;
1772 struct nds32
*nds32
= target_to_nds32(target
);
1774 address
= nds32_nextpc(nds32
, current
, address
);
1776 LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR
"%s", address
, !current
? "!" : "");
1779 uint32_t ir14_value
;
1780 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1781 if (nds32
->step_isr_enable
)
1782 ir14_value
|= (0x1 << 31);
1784 ir14_value
&= ~(0x1 << 31);
1785 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1787 /* check hit_syscall before leave_debug_state() because
1788 * leave_debug_state() may clear hit_syscall flag */
1789 bool no_step
= false;
1790 if (nds32
->hit_syscall
)
1791 /* step after hit_syscall should be ignored because
1792 * leave_debug_state will step implicitly to skip the
1796 /********* TODO: maybe create another function to handle this part */
1797 CHECK_RETVAL(nds32
->leave_debug_state(nds32
, true));
1798 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
1800 if (no_step
== false) {
1801 struct aice_port_s
*aice
= target_to_aice(target
);
1802 if (aice_step(aice
) != ERROR_OK
)
1807 CHECK_RETVAL(nds32
->enter_debug_state(nds32
, true));
1808 /********* TODO: maybe create another function to handle this part */
1811 if (nds32
->step_isr_enable
) {
1812 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1813 ir14_value
&= ~(0x1 << 31);
1814 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1817 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1822 static int nds32_step_without_watchpoint(struct nds32
*nds32
)
1824 struct target
*target
= nds32
->target
;
1826 if (target
->state
!= TARGET_HALTED
) {
1827 LOG_WARNING("target was not halted");
1828 return ERROR_TARGET_NOT_HALTED
;
1832 uint32_t ir14_value
;
1833 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1834 if (nds32
->step_isr_enable
)
1835 ir14_value
|= (0x1 << 31);
1837 ir14_value
&= ~(0x1 << 31);
1838 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1840 /********* TODO: maybe create another function to handle this part */
1841 CHECK_RETVAL(nds32
->leave_debug_state(nds32
, false));
1843 struct aice_port_s
*aice
= target_to_aice(target
);
1845 if (aice_step(aice
) != ERROR_OK
)
1849 CHECK_RETVAL(nds32
->enter_debug_state(nds32
, false));
1850 /********* TODO: maybe create another function to handle this part */
1853 if (nds32
->step_isr_enable
) {
1854 nds32_get_mapped_reg(nds32
, IR14
, &ir14_value
);
1855 ir14_value
&= ~(0x1 << 31);
1856 nds32_set_mapped_reg(nds32
, IR14
, ir14_value
);
1862 int nds32_target_state(struct nds32
*nds32
, enum target_state
*state
)
1864 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
1865 enum aice_target_state_s nds32_state
;
1867 if (aice_state(aice
, &nds32_state
) != ERROR_OK
)
1870 switch (nds32_state
) {
1871 case AICE_DISCONNECT
:
1872 LOG_INFO("USB is disconnected");
1874 case AICE_TARGET_DETACH
:
1875 LOG_INFO("Target is disconnected");
1877 case AICE_TARGET_UNKNOWN
:
1878 *state
= TARGET_UNKNOWN
;
1880 case AICE_TARGET_RUNNING
:
1881 *state
= TARGET_RUNNING
;
1883 case AICE_TARGET_HALTED
:
1884 *state
= TARGET_HALTED
;
1886 case AICE_TARGET_RESET
:
1887 *state
= TARGET_RESET
;
1889 case AICE_TARGET_DEBUG_RUNNING
:
1890 *state
= TARGET_DEBUG_RUNNING
;
1899 int nds32_examine_debug_reason(struct nds32
*nds32
)
1902 struct target
*target
= nds32
->target
;
1904 if (nds32
->hit_syscall
== true) {
1905 LOG_DEBUG("Hit syscall breakpoint");
1906 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1910 nds32
->get_debug_reason(nds32
, &reason
);
1912 LOG_DEBUG("nds32 examines debug reason: %s", nds32_debug_type_name
[reason
]);
1914 /* Examine debug reason */
1916 case NDS32_DEBUG_BREAK
:
1917 case NDS32_DEBUG_BREAK_16
:
1918 case NDS32_DEBUG_INST_BREAK
:
1922 struct nds32_instruction instruction
;
1924 nds32_get_mapped_reg(nds32
, PC
, &value_pc
);
1926 if (nds32_read_opcode(nds32
, value_pc
, &opcode
) != ERROR_OK
)
1928 if (nds32_evaluate_opcode(nds32
, opcode
, value_pc
, &instruction
) != ERROR_OK
)
1931 /* hit 'break 0x7FFF' */
1932 if ((instruction
.info
.opc_6
== 0x32) &&
1933 (instruction
.info
.sub_opc
== 0xA) &&
1934 (instruction
.info
.imm
== 0x7FFF)) {
1935 target
->debug_reason
= DBG_REASON_EXIT
;
1937 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1940 case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE
:
1941 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE
:
1942 case NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP
: /* GLOBAL_STOP is precise exception */
1946 result
= nds32
->get_watched_address(nds32
,
1947 &(nds32
->watched_address
), reason
);
1948 /* do single step(without watchpoints) to skip the "watched" instruction */
1949 nds32_step_without_watchpoint(nds32
);
1951 /* before single_step, save exception address */
1952 if (result
!= ERROR_OK
)
1955 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1958 case NDS32_DEBUG_DEBUG_INTERRUPT
:
1959 target
->debug_reason
= DBG_REASON_DBGRQ
;
1961 case NDS32_DEBUG_HARDWARE_SINGLE_STEP
:
1962 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1964 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE
:
1965 case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE
:
1966 case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE
:
1967 if (nds32
->get_watched_address(nds32
, &(nds32
->watched_address
), reason
) != ERROR_OK
)
1970 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1973 target
->debug_reason
= DBG_REASON_UNDEFINED
;
1980 int nds32_login(struct nds32
*nds32
)
1982 struct target
*target
= nds32
->target
;
1983 struct aice_port_s
*aice
= target_to_aice(target
);
1984 uint32_t passcode_length
;
1985 char command_sequence
[129];
1986 char command_str
[33];
1988 uint32_t copy_length
;
1992 LOG_DEBUG("nds32_login");
1994 if (nds32
->edm_passcode
) {
1995 /* convert EDM passcode to command sequences */
1996 passcode_length
= strlen(nds32
->edm_passcode
);
1997 command_sequence
[0] = '\0';
1998 for (i
= 0; i
< passcode_length
; i
+= 8) {
1999 if (passcode_length
- i
< 8)
2000 copy_length
= passcode_length
- i
;
2004 strncpy(code_str
, nds32
->edm_passcode
+ i
, copy_length
);
2005 code_str
[copy_length
] = '\0';
2006 code
= strtoul(code_str
, NULL
, 16);
2008 sprintf(command_str
, "write_misc gen_port0 0x%" PRIx32
";", code
);
2009 strcat(command_sequence
, command_str
);
2012 if (aice_program_edm(aice
, command_sequence
) != ERROR_OK
)
2015 /* get current privilege level */
2016 uint32_t value_edmsw
;
2017 aice_read_debug_reg(aice
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2018 nds32
->privilege_level
= (value_edmsw
>> 16) & 0x3;
2019 LOG_INFO("Current privilege level: %d", nds32
->privilege_level
);
2022 if (nds32_edm_ops_num
> 0) {
2023 const char *reg_name
;
2024 for (i
= 0 ; i
< nds32_edm_ops_num
; i
++) {
2025 code
= nds32_edm_ops
[i
].value
;
2026 if (nds32_edm_ops
[i
].reg_no
== 6)
2027 reg_name
= "gen_port0";
2028 else if (nds32_edm_ops
[i
].reg_no
== 7)
2029 reg_name
= "gen_port1";
2033 sprintf(command_str
, "write_misc %s 0x%" PRIx32
";", reg_name
, code
);
2034 if (aice_program_edm(aice
, command_str
) != ERROR_OK
)
2042 int nds32_halt(struct target
*target
)
2044 struct nds32
*nds32
= target_to_nds32(target
);
2045 struct aice_port_s
*aice
= target_to_aice(target
);
2046 enum target_state state
;
2048 LOG_DEBUG("target->state: %s",
2049 target_state_name(target
));
2051 if (target
->state
== TARGET_HALTED
) {
2052 LOG_DEBUG("target was already halted");
2056 if (nds32_target_state(nds32
, &state
) != ERROR_OK
)
2059 if (state
!= TARGET_HALTED
)
2060 /* TODO: if state == TARGET_HALTED, check ETYPE is DBGI or not */
2061 if (aice_halt(aice
) != ERROR_OK
)
2064 CHECK_RETVAL(nds32
->enter_debug_state(nds32
, true));
2066 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
2071 /* poll current target status */
2072 int nds32_poll(struct target
*target
)
2074 struct nds32
*nds32
= target_to_nds32(target
);
2075 enum target_state state
;
2077 if (nds32_target_state(nds32
, &state
) != ERROR_OK
)
2080 if (state
== TARGET_HALTED
) {
2081 if (target
->state
!= TARGET_HALTED
) {
2082 /* if false_hit, continue free_run */
2083 if (nds32
->enter_debug_state(nds32
, true) != ERROR_OK
) {
2084 struct aice_port_s
*aice
= target_to_aice(target
);
2089 LOG_DEBUG("Change target state to TARGET_HALTED.");
2091 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2093 } else if (state
== TARGET_RESET
) {
2094 if (target
->state
== TARGET_HALTED
) {
2095 /* similar to assert srst */
2096 register_cache_invalidate(nds32
->core_cache
);
2097 target
->state
= TARGET_RESET
;
2099 /* TODO: deassert srst */
2100 } else if (target
->state
== TARGET_RUNNING
) {
2101 /* reset as running */
2102 LOG_WARNING("<-- TARGET WARNING! The debug target has been reset. -->");
2105 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
) {
2106 LOG_DEBUG("Change target state to TARGET_RUNNING.");
2107 target
->state
= TARGET_RUNNING
;
2108 target
->debug_reason
= DBG_REASON_NOTHALTED
;
2115 int nds32_resume(struct target
*target
, int current
,
2116 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
2118 LOG_DEBUG("current %d address %08" TARGET_PRIxADDR
2119 " handle_breakpoints %d"
2120 " debug_execution %d",
2121 current
, address
, handle_breakpoints
, debug_execution
);
2123 struct nds32
*nds32
= target_to_nds32(target
);
2125 if (target
->state
!= TARGET_HALTED
) {
2126 LOG_ERROR("Target not halted");
2127 return ERROR_TARGET_NOT_HALTED
;
2130 address
= nds32_nextpc(nds32
, current
, address
);
2132 LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR
"%s", address
, !current
? "!" : "");
2134 if (!debug_execution
)
2135 target_free_all_working_areas(target
);
2137 /* Disable HSS to avoid users misuse HSS */
2138 if (nds32_reach_max_interrupt_level(nds32
) == false) {
2140 nds32_get_mapped_reg(nds32
, IR0
, &value_ir0
);
2141 value_ir0
&= ~(0x1 << 11);
2142 nds32_set_mapped_reg(nds32
, IR0
, value_ir0
);
2145 CHECK_RETVAL(nds32
->leave_debug_state(nds32
, true));
2146 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
2148 if (nds32
->virtual_hosting_ctrl_c
== false) {
2149 struct aice_port_s
*aice
= target_to_aice(target
);
2152 nds32
->virtual_hosting_ctrl_c
= false;
2154 target
->debug_reason
= DBG_REASON_NOTHALTED
;
2155 if (!debug_execution
)
2156 target
->state
= TARGET_RUNNING
;
2158 target
->state
= TARGET_DEBUG_RUNNING
;
2160 LOG_DEBUG("target->state: %s",
2161 target_state_name(target
));
2166 static int nds32_soft_reset_halt(struct target
*target
)
2169 struct nds32
*nds32
= target_to_nds32(target
);
2170 struct aice_port_s
*aice
= target_to_aice(target
);
2172 aice_assert_srst(aice
, AICE_SRST
);
2174 /* halt core and set pc to 0x0 */
2175 int retval
= target_halt(target
);
2176 if (retval
!= ERROR_OK
)
2179 /* start fetching from IVB */
2181 nds32_get_mapped_reg(nds32
, IR3
, &value_ir3
);
2182 nds32_set_mapped_reg(nds32
, PC
, value_ir3
& 0xFFFF0000);
2187 int nds32_assert_reset(struct target
*target
)
2189 struct nds32
*nds32
= target_to_nds32(target
);
2190 struct aice_port_s
*aice
= target_to_aice(target
);
2191 struct nds32_cpu_version
*cpu_version
= &(nds32
->cpu_version
);
2193 /* TODO: apply hw reset signal in not examined state */
2194 if (!(target_was_examined(target
))) {
2195 LOG_WARNING("Reset is not asserted because the target is not examined.");
2196 LOG_WARNING("Use a reset button or power cycle the target.");
2197 return ERROR_TARGET_NOT_EXAMINED
;
2200 if (target
->reset_halt
) {
2201 if ((nds32
->soft_reset_halt
)
2202 || (nds32
->edm
.version
< 0x51)
2203 || ((nds32
->edm
.version
== 0x51)
2204 && (cpu_version
->revision
== 0x1C)
2205 && (cpu_version
->cpu_id_family
== 0xC)
2206 && (cpu_version
->cpu_id_version
== 0x0)))
2207 nds32_soft_reset_halt(target
);
2209 aice_assert_srst(aice
, AICE_RESET_HOLD
);
2211 aice_assert_srst(aice
, AICE_SRST
);
2212 alive_sleep(nds32
->boot_time
);
2215 /* set passcode for secure MCU after core reset */
2218 /* registers are now invalid */
2219 register_cache_invalidate(nds32
->core_cache
);
2221 target
->state
= TARGET_RESET
;
2226 static int nds32_gdb_attach(struct nds32
*nds32
)
2228 LOG_DEBUG("nds32_gdb_attach, target coreid: %" PRId32
, nds32
->target
->coreid
);
2230 if (nds32
->attached
== false) {
2232 if (nds32
->keep_target_edm_ctl
) {
2233 /* backup target EDM_CTL */
2234 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
2235 aice_read_debug_reg(aice
, NDS_EDM_SR_EDM_CTL
, &nds32
->backup_edm_ctl
);
2238 target_halt(nds32
->target
);
2240 nds32
->attached
= true;
2246 static int nds32_gdb_detach(struct nds32
*nds32
)
2248 LOG_DEBUG("nds32_gdb_detach");
2249 bool backup_virtual_hosting_setting
;
2251 if (nds32
->attached
) {
2253 backup_virtual_hosting_setting
= nds32
->virtual_hosting
;
2254 /* turn off virtual hosting before resume as gdb-detach */
2255 nds32
->virtual_hosting
= false;
2256 target_resume(nds32
->target
, 1, 0, 0, 0);
2257 nds32
->virtual_hosting
= backup_virtual_hosting_setting
;
2259 if (nds32
->keep_target_edm_ctl
) {
2260 /* restore target EDM_CTL */
2261 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
2262 aice_write_debug_reg(aice
, NDS_EDM_SR_EDM_CTL
, nds32
->backup_edm_ctl
);
2265 nds32
->attached
= false;
2271 static int nds32_callback_event_handler(struct target
*target
,
2272 enum target_event event
, void *priv
)
2274 int retval
= ERROR_OK
;
2275 int target_number
= *(int *)priv
;
2277 if (target_number
!= target
->target_number
)
2280 struct nds32
*nds32
= target_to_nds32(target
);
2283 case TARGET_EVENT_GDB_ATTACH
:
2284 retval
= nds32_gdb_attach(nds32
);
2286 case TARGET_EVENT_GDB_DETACH
:
2287 retval
= nds32_gdb_detach(nds32
);
2296 int nds32_init(struct nds32
*nds32
)
2298 /* Initialize anything we can set up without talking to the target */
2299 nds32
->memory
.access_channel
= NDS_MEMORY_ACC_CPU
;
2301 /* register event callback */
2302 target_register_event_callback(nds32_callback_event_handler
,
2303 &(nds32
->target
->target_number
));
2308 int nds32_get_gdb_fileio_info(struct target
*target
, struct gdb_fileio_info
*fileio_info
)
2310 /* fill syscall parameters to file-I/O info */
2312 LOG_ERROR("Target has not initial file-I/O data structure");
2316 struct nds32
*nds32
= target_to_nds32(target
);
2318 uint32_t syscall_id
;
2320 if (nds32
->hit_syscall
== false)
2323 nds32_get_mapped_reg(nds32
, IR6
, &value_ir6
);
2324 syscall_id
= (value_ir6
>> 16) & 0x7FFF;
2325 nds32
->active_syscall_id
= syscall_id
;
2327 LOG_DEBUG("hit syscall ID: 0x%" PRIx32
, syscall_id
);
2329 /* free previous identifier storage */
2330 free(fileio_info
->identifier
);
2331 fileio_info
->identifier
= NULL
;
2333 uint32_t reg_r0
, reg_r1
, reg_r2
;
2334 nds32_get_mapped_reg(nds32
, R0
, ®_r0
);
2335 nds32_get_mapped_reg(nds32
, R1
, ®_r1
);
2336 nds32_get_mapped_reg(nds32
, R2
, ®_r2
);
2338 switch (syscall_id
) {
2339 case NDS32_SYSCALL_EXIT
:
2340 fileio_info
->identifier
= malloc(5);
2341 sprintf(fileio_info
->identifier
, "exit");
2342 fileio_info
->param_1
= reg_r0
;
2344 case NDS32_SYSCALL_OPEN
:
2346 uint8_t filename
[256];
2347 fileio_info
->identifier
= malloc(5);
2348 sprintf(fileio_info
->identifier
, "open");
2349 fileio_info
->param_1
= reg_r0
;
2350 /* reserve fileio_info->param_2 for length of path */
2351 fileio_info
->param_3
= reg_r1
;
2352 fileio_info
->param_4
= reg_r2
;
2354 target
->type
->read_buffer(target
, reg_r0
, 256, filename
);
2355 fileio_info
->param_2
= strlen((char *)filename
);
2358 case NDS32_SYSCALL_CLOSE
:
2359 fileio_info
->identifier
= malloc(6);
2360 sprintf(fileio_info
->identifier
, "close");
2361 fileio_info
->param_1
= reg_r0
;
2363 case NDS32_SYSCALL_READ
:
2364 fileio_info
->identifier
= malloc(5);
2365 sprintf(fileio_info
->identifier
, "read");
2366 fileio_info
->param_1
= reg_r0
;
2367 fileio_info
->param_2
= reg_r1
;
2368 fileio_info
->param_3
= reg_r2
;
2370 case NDS32_SYSCALL_WRITE
:
2371 fileio_info
->identifier
= malloc(6);
2372 sprintf(fileio_info
->identifier
, "write");
2373 fileio_info
->param_1
= reg_r0
;
2374 fileio_info
->param_2
= reg_r1
;
2375 fileio_info
->param_3
= reg_r2
;
2377 case NDS32_SYSCALL_LSEEK
:
2378 fileio_info
->identifier
= malloc(6);
2379 sprintf(fileio_info
->identifier
, "lseek");
2380 fileio_info
->param_1
= reg_r0
;
2381 fileio_info
->param_2
= reg_r1
;
2382 fileio_info
->param_3
= reg_r2
;
2384 case NDS32_SYSCALL_UNLINK
:
2386 uint8_t filename
[256];
2387 fileio_info
->identifier
= malloc(7);
2388 sprintf(fileio_info
->identifier
, "unlink");
2389 fileio_info
->param_1
= reg_r0
;
2390 /* reserve fileio_info->param_2 for length of path */
2392 target
->type
->read_buffer(target
, reg_r0
, 256, filename
);
2393 fileio_info
->param_2
= strlen((char *)filename
);
2396 case NDS32_SYSCALL_RENAME
:
2398 uint8_t filename
[256];
2399 fileio_info
->identifier
= malloc(7);
2400 sprintf(fileio_info
->identifier
, "rename");
2401 fileio_info
->param_1
= reg_r0
;
2402 /* reserve fileio_info->param_2 for length of old path */
2403 fileio_info
->param_3
= reg_r1
;
2404 /* reserve fileio_info->param_4 for length of new path */
2406 target
->type
->read_buffer(target
, reg_r0
, 256, filename
);
2407 fileio_info
->param_2
= strlen((char *)filename
);
2409 target
->type
->read_buffer(target
, reg_r1
, 256, filename
);
2410 fileio_info
->param_4
= strlen((char *)filename
);
2413 case NDS32_SYSCALL_FSTAT
:
2414 fileio_info
->identifier
= malloc(6);
2415 sprintf(fileio_info
->identifier
, "fstat");
2416 fileio_info
->param_1
= reg_r0
;
2417 fileio_info
->param_2
= reg_r1
;
2419 case NDS32_SYSCALL_STAT
:
2421 uint8_t filename
[256];
2422 fileio_info
->identifier
= malloc(5);
2423 sprintf(fileio_info
->identifier
, "stat");
2424 fileio_info
->param_1
= reg_r0
;
2425 /* reserve fileio_info->param_2 for length of old path */
2426 fileio_info
->param_3
= reg_r1
;
2428 target
->type
->read_buffer(target
, reg_r0
, 256, filename
);
2429 fileio_info
->param_2
= strlen((char *)filename
) + 1;
2432 case NDS32_SYSCALL_GETTIMEOFDAY
:
2433 fileio_info
->identifier
= malloc(13);
2434 sprintf(fileio_info
->identifier
, "gettimeofday");
2435 fileio_info
->param_1
= reg_r0
;
2436 fileio_info
->param_2
= reg_r1
;
2438 case NDS32_SYSCALL_ISATTY
:
2439 fileio_info
->identifier
= malloc(7);
2440 sprintf(fileio_info
->identifier
, "isatty");
2441 fileio_info
->param_1
= reg_r0
;
2443 case NDS32_SYSCALL_SYSTEM
:
2445 uint8_t command
[256];
2446 fileio_info
->identifier
= malloc(7);
2447 sprintf(fileio_info
->identifier
, "system");
2448 fileio_info
->param_1
= reg_r0
;
2449 /* reserve fileio_info->param_2 for length of old path */
2451 target
->type
->read_buffer(target
, reg_r0
, 256, command
);
2452 fileio_info
->param_2
= strlen((char *)command
);
2455 case NDS32_SYSCALL_ERRNO
:
2456 fileio_info
->identifier
= malloc(6);
2457 sprintf(fileio_info
->identifier
, "errno");
2458 nds32_set_mapped_reg(nds32
, R0
, nds32
->virtual_hosting_errno
);
2461 fileio_info
->identifier
= malloc(8);
2462 sprintf(fileio_info
->identifier
, "unknown");
2469 int nds32_gdb_fileio_end(struct target
*target
, int retcode
, int fileio_errno
, bool ctrl_c
)
2471 LOG_DEBUG("syscall return code: 0x%x, errno: 0x%x , ctrl_c: %s",
2472 retcode
, fileio_errno
, ctrl_c
? "true" : "false");
2474 struct nds32
*nds32
= target_to_nds32(target
);
2476 nds32_set_mapped_reg(nds32
, R0
, (uint32_t)retcode
);
2478 nds32
->virtual_hosting_errno
= fileio_errno
;
2479 nds32
->virtual_hosting_ctrl_c
= ctrl_c
;
2480 nds32
->active_syscall_id
= NDS32_SYSCALL_UNDEFINED
;
2485 int nds32_profiling(struct target
*target
, uint32_t *samples
,
2486 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
2488 /* sample $PC every 10 milliseconds */
2489 uint32_t iteration
= seconds
* 100;
2490 struct aice_port_s
*aice
= target_to_aice(target
);
2491 struct nds32
*nds32
= target_to_nds32(target
);
2493 /* REVISIT: can nds32 profile without halting? */
2494 if (target
->state
!= TARGET_HALTED
) {
2495 LOG_WARNING("target %s is not halted (profiling)", target
->cmd_name
);
2496 return ERROR_TARGET_NOT_HALTED
;
2499 if (max_num_samples
< iteration
)
2500 iteration
= max_num_samples
;
2502 int pc_regnum
= nds32
->register_map(nds32
, PC
);
2503 aice_profiling(aice
, 10, iteration
, pc_regnum
, samples
, num_samples
);
2505 register_cache_invalidate(nds32
->core_cache
);
2510 int nds32_gdb_fileio_write_memory(struct nds32
*nds32
, uint32_t address
,
2511 uint32_t size
, const uint8_t *buffer
)
2513 if ((nds32
->active_syscall_id
== NDS32_SYSCALL_FSTAT
) ||
2514 (nds32
->active_syscall_id
== NDS32_SYSCALL_STAT
)) {
2515 /* If doing GDB file-I/O, target should convert 'struct stat'
2516 * from gdb-format to target-format */
2517 uint8_t stat_buffer
[NDS32_STRUCT_STAT_SIZE
];
2519 stat_buffer
[0] = buffer
[3];
2520 stat_buffer
[1] = buffer
[2];
2522 stat_buffer
[2] = buffer
[7];
2523 stat_buffer
[3] = buffer
[6];
2525 stat_buffer
[4] = buffer
[11];
2526 stat_buffer
[5] = buffer
[10];
2527 stat_buffer
[6] = buffer
[9];
2528 stat_buffer
[7] = buffer
[8];
2530 stat_buffer
[8] = buffer
[15];
2531 stat_buffer
[9] = buffer
[16];
2533 stat_buffer
[10] = buffer
[19];
2534 stat_buffer
[11] = buffer
[18];
2536 stat_buffer
[12] = buffer
[23];
2537 stat_buffer
[13] = buffer
[22];
2539 stat_buffer
[14] = buffer
[27];
2540 stat_buffer
[15] = buffer
[26];
2542 stat_buffer
[16] = buffer
[35];
2543 stat_buffer
[17] = buffer
[34];
2544 stat_buffer
[18] = buffer
[33];
2545 stat_buffer
[19] = buffer
[32];
2547 stat_buffer
[20] = buffer
[55];
2548 stat_buffer
[21] = buffer
[54];
2549 stat_buffer
[22] = buffer
[53];
2550 stat_buffer
[23] = buffer
[52];
2552 stat_buffer
[24] = 0;
2553 stat_buffer
[25] = 0;
2554 stat_buffer
[26] = 0;
2555 stat_buffer
[27] = 0;
2557 stat_buffer
[28] = buffer
[59];
2558 stat_buffer
[29] = buffer
[58];
2559 stat_buffer
[30] = buffer
[57];
2560 stat_buffer
[31] = buffer
[56];
2562 stat_buffer
[32] = 0;
2563 stat_buffer
[33] = 0;
2564 stat_buffer
[34] = 0;
2565 stat_buffer
[35] = 0;
2567 stat_buffer
[36] = buffer
[63];
2568 stat_buffer
[37] = buffer
[62];
2569 stat_buffer
[38] = buffer
[61];
2570 stat_buffer
[39] = buffer
[60];
2572 stat_buffer
[40] = 0;
2573 stat_buffer
[41] = 0;
2574 stat_buffer
[42] = 0;
2575 stat_buffer
[43] = 0;
2577 stat_buffer
[44] = buffer
[43];
2578 stat_buffer
[45] = buffer
[42];
2579 stat_buffer
[46] = buffer
[41];
2580 stat_buffer
[47] = buffer
[40];
2582 stat_buffer
[48] = buffer
[51];
2583 stat_buffer
[49] = buffer
[50];
2584 stat_buffer
[50] = buffer
[49];
2585 stat_buffer
[51] = buffer
[48];
2587 stat_buffer
[52] = 0;
2588 stat_buffer
[53] = 0;
2589 stat_buffer
[54] = 0;
2590 stat_buffer
[55] = 0;
2591 stat_buffer
[56] = 0;
2592 stat_buffer
[57] = 0;
2593 stat_buffer
[58] = 0;
2594 stat_buffer
[59] = 0;
2596 return nds32_write_buffer(nds32
->target
, address
, NDS32_STRUCT_STAT_SIZE
, stat_buffer
);
2597 } else if (nds32
->active_syscall_id
== NDS32_SYSCALL_GETTIMEOFDAY
) {
2598 /* If doing GDB file-I/O, target should convert 'struct timeval'
2599 * from gdb-format to target-format */
2600 uint8_t timeval_buffer
[NDS32_STRUCT_TIMEVAL_SIZE
];
2601 timeval_buffer
[0] = buffer
[3];
2602 timeval_buffer
[1] = buffer
[2];
2603 timeval_buffer
[2] = buffer
[1];
2604 timeval_buffer
[3] = buffer
[0];
2605 timeval_buffer
[4] = buffer
[11];
2606 timeval_buffer
[5] = buffer
[10];
2607 timeval_buffer
[6] = buffer
[9];
2608 timeval_buffer
[7] = buffer
[8];
2610 return nds32_write_buffer(nds32
->target
, address
, NDS32_STRUCT_TIMEVAL_SIZE
, timeval_buffer
);
2613 return nds32_write_buffer(nds32
->target
, address
, size
, buffer
);
2616 int nds32_reset_halt(struct nds32
*nds32
)
2618 LOG_INFO("reset halt as init");
2620 struct aice_port_s
*aice
= target_to_aice(nds32
->target
);
2621 aice_assert_srst(aice
, AICE_RESET_HOLD
);
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