1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2013 Andes Technology *
5 * Hsiangkai Wang <hkwang@andestech.com> *
6 ***************************************************************************/
8 #ifndef OPENOCD_TARGET_NDS32_H
9 #define OPENOCD_TARGET_NDS32_H
11 #include <jtag/jtag.h>
13 #include "target_type.h"
15 #include "breakpoints.h"
16 #include "nds32_reg.h"
17 #include "nds32_insn.h"
18 #include "nds32_edm.h"
20 #define NDS32_EDM_OPERATION_MAX_NUM 64
22 #define CHECK_RETVAL(action) \
24 int __retval = (action); \
25 if (__retval != ERROR_OK) { \
26 LOG_DEBUG("error while calling \"%s\"", \
34 * Holds the interface to Andes cores.
37 extern const char *nds32_debug_type_name
[11];
39 enum nds32_debug_reason
{
40 NDS32_DEBUG_BREAK
= 0,
42 NDS32_DEBUG_INST_BREAK
,
43 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE
,
44 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE
,
45 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE
,
46 NDS32_DEBUG_DEBUG_INTERRUPT
,
47 NDS32_DEBUG_HARDWARE_SINGLE_STEP
,
48 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE
,
49 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE
,
50 NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP
,
53 #define NDS32_STRUCT_STAT_SIZE 60
54 #define NDS32_STRUCT_TIMEVAL_SIZE 8
56 enum nds32_syscall_id
{
57 NDS32_SYSCALL_UNDEFINED
= 0,
58 NDS32_SYSCALL_EXIT
= 1,
59 NDS32_SYSCALL_OPEN
= 2,
60 NDS32_SYSCALL_CLOSE
= 3,
61 NDS32_SYSCALL_READ
= 4,
62 NDS32_SYSCALL_WRITE
= 5,
63 NDS32_SYSCALL_LSEEK
= 6,
64 NDS32_SYSCALL_UNLINK
= 7,
65 NDS32_SYSCALL_RENAME
= 3001,
66 NDS32_SYSCALL_FSTAT
= 10,
67 NDS32_SYSCALL_STAT
= 15,
68 NDS32_SYSCALL_GETTIMEOFDAY
= 19,
69 NDS32_SYSCALL_ISATTY
= 3002,
70 NDS32_SYSCALL_SYSTEM
= 3003,
71 NDS32_SYSCALL_ERRNO
= 6001,
74 #define NDS32_COMMON_MAGIC 0xADE5ADE5U
78 /** EDM_CFG.VER, indicate the EDM version */
81 /** The number of hardware breakpoints */
84 /** EDM_CFG.DALM, indicate if direct local memory access
85 * feature is supported or not */
86 bool direct_access_local_memory
;
88 /** Support ACC_CTL register */
92 bool support_max_stop
;
97 /** enable cache or not */
100 /** cache sets per way */
106 /** cache line size */
109 /** cache locking support */
113 struct nds32_memory
{
116 struct nds32_cache icache
;
119 struct nds32_cache dcache
;
121 /** On-chip instruction local memory base */
124 /** On-chip instruction local memory size */
127 /** ILM base register alignment version */
130 /** DLM is enabled or not */
133 /** DLM start address */
136 /** DLM end address */
139 /** On-chip data local memory base */
142 /** On-chip data local memory size */
145 /** DLM base register alignment version */
148 /** DLM is enabled or not */
151 /** DLM start address */
154 /** DLM end address */
157 /** Memory access method */
158 enum nds_memory_access access_channel
;
160 /** Memory access mode */
161 enum nds_memory_select mode
;
163 /** Address translation */
164 bool address_translation
;
167 struct nds32_cpu_version
{
168 bool performance_extension
;
169 bool _16bit_extension
;
170 bool performance_extension_2
;
171 bool cop_fpu_extension
;
172 bool string_extension
;
179 struct nds32_mmu_config
{
180 int memory_protection
;
181 int memory_protection_version
;
182 bool fully_associative_tlb
;
186 bool _8k_page_support
;
187 int extra_page_size_support
;
189 bool hardware_page_table_walker
;
196 int default_min_page_size
;
197 bool multiple_page_size_in_use
;
200 struct nds32_misc_config
{
202 bool local_memory_dma
;
203 bool performance_monitor
;
204 bool high_speed_memory_port
;
206 bool div_instruction
;
207 bool mac_instruction
;
210 bool reduce_register
;
212 bool interruption_level
;
213 int baseline_instruction
;
215 bool implement_dependant_register
;
216 bool implement_dependant_sr_encoding
;
224 * Represents a generic Andes core.
227 unsigned int common_magic
;
229 struct reg_cache
*core_cache
;
231 /** Handle for the debug module. */
232 struct nds32_edm edm
;
234 /** Memory information */
235 struct nds32_memory memory
;
238 struct nds32_cpu_version cpu_version
;
240 /** MMU configuration */
241 struct nds32_mmu_config mmu_config
;
243 /** Misc configuration */
244 struct nds32_misc_config misc_config
;
246 /** Retrieve all core registers, for display. */
247 int (*full_context
)(struct nds32
*nds32
);
249 /** Register mappings */
250 int (*register_map
)(struct nds32
*nds32
, int reg_no
);
252 /** Get debug exception virtual address */
253 int (*get_debug_reason
)(struct nds32
*nds32
, uint32_t *reason
);
255 /** Restore target registers may be modified in debug state */
256 int (*leave_debug_state
)(struct nds32
*nds32
, bool enable_watchpoint
);
258 /** Backup target registers may be modified in debug state */
259 int (*enter_debug_state
)(struct nds32
*nds32
, bool enable_watchpoint
);
261 /** Get address hit watchpoint */
262 int (*get_watched_address
)(struct nds32
*nds32
, uint32_t *address
, uint32_t reason
);
264 /** maximum interrupt level */
265 uint32_t max_interrupt_level
;
267 /** current interrupt level */
268 uint32_t current_interrupt_level
;
270 uint32_t watched_address
;
272 /** Flag reporting whether virtual hosting is active. */
273 bool virtual_hosting
;
275 /** Flag reporting whether continue/step hits syscall or not */
278 /** Value to be returned by virtual hosting SYS_ERRNO request. */
279 int virtual_hosting_errno
;
281 /** Flag reporting whether syscall is aborted */
282 bool virtual_hosting_ctrl_c
;
284 /** Record syscall ID for other operations to do special processing for target */
285 int active_syscall_id
;
287 struct breakpoint syscall_break
;
289 /** Flag reporting whether global stop is active. */
292 /** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */
293 bool soft_reset_halt
;
295 /** reset-halt as target examine */
296 bool reset_halt_as_examine
;
298 /** backup/restore target EDM_CTL value. As debugging target debug
299 * handler, it should be true. */
300 bool keep_target_edm_ctl
;
302 /* Value of $EDM_CTL before target enters debug mode */
303 uint32_t backup_edm_ctl
;
305 /** always use word-aligned address to access memory */
306 bool word_access_mem
;
308 /** EDM passcode for debugging secure MCU */
311 /** current privilege_level if using secure MCU. value 0 is the highest level. */
314 /** Period to wait after SRST. */
317 /** Flag to indicate HSS steps into ISR or not */
318 bool step_isr_enable
;
320 /** Flag to indicate register table is ready or not */
321 bool init_arch_info_after_halted
;
323 /** Flag to indicate audio-extension is enabled or not */
326 /** Flag to indicate fpu-extension is enabled or not */
329 /* Andes Core has mixed endian model. Instruction is always big-endian.
330 * Data may be big or little endian. Device registers may have different
331 * endian from data and instruction. */
332 /** Endian of data memory */
333 enum target_endianness data_endian
;
335 /** Endian of device registers */
336 enum target_endianness device_reg_endian
;
338 /** Flag to indicate if auto convert software breakpoints to
339 * hardware breakpoints or not in ROM */
340 bool auto_convert_hw_bp
;
342 /* Flag to indicate the target is attached by debugger or not */
345 /** Backpointer to the target. */
346 struct target
*target
;
354 struct target
*target
;
359 struct nds32_edm_operation
{
364 extern int nds32_config(struct nds32
*nds32
);
365 extern int nds32_init_arch_info(struct target
*target
, struct nds32
*nds32
);
366 extern int nds32_full_context(struct nds32
*nds32
);
367 extern int nds32_arch_state(struct target
*target
);
368 extern int nds32_add_software_breakpoint(struct target
*target
,
369 struct breakpoint
*breakpoint
);
370 extern int nds32_remove_software_breakpoint(struct target
*target
,
371 struct breakpoint
*breakpoint
);
373 extern int nds32_get_gdb_reg_list(struct target
*target
,
374 struct reg
**reg_list
[], int *reg_list_size
,
375 enum target_register_class reg_class
);
377 extern int nds32_write_buffer(struct target
*target
, uint32_t address
,
378 uint32_t size
, const uint8_t *buffer
);
379 extern int nds32_read_buffer(struct target
*target
, uint32_t address
,
380 uint32_t size
, uint8_t *buffer
);
381 extern int nds32_read_memory(struct target
*target
, uint32_t address
,
382 uint32_t size
, uint32_t count
, uint8_t *buffer
);
383 extern int nds32_write_memory(struct target
*target
, uint32_t address
,
384 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
386 extern int nds32_init_register_table(struct nds32
*nds32
);
387 extern int nds32_init_memory_info(struct nds32
*nds32
);
388 extern int nds32_restore_context(struct target
*target
);
389 extern int nds32_get_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t *value
);
390 extern int nds32_set_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t value
);
392 extern int nds32_edm_config(struct nds32
*nds32
);
393 extern int nds32_cache_sync(struct target
*target
, target_addr_t address
, uint32_t length
);
394 extern int nds32_mmu(struct target
*target
, int *enabled
);
395 extern int nds32_virtual_to_physical(struct target
*target
, target_addr_t address
,
396 target_addr_t
*physical
);
397 extern int nds32_read_phys_memory(struct target
*target
, target_addr_t address
,
398 uint32_t size
, uint32_t count
, uint8_t *buffer
);
399 extern int nds32_write_phys_memory(struct target
*target
, target_addr_t address
,
400 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
401 extern uint32_t nds32_nextpc(struct nds32
*nds32
, int current
, uint32_t address
);
402 extern int nds32_examine_debug_reason(struct nds32
*nds32
);
403 extern int nds32_step(struct target
*target
, int current
,
404 target_addr_t address
, int handle_breakpoints
);
405 extern int nds32_target_state(struct nds32
*nds32
, enum target_state
*state
);
406 extern int nds32_halt(struct target
*target
);
407 extern int nds32_poll(struct target
*target
);
408 extern int nds32_resume(struct target
*target
, int current
,
409 target_addr_t address
, int handle_breakpoints
, int debug_execution
);
410 extern int nds32_assert_reset(struct target
*target
);
411 extern int nds32_init(struct nds32
*nds32
);
412 extern int nds32_get_gdb_fileio_info(struct target
*target
, struct gdb_fileio_info
*fileio_info
);
413 extern int nds32_gdb_fileio_write_memory(struct nds32
*nds32
, uint32_t address
,
414 uint32_t size
, const uint8_t *buffer
);
415 extern int nds32_gdb_fileio_end(struct target
*target
, int retcode
, int fileio_errno
, bool ctrl_c
);
416 extern int nds32_reset_halt(struct nds32
*nds32
);
417 extern int nds32_login(struct nds32
*nds32
);
418 extern int nds32_profiling(struct target
*target
, uint32_t *samples
,
419 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
);
421 /** Convert target handle to generic Andes target state handle. */
422 static inline struct nds32
*target_to_nds32(struct target
*target
)
425 return target
->arch_info
;
429 static inline struct aice_port_s
*target_to_aice(struct target
*target
)
432 return target
->tap
->priv
;
435 static inline bool is_nds32(struct nds32
*nds32
)
438 return nds32
->common_magic
== NDS32_COMMON_MAGIC
;
441 static inline bool nds32_reach_max_interrupt_level(struct nds32
*nds32
)
444 return nds32
->max_interrupt_level
== nds32
->current_interrupt_level
;
447 #endif /* OPENOCD_TARGET_NDS32_H */
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