src/target/nds32.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2013 Andes Technology                                   *
   5  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_TARGET_NDS32_H
   9 #define OPENOCD_TARGET_NDS32_H
  10
  11 #include <jtag/jtag.h>
  12 #include "target.h"
  13 #include "target_type.h"
  14 #include "register.h"
  15 #include "breakpoints.h"
  16 #include "nds32_reg.h"
  17 #include "nds32_insn.h"
  18 #include "nds32_edm.h"
  19
  20 #define NDS32_EDM_OPERATION_MAX_NUM 64
  21
  22 #define CHECK_RETVAL(action)                    \
  23         do {                                    \
  24                 int __retval = (action);        \
  25                 if (__retval != ERROR_OK) {     \
  26                         LOG_DEBUG("error while calling \"%s\"", \
  27                                 # action);     \
  28                         return __retval;        \
  29                 }                               \
  30         } while (0)
  31
  32 /**
  33  * @file
  34  * Holds the interface to Andes cores.
  35  */
  36
  37 extern const char *nds32_debug_type_name[11];
  38
  39 enum nds32_debug_reason {
  40         NDS32_DEBUG_BREAK = 0,
  41         NDS32_DEBUG_BREAK_16,
  42         NDS32_DEBUG_INST_BREAK,
  43         NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE,
  44         NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE,
  45         NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE,
  46         NDS32_DEBUG_DEBUG_INTERRUPT,
  47         NDS32_DEBUG_HARDWARE_SINGLE_STEP,
  48         NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE,
  49         NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE,
  50         NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP,
  51 };
  52
  53 #define NDS32_STRUCT_STAT_SIZE 60
  54 #define NDS32_STRUCT_TIMEVAL_SIZE 8
  55
  56 enum nds32_syscall_id {
  57         NDS32_SYSCALL_UNDEFINED = 0,
  58         NDS32_SYSCALL_EXIT = 1,
  59         NDS32_SYSCALL_OPEN = 2,
  60         NDS32_SYSCALL_CLOSE = 3,
  61         NDS32_SYSCALL_READ = 4,
  62         NDS32_SYSCALL_WRITE = 5,
  63         NDS32_SYSCALL_LSEEK = 6,
  64         NDS32_SYSCALL_UNLINK = 7,
  65         NDS32_SYSCALL_RENAME = 3001,
  66         NDS32_SYSCALL_FSTAT = 10,
  67         NDS32_SYSCALL_STAT = 15,
  68         NDS32_SYSCALL_GETTIMEOFDAY = 19,
  69         NDS32_SYSCALL_ISATTY = 3002,
  70         NDS32_SYSCALL_SYSTEM = 3003,
  71         NDS32_SYSCALL_ERRNO = 6001,
  72 };
  73
  74 #define NDS32_COMMON_MAGIC 0xADE5ADE5U
  75
  76 struct nds32_edm {
  77
  78         /** EDM_CFG.VER, indicate the EDM version */
  79         int version;
  80
  81         /** The number of hardware breakpoints */
  82         int breakpoint_num;
  83
  84         /** EDM_CFG.DALM, indicate if direct local memory access
  85          * feature is supported or not */
  86         bool direct_access_local_memory;
  87
  88         /** Support ACC_CTL register */
  89         bool access_control;
  90
  91         /** */
  92         bool support_max_stop;
  93 };
  94
  95 struct nds32_cache {
  96
  97         /** enable cache or not */
  98         bool enable;
  99
 100         /** cache sets per way */
 101         int set;
 102
 103         /** cache ways */
 104         int way;
 105
 106         /** cache line size */
 107         int line_size;
 108
 109         /** cache locking support */
 110         bool lock_support;
 111 };
 112
 113 struct nds32_memory {
 114
 115         /** ICache */
 116         struct nds32_cache icache;
 117
 118         /** DCache */
 119         struct nds32_cache dcache;
 120
 121         /** On-chip instruction local memory base */
 122         int ilm_base;
 123
 124         /** On-chip instruction local memory size */
 125         int ilm_size;
 126
 127         /** ILM base register alignment version */
 128         int ilm_align_ver;
 129
 130         /** DLM is enabled or not */
 131         bool ilm_enable;
 132
 133         /** DLM start address */
 134         int ilm_start;
 135
 136         /** DLM end address */
 137         int ilm_end;
 138
 139         /** On-chip data local memory base */
 140         int dlm_base;
 141
 142         /** On-chip data local memory size */
 143         int dlm_size;
 144
 145         /** DLM base register alignment version */
 146         int dlm_align_ver;
 147
 148         /** DLM is enabled or not */
 149         bool dlm_enable;
 150
 151         /** DLM start address */
 152         int dlm_start;
 153
 154         /** DLM end address */
 155         int dlm_end;
 156
 157         /** Memory access method */
 158         enum nds_memory_access access_channel;
 159
 160         /** Memory access mode */
 161         enum nds_memory_select mode;
 162
 163         /** Address translation */
 164         bool address_translation;
 165 };
 166
 167 struct nds32_cpu_version {
 168         bool performance_extension;
 169         bool _16bit_extension;
 170         bool performance_extension_2;
 171         bool cop_fpu_extension;
 172         bool string_extension;
 173
 174         int revision;
 175         int cpu_id_family;
 176         int cpu_id_version;
 177 };
 178
 179 struct nds32_mmu_config {
 180         int memory_protection;
 181         int memory_protection_version;
 182         bool fully_associative_tlb;
 183         int tlb_size;
 184         int tlb_ways;
 185         int tlb_sets;
 186         bool _8k_page_support;
 187         int extra_page_size_support;
 188         bool tlb_lock;
 189         bool hardware_page_table_walker;
 190         bool default_endian;
 191         int partition_num;
 192         bool invisible_tlb;
 193         bool vlpt;
 194         bool ntme;
 195         bool drde;
 196         int default_min_page_size;
 197         bool multiple_page_size_in_use;
 198 };
 199
 200 struct nds32_misc_config {
 201         bool edm;
 202         bool local_memory_dma;
 203         bool performance_monitor;
 204         bool high_speed_memory_port;
 205         bool debug_tracer;
 206         bool div_instruction;
 207         bool mac_instruction;
 208         int audio_isa;
 209         bool l2_cache;
 210         bool reduce_register;
 211         bool addr_24;
 212         bool interruption_level;
 213         int baseline_instruction;
 214         bool no_dx_register;
 215         bool implement_dependant_register;
 216         bool implement_dependant_sr_encoding;
 217         bool ifc;
 218         bool mcu;
 219         bool ex9;
 220         int shadow;
 221 };
 222
 223 /**
 224  * Represents a generic Andes core.
 225  */
 226 struct nds32 {
 227         uint32_t common_magic;
 228         struct reg_cache *core_cache;
 229
 230         /** Handle for the debug module. */
 231         struct nds32_edm edm;
 232
 233         /** Memory information */
 234         struct nds32_memory memory;
 235
 236         /** cpu version */
 237         struct nds32_cpu_version cpu_version;
 238
 239         /** MMU configuration */
 240         struct nds32_mmu_config mmu_config;
 241
 242         /** Misc configuration */
 243         struct nds32_misc_config misc_config;
 244
 245         /** Retrieve all core registers, for display. */
 246         int (*full_context)(struct nds32 *nds32);
 247
 248         /** Register mappings */
 249         int (*register_map)(struct nds32 *nds32, int reg_no);
 250
 251         /** Get debug exception virtual address */
 252         int (*get_debug_reason)(struct nds32 *nds32, uint32_t *reason);
 253
 254         /** Restore target registers may be modified in debug state */
 255         int (*leave_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
 256
 257         /** Backup target registers may be modified in debug state */
 258         int (*enter_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
 259
 260         /** Get address hit watchpoint */
 261         int (*get_watched_address)(struct nds32 *nds32, uint32_t *address, uint32_t reason);
 262
 263         /** maximum interrupt level */
 264         uint32_t max_interrupt_level;
 265
 266         /** current interrupt level */
 267         uint32_t current_interrupt_level;
 268
 269         uint32_t watched_address;
 270
 271         /** Flag reporting whether virtual hosting is active. */
 272         bool virtual_hosting;
 273
 274         /** Flag reporting whether continue/step hits syscall or not */
 275         bool hit_syscall;
 276
 277         /** Value to be returned by virtual hosting SYS_ERRNO request. */
 278         int virtual_hosting_errno;
 279
 280         /** Flag reporting whether syscall is aborted */
 281         bool virtual_hosting_ctrl_c;
 282
 283         /** Record syscall ID for other operations to do special processing for target */
 284         int active_syscall_id;
 285
 286         struct breakpoint syscall_break;
 287
 288         /** Flag reporting whether global stop is active. */
 289         bool global_stop;
 290
 291         /** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */
 292         bool soft_reset_halt;
 293
 294         /** reset-halt as target examine */
 295         bool reset_halt_as_examine;
 296
 297         /** backup/restore target EDM_CTL value. As debugging target debug
 298          * handler, it should be true. */
 299         bool keep_target_edm_ctl;
 300
 301         /* Value of $EDM_CTL before target enters debug mode */
 302         uint32_t backup_edm_ctl;
 303
 304         /** always use word-aligned address to access memory */
 305         bool word_access_mem;
 306
 307         /** EDM passcode for debugging secure MCU */
 308         char *edm_passcode;
 309
 310         /** current privilege_level if using secure MCU. value 0 is the highest level.  */
 311         int privilege_level;
 312
 313         /** Period to wait after SRST. */
 314         uint32_t boot_time;
 315
 316         /** Flag to indicate HSS steps into ISR or not */
 317         bool step_isr_enable;
 318
 319         /** Flag to indicate register table is ready or not */
 320         bool init_arch_info_after_halted;
 321
 322         /** Flag to indicate audio-extension is enabled or not */
 323         bool audio_enable;
 324
 325         /** Flag to indicate fpu-extension is enabled or not */
 326         bool fpu_enable;
 327
 328         /* Andes Core has mixed endian model. Instruction is always big-endian.
 329          * Data may be big or little endian. Device registers may have different
 330          * endian from data and instruction. */
 331         /** Endian of data memory */
 332         enum target_endianness data_endian;
 333
 334         /** Endian of device registers */
 335         enum target_endianness device_reg_endian;
 336
 337         /** Flag to indicate if auto convert software breakpoints to
 338          *  hardware breakpoints or not in ROM */
 339         bool auto_convert_hw_bp;
 340
 341         /* Flag to indicate the target is attached by debugger or not */
 342         bool attached;
 343
 344         /** Backpointer to the target. */
 345         struct target *target;
 346
 347         void *arch_info;
 348 };
 349
 350 struct nds32_reg {
 351         int32_t num;
 352         uint8_t value[8];
 353         struct target *target;
 354         struct nds32 *nds32;
 355         bool enable;
 356 };
 357
 358 struct nds32_edm_operation {
 359         uint32_t reg_no;
 360         uint32_t value;
 361 };
 362
 363 extern int nds32_config(struct nds32 *nds32);
 364 extern int nds32_init_arch_info(struct target *target, struct nds32 *nds32);
 365 extern int nds32_full_context(struct nds32 *nds32);
 366 extern int nds32_arch_state(struct target *target);
 367 extern int nds32_add_software_breakpoint(struct target *target,
 368                 struct breakpoint *breakpoint);
 369 extern int nds32_remove_software_breakpoint(struct target *target,
 370                 struct breakpoint *breakpoint);
 371
 372 extern int nds32_get_gdb_reg_list(struct target *target,
 373                 struct reg **reg_list[], int *reg_list_size,
 374                 enum target_register_class reg_class);
 375
 376 extern int nds32_write_buffer(struct target *target, uint32_t address,
 377                 uint32_t size, const uint8_t *buffer);
 378 extern int nds32_read_buffer(struct target *target, uint32_t address,
 379                 uint32_t size, uint8_t *buffer);
 380 extern int nds32_read_memory(struct target *target, uint32_t address,
 381                 uint32_t size, uint32_t count, uint8_t *buffer);
 382 extern int nds32_write_memory(struct target *target, uint32_t address,
 383                 uint32_t size, uint32_t count, const uint8_t *buffer);
 384
 385 extern int nds32_init_register_table(struct nds32 *nds32);
 386 extern int nds32_init_memory_info(struct nds32 *nds32);
 387 extern int nds32_restore_context(struct target *target);
 388 extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value);
 389 extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value);
 390
 391 extern int nds32_edm_config(struct nds32 *nds32);
 392 extern int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t length);
 393 extern int nds32_mmu(struct target *target, int *enabled);
 394 extern int nds32_virtual_to_physical(struct target *target, target_addr_t address,
 395                 target_addr_t *physical);
 396 extern int nds32_read_phys_memory(struct target *target, target_addr_t address,
 397                 uint32_t size, uint32_t count, uint8_t *buffer);
 398 extern int nds32_write_phys_memory(struct target *target, target_addr_t address,
 399                 uint32_t size, uint32_t count, const uint8_t *buffer);
 400 extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address);
 401 extern int nds32_examine_debug_reason(struct nds32 *nds32);
 402 extern int nds32_step(struct target *target, int current,
 403                 target_addr_t address, int handle_breakpoints);
 404 extern int nds32_target_state(struct nds32 *nds32, enum target_state *state);
 405 extern int nds32_halt(struct target *target);
 406 extern int nds32_poll(struct target *target);
 407 extern int nds32_resume(struct target *target, int current,
 408                 target_addr_t address, int handle_breakpoints, int debug_execution);
 409 extern int nds32_assert_reset(struct target *target);
 410 extern int nds32_init(struct nds32 *nds32);
 411 extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info);
 412 extern int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address,
 413                 uint32_t size, const uint8_t *buffer);
 414 extern int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c);
 415 extern int nds32_reset_halt(struct nds32 *nds32);
 416 extern int nds32_login(struct nds32 *nds32);
 417 extern int nds32_profiling(struct target *target, uint32_t *samples,
 418                         uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 419
 420 /** Convert target handle to generic Andes target state handle. */
 421 static inline struct nds32 *target_to_nds32(struct target *target)
 422 {
 423         assert(target);
 424         return target->arch_info;
 425 }
 426
 427 /** */
 428 static inline struct aice_port_s *target_to_aice(struct target *target)
 429 {
 430         assert(target);
 431         return target->tap->priv;
 432 }
 433
 434 static inline bool is_nds32(struct nds32 *nds32)
 435 {
 436         assert(nds32);
 437         return nds32->common_magic == NDS32_COMMON_MAGIC;
 438 }
 439
 440 static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32)
 441 {
 442         assert(nds32);
 443         return nds32->max_interrupt_level == nds32->current_interrupt_level;
 444 }
 445
 446 #endif /* OPENOCD_TARGET_NDS32_H */