1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
25 #include <helper/command.h>
27 #include "nds32_aice.h"
28 #include "nds32_disassembler.h"
30 extern struct nds32_edm_operation nds32_edm_ops
[NDS32_EDM_OPERATION_MAX_NUM
];
31 extern uint32_t nds32_edm_ops_num
;
33 static const char *const NDS_MEMORY_ACCESS_NAME
[] = {
38 static const char *const NDS_MEMORY_SELECT_NAME
[] = {
45 COMMAND_HANDLER(handle_nds32_dssim_command
)
47 struct target
*target
= get_current_target(CMD_CTX
);
48 struct nds32
*nds32
= target_to_nds32(target
);
50 if (!is_nds32(nds32
)) {
51 command_print(CMD_CTX
, "current target isn't an Andes core");
56 if (strcmp(CMD_ARGV
[0], "on") == 0)
57 nds32
->step_isr_enable
= true;
58 if (strcmp(CMD_ARGV
[0], "off") == 0)
59 nds32
->step_isr_enable
= false;
62 command_print(CMD_CTX
, "$INT_MASK.DSSIM: %d", nds32
->step_isr_enable
);
67 COMMAND_HANDLER(handle_nds32_memory_access_command
)
69 struct target
*target
= get_current_target(CMD_CTX
);
70 struct nds32
*nds32
= target_to_nds32(target
);
71 struct aice_port_s
*aice
= target_to_aice(target
);
73 if (!is_nds32(nds32
)) {
74 command_print(CMD_CTX
, "current target isn't an Andes core");
80 /* If target has no cache, always use BUS mode
81 * to access memory. */
82 struct nds32_memory
*memory
= &(nds32
->memory
);
84 if (memory
->dcache
.line_size
== 0) {
85 /* There is no Dcache. */
86 nds32
->memory
.access_channel
= NDS_MEMORY_ACC_BUS
;
87 } else if (memory
->dcache
.enable
== false) {
88 /* Dcache is disabled. */
89 nds32
->memory
.access_channel
= NDS_MEMORY_ACC_BUS
;
91 /* There is Dcache and Dcache is enabled. */
92 if (strcmp(CMD_ARGV
[0], "bus") == 0)
93 nds32
->memory
.access_channel
= NDS_MEMORY_ACC_BUS
;
94 else if (strcmp(CMD_ARGV
[0], "cpu") == 0)
95 nds32
->memory
.access_channel
= NDS_MEMORY_ACC_CPU
;
96 else /* default access channel is NDS_MEMORY_ACC_CPU */
97 nds32
->memory
.access_channel
= NDS_MEMORY_ACC_CPU
;
100 aice_memory_access(aice
, nds32
->memory
.access_channel
);
103 command_print(CMD_CTX
, "memory access channel: %s",
104 NDS_MEMORY_ACCESS_NAME
[nds32
->memory
.access_channel
]);
109 COMMAND_HANDLER(handle_nds32_memory_mode_command
)
111 struct target
*target
= get_current_target(CMD_CTX
);
112 struct nds32
*nds32
= target_to_nds32(target
);
113 struct aice_port_s
*aice
= target_to_aice(target
);
115 if (!is_nds32(nds32
)) {
116 command_print(CMD_CTX
, "current target isn't an Andes core");
122 if (nds32
->edm
.access_control
== false) {
123 command_print(CMD_CTX
, "Target does not support ACC_CTL. "
124 "Set memory mode to MEMORY");
125 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
126 } else if (nds32
->edm
.direct_access_local_memory
== false) {
127 command_print(CMD_CTX
, "Target does not support direct access "
128 "local memory. Set memory mode to MEMORY");
129 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
132 aice_memory_mode(aice
, nds32
->memory
.mode
);
134 if (strcmp(CMD_ARGV
[0], "auto") == 0) {
135 nds32
->memory
.mode
= NDS_MEMORY_SELECT_AUTO
;
136 } else if (strcmp(CMD_ARGV
[0], "mem") == 0) {
137 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
138 } else if (strcmp(CMD_ARGV
[0], "ilm") == 0) {
139 if (nds32
->memory
.ilm_base
== 0)
140 command_print(CMD_CTX
, "Target does not support ILM");
142 nds32
->memory
.mode
= NDS_MEMORY_SELECT_ILM
;
143 } else if (strcmp(CMD_ARGV
[0], "dlm") == 0) {
144 if (nds32
->memory
.dlm_base
== 0)
145 command_print(CMD_CTX
, "Target does not support DLM");
147 nds32
->memory
.mode
= NDS_MEMORY_SELECT_DLM
;
151 aice_memory_mode(aice
, nds32
->memory
.mode
);
155 command_print(CMD_CTX
, "memory mode: %s",
156 NDS_MEMORY_SELECT_NAME
[nds32
->memory
.mode
]);
161 COMMAND_HANDLER(handle_nds32_cache_command
)
163 struct target
*target
= get_current_target(CMD_CTX
);
164 struct nds32
*nds32
= target_to_nds32(target
);
165 struct aice_port_s
*aice
= target_to_aice(target
);
166 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
167 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
170 if (!is_nds32(nds32
)) {
171 command_print(CMD_CTX
, "current target isn't an Andes core");
177 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
178 if ((dcache
->line_size
!= 0) && (dcache
->enable
== true)) {
180 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
181 if (result
!= ERROR_OK
) {
182 command_print(CMD_CTX
, "Write back data cache...failed");
186 command_print(CMD_CTX
, "Write back data cache...done");
189 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
190 if (result
!= ERROR_OK
) {
191 command_print(CMD_CTX
, "Invalidate data cache...failed");
195 command_print(CMD_CTX
, "Invalidate data cache...done");
197 if (dcache
->line_size
== 0)
198 command_print(CMD_CTX
, "No data cache");
200 command_print(CMD_CTX
, "Data cache disabled");
203 if ((icache
->line_size
!= 0) && (icache
->enable
== true)) {
205 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
206 if (result
!= ERROR_OK
) {
207 command_print(CMD_CTX
, "Invalidate instruction cache...failed");
211 command_print(CMD_CTX
, "Invalidate instruction cache...done");
213 if (icache
->line_size
== 0)
214 command_print(CMD_CTX
, "No instruction cache");
216 command_print(CMD_CTX
, "Instruction cache disabled");
219 command_print(CMD_CTX
, "No valid parameter");
225 COMMAND_HANDLER(handle_nds32_icache_command
)
227 struct target
*target
= get_current_target(CMD_CTX
);
228 struct nds32
*nds32
= target_to_nds32(target
);
229 struct aice_port_s
*aice
= target_to_aice(target
);
230 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
233 if (!is_nds32(nds32
)) {
234 command_print(CMD_CTX
, "current target isn't an Andes core");
240 if (icache
->line_size
== 0) {
241 command_print(CMD_CTX
, "No instruction cache");
245 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
246 if (icache
->enable
== true) {
248 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
249 if (result
!= ERROR_OK
) {
250 command_print(CMD_CTX
, "Invalidate instruction cache...failed");
254 command_print(CMD_CTX
, "Invalidate instruction cache...done");
256 command_print(CMD_CTX
, "Instruction cache disabled");
258 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
260 nds32_get_mapped_reg(nds32
, IR8
, &value
);
261 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x1);
262 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
264 nds32_get_mapped_reg(nds32
, IR8
, &value
);
265 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x1);
266 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
267 /* TODO: dump cache content */
269 command_print(CMD_CTX
, "No valid parameter");
276 COMMAND_HANDLER(handle_nds32_dcache_command
)
278 struct target
*target
= get_current_target(CMD_CTX
);
279 struct nds32
*nds32
= target_to_nds32(target
);
280 struct aice_port_s
*aice
= target_to_aice(target
);
281 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
284 if (!is_nds32(nds32
)) {
285 command_print(CMD_CTX
, "current target isn't an Andes core");
291 if (dcache
->line_size
== 0) {
292 command_print(CMD_CTX
, "No data cache");
296 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
297 if (dcache
->enable
== true) {
299 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
300 if (result
!= ERROR_OK
) {
301 command_print(CMD_CTX
, "Write back data cache...failed");
305 command_print(CMD_CTX
, "Write back data cache...done");
308 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
309 if (result
!= ERROR_OK
) {
310 command_print(CMD_CTX
, "Invalidate data cache...failed");
314 command_print(CMD_CTX
, "Invalidate data cache...done");
316 command_print(CMD_CTX
, "Data cache disabled");
318 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
320 nds32_get_mapped_reg(nds32
, IR8
, &value
);
321 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x2);
322 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
324 nds32_get_mapped_reg(nds32
, IR8
, &value
);
325 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x2);
326 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
327 /* TODO: dump cache content */
329 command_print(CMD_CTX
, "No valid parameter");
336 COMMAND_HANDLER(handle_nds32_auto_break_command
)
338 struct target
*target
= get_current_target(CMD_CTX
);
339 struct nds32
*nds32
= target_to_nds32(target
);
341 if (!is_nds32(nds32
)) {
342 command_print(CMD_CTX
, "current target isn't an Andes core");
347 if (strcmp(CMD_ARGV
[0], "on") == 0)
348 nds32
->auto_convert_hw_bp
= true;
349 if (strcmp(CMD_ARGV
[0], "off") == 0)
350 nds32
->auto_convert_hw_bp
= false;
353 if (nds32
->auto_convert_hw_bp
)
354 command_print(CMD_CTX
, "convert sw break to hw break on ROM: on");
356 command_print(CMD_CTX
, "convert sw break to hw break on ROM: off");
361 COMMAND_HANDLER(handle_nds32_virtual_hosting_command
)
363 struct target
*target
= get_current_target(CMD_CTX
);
364 struct nds32
*nds32
= target_to_nds32(target
);
366 if (!is_nds32(nds32
)) {
367 command_print(CMD_CTX
, "current target isn't an Andes core");
372 if (strcmp(CMD_ARGV
[0], "on") == 0)
373 nds32
->virtual_hosting
= true;
374 if (strcmp(CMD_ARGV
[0], "off") == 0)
375 nds32
->virtual_hosting
= false;
378 if (nds32
->virtual_hosting
)
379 LOG_INFO("virtual hosting: on");
381 LOG_INFO("virtual hosting: off");
386 COMMAND_HANDLER(handle_nds32_global_stop_command
)
388 struct target
*target
= get_current_target(CMD_CTX
);
389 struct nds32
*nds32
= target_to_nds32(target
);
391 if (!is_nds32(nds32
)) {
392 command_print(CMD_CTX
, "current target isn't an Andes core");
397 if (strcmp(CMD_ARGV
[0], "on") == 0)
398 nds32
->global_stop
= true;
399 if (strcmp(CMD_ARGV
[0], "off") == 0)
400 nds32
->global_stop
= false;
403 if (nds32
->global_stop
)
404 LOG_INFO("global stop: on");
406 LOG_INFO("global stop: off");
411 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command
)
413 struct target
*target
= get_current_target(CMD_CTX
);
414 struct nds32
*nds32
= target_to_nds32(target
);
416 if (!is_nds32(nds32
)) {
417 command_print(CMD_CTX
, "current target isn't an Andes core");
422 if (strcmp(CMD_ARGV
[0], "on") == 0)
423 nds32
->soft_reset_halt
= true;
424 if (strcmp(CMD_ARGV
[0], "off") == 0)
425 nds32
->soft_reset_halt
= false;
428 if (nds32
->soft_reset_halt
)
429 LOG_INFO("soft-reset-halt: on");
431 LOG_INFO("soft-reset-halt: off");
436 COMMAND_HANDLER(handle_nds32_boot_time_command
)
438 struct target
*target
= get_current_target(CMD_CTX
);
439 struct nds32
*nds32
= target_to_nds32(target
);
441 if (!is_nds32(nds32
)) {
442 command_print(CMD_CTX
, "current target isn't an Andes core");
447 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], nds32
->boot_time
);
452 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command
)
454 struct target
*target
= get_current_target(CMD_CTX
);
455 struct nds32
*nds32
= target_to_nds32(target
);
457 if (!is_nds32(nds32
)) {
458 command_print(CMD_CTX
, "current target isn't an Andes core");
462 nds32
->edm_passcode
= strdup(CMD_ARGV
[0]);
464 LOG_INFO("set EDM passcode: %s", nds32
->edm_passcode
);
469 COMMAND_HANDLER(handle_nds32_login_edm_operation_command
)
471 struct target
*target
= get_current_target(CMD_CTX
);
472 struct nds32
*nds32
= target_to_nds32(target
);
474 if (!is_nds32(nds32
)) {
475 command_print(CMD_CTX
, "current target isn't an Andes core");
481 uint32_t misc_reg_no
;
484 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], misc_reg_no
);
485 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], data
);
487 if (nds32_edm_ops_num
>= NDS32_EDM_OPERATION_MAX_NUM
)
490 /* Just save the operation. Execute it in nds32_login() */
491 nds32_edm_ops
[nds32_edm_ops_num
].reg_no
= misc_reg_no
;
492 nds32_edm_ops
[nds32_edm_ops_num
].value
= data
;
500 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command
)
502 struct target
*target
= get_current_target(CMD_CTX
);
503 struct nds32
*nds32
= target_to_nds32(target
);
505 if (!is_nds32(nds32
)) {
506 command_print(CMD_CTX
, "current target isn't an Andes core");
511 if (strcmp(CMD_ARGV
[0], "on") == 0)
512 nds32
->reset_halt_as_examine
= true;
513 if (strcmp(CMD_ARGV
[0], "off") == 0)
514 nds32
->reset_halt_as_examine
= false;
520 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command
)
522 struct target
*target
= get_current_target(CMD_CTX
);
523 struct nds32
*nds32
= target_to_nds32(target
);
525 if (!is_nds32(nds32
)) {
526 command_print(CMD_CTX
, "current target isn't an Andes core");
531 if (strcmp(CMD_ARGV
[0], "on") == 0)
532 nds32
->keep_target_edm_ctl
= true;
533 if (strcmp(CMD_ARGV
[0], "off") == 0)
534 nds32
->keep_target_edm_ctl
= false;
540 COMMAND_HANDLER(handle_nds32_decode_command
)
542 struct target
*target
= get_current_target(CMD_CTX
);
543 struct nds32
*nds32
= target_to_nds32(target
);
545 if (!is_nds32(nds32
)) {
546 command_print(CMD_CTX
, "current target isn't an Andes core");
557 struct nds32_instruction instruction
;
559 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
560 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], insn_count
);
564 while (i
< insn_count
) {
565 if (ERROR_OK
!= nds32_read_opcode(nds32
, read_addr
, &opcode
))
567 if (ERROR_OK
!= nds32_evaluate_opcode(nds32
, opcode
,
568 read_addr
, &instruction
))
571 command_print(CMD_CTX
, "%s", instruction
.text
);
573 read_addr
+= instruction
.instruction_size
;
576 } else if (CMD_ARGC
== 1) {
580 struct nds32_instruction instruction
;
582 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
584 if (ERROR_OK
!= nds32_read_opcode(nds32
, addr
, &opcode
))
586 if (ERROR_OK
!= nds32_evaluate_opcode(nds32
, opcode
, addr
, &instruction
))
589 command_print(CMD_CTX
, "%s", instruction
.text
);
596 COMMAND_HANDLER(handle_nds32_word_access_mem_command
)
598 struct target
*target
= get_current_target(CMD_CTX
);
599 struct nds32
*nds32
= target_to_nds32(target
);
601 if (!is_nds32(nds32
)) {
602 command_print(CMD_CTX
, "current target isn't an Andes core");
607 if (strcmp(CMD_ARGV
[0], "on") == 0)
608 nds32
->word_access_mem
= true;
609 if (strcmp(CMD_ARGV
[0], "off") == 0)
610 nds32
->word_access_mem
= false;
616 COMMAND_HANDLER(handle_nds32_query_target_command
)
618 struct target
*target
= get_current_target(CMD_CTX
);
619 struct nds32
*nds32
= target_to_nds32(target
);
621 if (!is_nds32(nds32
)) {
622 command_print(CMD_CTX
, "current target isn't an Andes core");
626 command_print(CMD_CTX
, "OCD");
631 COMMAND_HANDLER(handle_nds32_query_endian_command
)
633 struct target
*target
= get_current_target(CMD_CTX
);
634 struct nds32
*nds32
= target_to_nds32(target
);
636 if (!is_nds32(nds32
)) {
637 command_print(CMD_CTX
, "current target isn't an Andes core");
642 nds32_get_mapped_reg(nds32
, IR0
, &value_psw
);
644 if (value_psw
& 0x20)
645 command_print(CMD_CTX
, "BE");
647 command_print(CMD_CTX
, "LE");
652 COMMAND_HANDLER(handle_nds32_query_cpuid_command
)
654 struct target
*target
= get_current_target(CMD_CTX
);
655 struct nds32
*nds32
= target_to_nds32(target
);
657 if (!is_nds32(nds32
)) {
658 command_print(CMD_CTX
, "current target isn't an Andes core");
662 command_print(CMD_CTX
, "CPUID: %s", target_name(target
));
667 static int jim_nds32_bulk_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
669 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
672 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
675 Jim_SetResultFormatted(goi
.interp
,
676 "usage: %s <address> <count> <data>", cmd_name
);
682 e
= Jim_GetOpt_Wide(&goi
, &address
);
687 e
= Jim_GetOpt_Wide(&goi
, &count
);
691 uint32_t *data
= malloc(count
* sizeof(uint32_t));
693 for (i
= 0; i
< count
; i
++) {
695 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
698 data
[i
] = (uint32_t)tmp
;
701 /* all args must be consumed */
705 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
708 result
= target_write_buffer(target
, address
, count
* 4, (const uint8_t *)data
);
715 static int jim_nds32_multi_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
717 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
720 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
723 Jim_SetResultFormatted(goi
.interp
,
724 "usage: %s # of pairs [<address> <data>]+", cmd_name
);
729 jim_wide num_of_pairs
;
730 e
= Jim_GetOpt_Wide(&goi
, &num_of_pairs
);
734 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
735 struct aice_port_s
*aice
= target_to_aice(target
);
741 aice_pack_command(aice
, true);
742 for (i
= 0; i
< num_of_pairs
; i
++) {
744 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
747 address
= (uint32_t)tmp
;
749 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
752 data
= (uint32_t)tmp
;
754 result
= target_write_buffer(target
, address
, 4, (const uint8_t *)&data
);
755 if (result
!= ERROR_OK
)
758 aice_pack_command(aice
, false);
760 /* all args must be consumed */
767 static int jim_nds32_bulk_read(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
769 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
772 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
775 Jim_SetResultFormatted(goi
.interp
,
776 "usage: %s <address> <count>", cmd_name
);
782 e
= Jim_GetOpt_Wide(&goi
, &address
);
787 e
= Jim_GetOpt_Wide(&goi
, &count
);
791 /* all args must be consumed */
795 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
796 uint32_t *data
= malloc(count
* sizeof(uint32_t));
798 result
= target_read_buffer(target
, address
, count
* 4, (uint8_t *)data
);
802 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
803 for (i
= 0; i
< count
; i
++) {
804 sprintf(data_str
, "0x%08x ", data
[i
]);
805 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
813 static int jim_nds32_read_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
815 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
818 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
821 Jim_SetResultFormatted(goi
.interp
,
822 "usage: %s <edm_sr_name>", cmd_name
);
829 e
= Jim_GetOpt_String(&goi
, &edm_sr_name
, &edm_sr_name_len
);
833 /* all args must be consumed */
837 uint32_t edm_sr_number
;
838 uint32_t edm_sr_value
;
839 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
840 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
841 else if (strncmp(edm_sr_name
, "edmsw", edm_sr_name_len
) == 0)
842 edm_sr_number
= NDS_EDM_SR_EDMSW
;
846 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
847 struct aice_port_s
*aice
= target_to_aice(target
);
850 aice_read_debug_reg(aice
, edm_sr_number
, &edm_sr_value
);
852 sprintf(data_str
, "0x%08x", edm_sr_value
);
853 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
854 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
859 static int jim_nds32_write_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
861 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
864 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
867 Jim_SetResultFormatted(goi
.interp
,
868 "usage: %s <edm_sr_name> <value>", cmd_name
);
875 e
= Jim_GetOpt_String(&goi
, &edm_sr_name
, &edm_sr_name_len
);
880 e
= Jim_GetOpt_Wide(&goi
, &value
);
884 /* all args must be consumed */
888 uint32_t edm_sr_number
;
889 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
890 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
894 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
895 struct aice_port_s
*aice
= target_to_aice(target
);
897 aice_write_debug_reg(aice
, edm_sr_number
, value
);
902 static const struct command_registration nds32_query_command_handlers
[] = {
905 .handler
= handle_nds32_query_target_command
,
906 .mode
= COMMAND_EXEC
,
908 .help
= "reply 'OCD' for gdb to identify server-side is OpenOCD",
912 .handler
= handle_nds32_query_endian_command
,
913 .mode
= COMMAND_EXEC
,
915 .help
= "query target endian",
919 .handler
= handle_nds32_query_cpuid_command
,
920 .mode
= COMMAND_EXEC
,
922 .help
= "query CPU ID",
925 COMMAND_REGISTRATION_DONE
928 static const struct command_registration nds32_exec_command_handlers
[] = {
931 .handler
= handle_nds32_dssim_command
,
932 .mode
= COMMAND_EXEC
,
933 .usage
= "['on'|'off']",
934 .help
= "display/change $INT_MASK.DSSIM status",
937 .name
= "mem_access",
938 .handler
= handle_nds32_memory_access_command
,
939 .mode
= COMMAND_EXEC
,
940 .usage
= "['bus'|'cpu']",
941 .help
= "display/change memory access channel",
945 .handler
= handle_nds32_memory_mode_command
,
946 .mode
= COMMAND_EXEC
,
947 .usage
= "['auto'|'mem'|'ilm'|'dlm']",
948 .help
= "display/change memory mode",
952 .handler
= handle_nds32_cache_command
,
953 .mode
= COMMAND_EXEC
,
954 .usage
= "['invalidate']",
955 .help
= "cache control",
959 .handler
= handle_nds32_icache_command
,
960 .mode
= COMMAND_EXEC
,
961 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
962 .help
= "icache control",
966 .handler
= handle_nds32_dcache_command
,
967 .mode
= COMMAND_EXEC
,
968 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
969 .help
= "dcache control",
972 .name
= "auto_break",
973 .handler
= handle_nds32_auto_break_command
,
974 .mode
= COMMAND_EXEC
,
975 .usage
= "['on'|'off']",
976 .help
= "convert software breakpoints to hardware breakpoints if needed",
979 .name
= "virtual_hosting",
980 .handler
= handle_nds32_virtual_hosting_command
,
982 .usage
= "['on'|'off']",
983 .help
= "turn on/off virtual hosting",
986 .name
= "global_stop",
987 .handler
= handle_nds32_global_stop_command
,
989 .usage
= "['on'|'off']",
990 .help
= "turn on/off global stop. After turning on, every load/store" \
991 "instructions will be stopped to check memory access.",
994 .name
= "soft_reset_halt",
995 .handler
= handle_nds32_soft_reset_halt_command
,
997 .usage
= "['on'|'off']",
998 .help
= "as issuing rest-halt, to use soft-reset-halt or not." \
999 "the feature is for backward-compatible.",
1002 .name
= "boot_time",
1003 .handler
= handle_nds32_boot_time_command
,
1004 .mode
= COMMAND_CONFIG
,
1005 .usage
= "milliseconds",
1006 .help
= "set the period to wait after srst.",
1009 .name
= "login_edm_passcode",
1010 .handler
= handle_nds32_login_edm_passcode_command
,
1011 .mode
= COMMAND_CONFIG
,
1012 .usage
= "passcode",
1013 .help
= "set EDM passcode for secure MCU debugging.",
1016 .name
= "login_edm_operation",
1017 .handler
= handle_nds32_login_edm_operation_command
,
1018 .mode
= COMMAND_CONFIG
,
1019 .usage
= "login_edm_operation misc_reg_no value",
1020 .help
= "add EDM operations for secure MCU debugging.",
1023 .name
= "reset_halt_as_init",
1024 .handler
= handle_nds32_reset_halt_as_init_command
,
1025 .mode
= COMMAND_CONFIG
,
1026 .usage
= "['on'|'off']",
1027 .help
= "reset halt as openocd init.",
1030 .name
= "keep_target_edm_ctl",
1031 .handler
= handle_nds32_keep_target_edm_ctl_command
,
1032 .mode
= COMMAND_CONFIG
,
1033 .usage
= "['on'|'off']",
1034 .help
= "Backup/Restore target EDM_CTL register.",
1038 .handler
= handle_nds32_decode_command
,
1039 .mode
= COMMAND_EXEC
,
1040 .usage
= "address icount",
1041 .help
= "decode instruction.",
1044 .name
= "word_access_mem",
1045 .handler
= handle_nds32_word_access_mem_command
,
1046 .mode
= COMMAND_ANY
,
1047 .usage
= "['on'|'off']",
1048 .help
= "Always use word-aligned address to access memory.",
1051 .name
= "bulk_write",
1052 .jim_handler
= jim_nds32_bulk_write
,
1053 .mode
= COMMAND_EXEC
,
1054 .help
= "Write multiple 32-bit words to target memory",
1055 .usage
= "address count data",
1058 .name
= "multi_write",
1059 .jim_handler
= jim_nds32_multi_write
,
1060 .mode
= COMMAND_EXEC
,
1061 .help
= "Write multiple addresses/words to target memory",
1062 .usage
= "num_of_pairs [address data]+",
1065 .name
= "bulk_read",
1066 .jim_handler
= jim_nds32_bulk_read
,
1067 .mode
= COMMAND_EXEC
,
1068 .help
= "Read multiple 32-bit words from target memory",
1069 .usage
= "address count",
1072 .name
= "read_edmsr",
1073 .jim_handler
= jim_nds32_read_edm_sr
,
1074 .mode
= COMMAND_EXEC
,
1075 .help
= "Read EDM system register",
1076 .usage
= "['edmsw'|'edm_dtr']",
1079 .name
= "write_edmsr",
1080 .jim_handler
= jim_nds32_write_edm_sr
,
1081 .mode
= COMMAND_EXEC
,
1082 .help
= "Write EDM system register",
1083 .usage
= "['edm_dtr'] value",
1087 .mode
= COMMAND_EXEC
,
1088 .help
= "Andes query command group",
1090 .chain
= nds32_query_command_handlers
,
1093 COMMAND_REGISTRATION_DONE
1096 const struct command_registration nds32_command_handlers
[] = {
1099 .mode
= COMMAND_ANY
,
1100 .help
= "Andes command group",
1102 .chain
= nds32_exec_command_handlers
,
1104 COMMAND_REGISTRATION_DONE
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