src/target/nds32_reg.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2013 Andes Technology                                   *
   5  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_TARGET_NDS32_REG_H
   9 #define OPENOCD_TARGET_NDS32_REG_H
  10
  11 #define SRIDX(a, b, c)                  ((a << 7) | (b << 3) | c)
  12 #define NDS32_REGISTER_DISABLE          (0x0)
  13
  14 enum nds32_reg_number_s {
  15         R0 = 0, /* general registers */
  16         R1,
  17         R2,
  18         R3,
  19         R4,
  20         R5,
  21         R6,
  22         R7,
  23         R8,
  24         R9,
  25         R10,
  26         R11,
  27         R12,
  28         R13,
  29         R14,
  30         R15,
  31         R16,
  32         R17,
  33         R18,
  34         R19,
  35         R20,
  36         R21,
  37         R22,
  38         R23,
  39         R24,
  40         R25,
  41         R26,
  42         R27,
  43         R28,
  44         R29,
  45         R30,
  46         R31,
  47         PC,
  48         D0LO,
  49         D0HI,
  50         D1LO,
  51         D1HI,
  52         ITB,
  53         IFC_LP,
  54         CR0, /* system registers */
  55         CR1,
  56         CR2,
  57         CR3,
  58         CR4,
  59         CR5,
  60         CR6,
  61         IR0,
  62         IR1,
  63         IR2,
  64         IR3,
  65         IR4,
  66         IR5,
  67         IR6,
  68         IR7,
  69         IR8,
  70         IR9,
  71         IR10,
  72         IR11,
  73         IR12,
  74         IR13,
  75         IR14,
  76         IR15,
  77         IR16,
  78         IR17,
  79         IR18,
  80         IR19,
  81         IR20,
  82         IR21,
  83         IR22,
  84         IR23,
  85         IR24,
  86         IR25,
  87         IR26,
  88         IR27,
  89         IR28,
  90         IR29,
  91         IR30,
  92         MR0,
  93         MR1,
  94         MR2,
  95         MR3,
  96         MR4,
  97         MR5,
  98         MR6,
  99         MR7,
 100         MR8,
 101         MR9,
 102         MR10,
 103         MR11,
 104         DR0,
 105         DR1,
 106         DR2,
 107         DR3,
 108         DR4,
 109         DR5,
 110         DR6,
 111         DR7,
 112         DR8,
 113         DR9,
 114         DR10,
 115         DR11,
 116         DR12,
 117         DR13,
 118         DR14,
 119         DR15,
 120         DR16,
 121         DR17,
 122         DR18,
 123         DR19,
 124         DR20,
 125         DR21,
 126         DR22,
 127         DR23,
 128         DR24,
 129         DR25,
 130         DR26,
 131         DR27,
 132         DR28,
 133         DR29,
 134         DR30,
 135         DR31,
 136         DR32,
 137         DR33,
 138         DR34,
 139         DR35,
 140         DR36,
 141         DR37,
 142         DR38,
 143         DR39,
 144         DR40,
 145         DR41,
 146         DR42,
 147         DR43,
 148         DR44,
 149         DR45,
 150         DR46,
 151         DR47,
 152         DR48,
 153         PFR0,
 154         PFR1,
 155         PFR2,
 156         PFR3,
 157         DMAR0,
 158         DMAR1,
 159         DMAR2,
 160         DMAR3,
 161         DMAR4,
 162         DMAR5,
 163         DMAR6,
 164         DMAR7,
 165         DMAR8,
 166         DMAR9,
 167         DMAR10,
 168         RACR,
 169         FUCPR,
 170         IDR0,
 171         IDR1,
 172         SECUR0,
 173         D0L24, /* audio registers */
 174         D1L24,
 175         I0,
 176         I1,
 177         I2,
 178         I3,
 179         I4,
 180         I5,
 181         I6,
 182         I7,
 183         M1,
 184         M2,
 185         M3,
 186         M5,
 187         M6,
 188         M7,
 189         MOD,
 190         LBE,
 191         LE,
 192         LC,
 193         ADM_VBASE,
 194         SHFT_CTL0,
 195         SHFT_CTL1,
 196         CB_CTL,
 197         CBB0,
 198         CBB1,
 199         CBB2,
 200         CBB3,
 201         CBE0,
 202         CBE1,
 203         CBE2,
 204         CBE3,
 205         FPCSR, /* fpu */
 206         FPCFG,
 207         FS0,
 208         FS1,
 209         FS2,
 210         FS3,
 211         FS4,
 212         FS5,
 213         FS6,
 214         FS7,
 215         FS8,
 216         FS9,
 217         FS10,
 218         FS11,
 219         FS12,
 220         FS13,
 221         FS14,
 222         FS15,
 223         FS16,
 224         FS17,
 225         FS18,
 226         FS19,
 227         FS20,
 228         FS21,
 229         FS22,
 230         FS23,
 231         FS24,
 232         FS25,
 233         FS26,
 234         FS27,
 235         FS28,
 236         FS29,
 237         FS30,
 238         FS31,
 239         FD0,
 240         FD1,
 241         FD2,
 242         FD3,
 243         FD4,
 244         FD5,
 245         FD6,
 246         FD7,
 247         FD8,
 248         FD9,
 249         FD10,
 250         FD11,
 251         FD12,
 252         FD13,
 253         FD14,
 254         FD15,
 255         FD16,
 256         FD17,
 257         FD18,
 258         FD19,
 259         FD20,
 260         FD21,
 261         FD22,
 262         FD23,
 263         FD24,
 264         FD25,
 265         FD26,
 266         FD27,
 267         FD28,
 268         FD29,
 269         FD30,
 270         FD31,
 271
 272         TOTAL_REG_NUM,
 273 };
 274
 275 enum nds32_reg_type_s {
 276         NDS32_REG_TYPE_GPR = 0,
 277         NDS32_REG_TYPE_SPR,
 278         NDS32_REG_TYPE_CR,
 279         NDS32_REG_TYPE_IR,
 280         NDS32_REG_TYPE_MR,
 281         NDS32_REG_TYPE_DR,
 282         NDS32_REG_TYPE_PFR,
 283         NDS32_REG_TYPE_DMAR,
 284         NDS32_REG_TYPE_RACR,
 285         NDS32_REG_TYPE_IDR,
 286         NDS32_REG_TYPE_AUMR,
 287         NDS32_REG_TYPE_SECURE,
 288         NDS32_REG_TYPE_FPU,
 289 };
 290
 291 struct nds32_reg_s {
 292         const char *simple_mnemonic;
 293         const char *symbolic_mnemonic;
 294         uint32_t sr_index;
 295         enum nds32_reg_type_s type;
 296         uint8_t size;
 297 };
 298
 299 struct nds32_reg_exception_s {
 300         uint32_t reg_num;
 301         uint32_t ex_value_bit_pos;
 302         uint32_t ex_value_mask;
 303         uint32_t ex_value;
 304 };
 305
 306 void nds32_reg_init(void);
 307 uint32_t nds32_reg_sr_index(uint32_t number);
 308 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
 309 uint8_t nds32_reg_size(uint32_t number);
 310 const char *nds32_reg_simple_name(uint32_t number);
 311 const char *nds32_reg_symbolic_name(uint32_t number);
 312 bool nds32_reg_exception(uint32_t number, uint32_t value);
 313
 314 #endif /* OPENOCD_TARGET_NDS32_REG_H */