1 /***************************************************************************
2 * Copyright (C) 2013-2014 by Franck Jullien *
5 * Inspired from adv_jtag_bridge which is: *
6 * Copyright (C) 2008-2010 Nathan Yawn *
7 * nyawn@opencores.net *
9 * And the Mohor interface version of this file which is: *
10 * Copyright (C) 2011 by Julius Baxter *
11 * julius@opencores.org *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 ***************************************************************************/
31 #include "jsp_server.h"
33 #include <target/target.h>
34 #include <jtag/jtag.h>
36 #define JSP_BANNER "\n\r" \
37 "******************************\n\r" \
38 "** JTAG Serial Port **\n\r" \
39 "******************************\n\r" \
44 /* This an option to the adv debug unit.
45 * If this is defined, status bits will be skipped on burst
46 * reads and writes to improve download speeds.
47 * This option must match the RTL configured option.
49 #define ADBG_USE_HISPEED 1
51 /* This an option to the adv debug unit.
52 * If this is defined, the JTAG Serial Port Server is started.
53 * This option must match the RTL configured option.
55 #define ENABLE_JSP_SERVER 2
57 /* Define this if you intend to use the JSP in a system with multiple
58 * devices on the JTAG chain
60 #define ENABLE_JSP_MULTI 4
62 /* Definitions for the top-level debug unit. This really just consists
63 * of a single register, used to select the active debug module ("chain").
65 #define DBG_MODULE_SELECT_REG_SIZE 2
66 #define DBG_MAX_MODULES 4
74 /* CPU control register bits mask */
75 #define DBG_CPU_CR_STALL 0x01
76 #define DBG_CPU_CR_RESET 0x02
78 /* Polynomial for the CRC calculation
79 * Yes, it's backwards. Yes, this is on purpose.
80 * The hardware is designed this way to save on logic and routing,
81 * and it's really all the same to us here.
83 #define ADBG_CRC_POLY 0xedb88320
85 /* These are for the internal registers in the Wishbone module
86 * The first is the length of the index register,
87 * the indexes of the various registers are defined after that.
89 #define DBG_WB_REG_SEL_LEN 1
90 #define DBG_WB_REG_ERROR 0
92 /* Opcode definitions for the Wishbone module. */
93 #define DBG_WB_OPCODE_LEN 4
94 #define DBG_WB_CMD_NOP 0x0
95 #define DBG_WB_CMD_BWRITE8 0x1
96 #define DBG_WB_CMD_BWRITE16 0x2
97 #define DBG_WB_CMD_BWRITE32 0x3
98 #define DBG_WB_CMD_BREAD8 0x5
99 #define DBG_WB_CMD_BREAD16 0x6
100 #define DBG_WB_CMD_BREAD32 0x7
101 #define DBG_WB_CMD_IREG_WR 0x9
102 #define DBG_WB_CMD_IREG_SEL 0xd
104 /* Internal register definitions for the CPU0 module. */
105 #define DBG_CPU0_REG_SEL_LEN 1
106 #define DBG_CPU0_REG_STATUS 0
108 /* Opcode definitions for the first CPU module. */
109 #define DBG_CPU0_OPCODE_LEN 4
110 #define DBG_CPU0_CMD_NOP 0x0
111 #define DBG_CPU0_CMD_BWRITE32 0x3
112 #define DBG_CPU0_CMD_BREAD32 0x7
113 #define DBG_CPU0_CMD_IREG_WR 0x9
114 #define DBG_CPU0_CMD_IREG_SEL 0xd
116 /* Internal register definitions for the CPU1 module. */
117 #define DBG_CPU1_REG_SEL_LEN 1
118 #define DBG_CPU1_REG_STATUS 0
120 /* Opcode definitions for the second CPU module. */
121 #define DBG_CPU1_OPCODE_LEN 4
122 #define DBG_CPU1_CMD_NOP 0x0
123 #define DBG_CPU1_CMD_BWRITE32 0x3
124 #define DBG_CPU1_CMD_BREAD32 0x7
125 #define DBG_CPU1_CMD_IREG_WR 0x9
126 #define DBG_CPU1_CMD_IREG_SEL 0xd
128 #define MAX_READ_STATUS_WAIT 10
129 #define MAX_READ_BUSY_RETRY 2
130 #define MAX_READ_CRC_RETRY 2
131 #define MAX_WRITE_CRC_RETRY 2
132 #define BURST_READ_READY 1
133 #define MAX_BUS_ERRORS 2
135 #define MAX_BURST_SIZE (4 * 1024)
137 #define STATUS_BYTES 1
140 static struct or1k_du or1k_du_adv
;
142 static const char * const chain_name
[] = {"WISHBONE", "CPU0", "CPU1", "JSP"};
144 static uint32_t adbg_compute_crc(uint32_t crc
, uint32_t data_in
,
147 for (int i
= 0; i
< length_bits
; i
++) {
149 d
= ((data_in
>> i
) & 0x1) ? 0xffffffff : 0;
150 c
= (crc
& 0x1) ? 0xffffffff : 0;
152 crc
= crc
^ ((d
^ c
) & ADBG_CRC_POLY
);
158 static int find_status_bit(void *_buf
, int len
)
165 while (!(buf
[i
] & (1 << count
++)) && (i
< len
)) {
173 ret
= (i
* 8) + count
;
178 static int or1k_adv_jtag_init(struct or1k_jtag
*jtag_info
)
180 struct or1k_tap_ip
*tap_ip
= jtag_info
->tap_ip
;
182 int retval
= tap_ip
->init(jtag_info
);
183 if (retval
!= ERROR_OK
) {
184 LOG_ERROR("TAP initialization failed");
188 /* TAP is now configured to communicate with debug interface */
189 jtag_info
->or1k_jtag_inited
= 1;
191 /* TAP reset - not sure what state debug module chain is in now */
192 jtag_info
->or1k_jtag_module_selected
= DC_NONE
;
194 jtag_info
->current_reg_idx
= malloc(DBG_MAX_MODULES
* sizeof(uint8_t));
195 memset(jtag_info
->current_reg_idx
, 0, DBG_MAX_MODULES
* sizeof(uint8_t));
197 if (or1k_du_adv
.options
& ADBG_USE_HISPEED
)
198 LOG_INFO("adv debug unit is configured with option ADBG_USE_HISPEED");
200 if (or1k_du_adv
.options
& ENABLE_JSP_SERVER
) {
201 if (or1k_du_adv
.options
& ENABLE_JSP_MULTI
)
202 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_MULTI");
203 LOG_INFO("adv debug unit is configured with option ENABLE_JSP_SERVER");
204 retval
= jsp_init(jtag_info
, JSP_BANNER
);
205 if (retval
!= ERROR_OK
) {
206 LOG_ERROR("Couldn't start the JSP server");
211 LOG_DEBUG("Init done");
217 /* Selects one of the modules in the debug unit
218 * (e.g. wishbone unit, CPU0, etc.)
220 static int adbg_select_module(struct or1k_jtag
*jtag_info
, int chain
)
222 if (jtag_info
->or1k_jtag_module_selected
== chain
)
225 /* MSB of the data out must be set to 1, indicating a module
228 uint8_t data
= chain
| (1 << DBG_MODULE_SELECT_REG_SIZE
);
230 LOG_DEBUG("Select module: %s", chain_name
[chain
]);
232 struct scan_field field
;
234 field
.num_bits
= (DBG_MODULE_SELECT_REG_SIZE
+ 1);
235 field
.out_value
= &data
;
236 field
.in_value
= NULL
;
237 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
239 int retval
= jtag_execute_queue();
240 if (retval
!= ERROR_OK
)
243 jtag_info
->or1k_jtag_module_selected
= chain
;
248 /* Set the index of the desired register in the currently selected module
249 * 1 bit module select command
253 static int adbg_select_ctrl_reg(struct or1k_jtag
*jtag_info
, uint8_t regidx
)
259 /* If this reg is already selected, don't do a JTAG transaction */
260 if (jtag_info
->current_reg_idx
[jtag_info
->or1k_jtag_module_selected
] == regidx
)
263 switch (jtag_info
->or1k_jtag_module_selected
) {
265 index_len
= DBG_WB_REG_SEL_LEN
;
266 opcode
= DBG_WB_CMD_IREG_SEL
;
267 opcode_len
= DBG_WB_OPCODE_LEN
;
270 index_len
= DBG_CPU0_REG_SEL_LEN
;
271 opcode
= DBG_CPU0_CMD_IREG_SEL
;
272 opcode_len
= DBG_CPU0_OPCODE_LEN
;
275 index_len
= DBG_CPU1_REG_SEL_LEN
;
276 opcode
= DBG_CPU1_CMD_IREG_SEL
;
277 opcode_len
= DBG_CPU1_OPCODE_LEN
;
280 LOG_ERROR("Illegal debug chain selected (%i) while selecting control register",
281 jtag_info
->or1k_jtag_module_selected
);
285 /* MSB must be 0 to access modules */
286 uint32_t data
= (opcode
& ~(1 << opcode_len
)) << index_len
;
289 struct scan_field field
;
291 field
.num_bits
= (opcode_len
+ 1) + index_len
;
292 field
.out_value
= (uint8_t *)&data
;
293 field
.in_value
= NULL
;
294 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
296 int retval
= jtag_execute_queue();
297 if (retval
!= ERROR_OK
)
300 jtag_info
->current_reg_idx
[jtag_info
->or1k_jtag_module_selected
] = regidx
;
305 /* Write control register (internal to the debug unit) */
306 static int adbg_ctrl_write(struct or1k_jtag
*jtag_info
, uint8_t regidx
,
307 uint32_t *cmd_data
, int length_bits
)
313 LOG_DEBUG("Write control register %" PRId8
": 0x%08" PRIx32
, regidx
, cmd_data
[0]);
315 int retval
= adbg_select_ctrl_reg(jtag_info
, regidx
);
316 if (retval
!= ERROR_OK
) {
317 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
321 switch (jtag_info
->or1k_jtag_module_selected
) {
323 index_len
= DBG_WB_REG_SEL_LEN
;
324 opcode
= DBG_WB_CMD_IREG_WR
;
325 opcode_len
= DBG_WB_OPCODE_LEN
;
328 index_len
= DBG_CPU0_REG_SEL_LEN
;
329 opcode
= DBG_CPU0_CMD_IREG_WR
;
330 opcode_len
= DBG_CPU0_OPCODE_LEN
;
333 index_len
= DBG_CPU1_REG_SEL_LEN
;
334 opcode
= DBG_CPU1_CMD_IREG_WR
;
335 opcode_len
= DBG_CPU1_OPCODE_LEN
;
338 LOG_ERROR("Illegal debug chain selected (%i) while doing control write",
339 jtag_info
->or1k_jtag_module_selected
);
343 struct scan_field field
[2];
345 /* MSB must be 0 to access modules */
346 uint32_t data
= (opcode
& ~(1 << opcode_len
)) << index_len
;
349 field
[0].num_bits
= length_bits
;
350 field
[0].out_value
= (uint8_t *)cmd_data
;
351 field
[0].in_value
= NULL
;
353 field
[1].num_bits
= (opcode_len
+ 1) + index_len
;
354 field
[1].out_value
= (uint8_t *)&data
;
355 field
[1].in_value
= NULL
;
357 jtag_add_dr_scan(jtag_info
->tap
, 2, field
, TAP_IDLE
);
359 return jtag_execute_queue();
362 /* Reads control register (internal to the debug unit) */
363 static int adbg_ctrl_read(struct or1k_jtag
*jtag_info
, uint32_t regidx
,
364 uint32_t *data
, int length_bits
)
367 int retval
= adbg_select_ctrl_reg(jtag_info
, regidx
);
368 if (retval
!= ERROR_OK
) {
369 LOG_ERROR("Error while calling adbg_select_ctrl_reg");
376 /* There is no 'read' command, We write a NOP to read */
377 switch (jtag_info
->or1k_jtag_module_selected
) {
379 opcode
= DBG_WB_CMD_NOP
;
380 opcode_len
= DBG_WB_OPCODE_LEN
;
383 opcode
= DBG_CPU0_CMD_NOP
;
384 opcode_len
= DBG_CPU0_OPCODE_LEN
;
387 opcode
= DBG_CPU1_CMD_NOP
;
388 opcode_len
= DBG_CPU1_OPCODE_LEN
;
391 LOG_ERROR("Illegal debug chain selected (%i) while doing control read",
392 jtag_info
->or1k_jtag_module_selected
);
396 /* Zero MSB = op for module, not top-level debug unit */
397 uint32_t outdata
= opcode
& ~(0x1 << opcode_len
);
399 struct scan_field field
[2];
401 field
[0].num_bits
= length_bits
;
402 field
[0].out_value
= NULL
;
403 field
[0].in_value
= (uint8_t *)data
;
405 field
[1].num_bits
= opcode_len
+ 1;
406 field
[1].out_value
= (uint8_t *)&outdata
;
407 field
[1].in_value
= NULL
;
409 jtag_add_dr_scan(jtag_info
->tap
, 2, field
, TAP_IDLE
);
411 return jtag_execute_queue();
414 /* sends out a burst command to the selected module in the debug unit (MSB to LSB):
415 * 1-bit module command
418 * 16-bit length (of the burst, in words)
420 static int adbg_burst_command(struct or1k_jtag
*jtag_info
, uint32_t opcode
,
421 uint32_t address
, uint16_t length_words
)
425 /* Set up the data */
426 data
[0] = length_words
| (address
<< 16);
427 /* MSB must be 0 to access modules */
428 data
[1] = ((address
>> 16) | ((opcode
& 0xf) << 16)) & ~(0x1 << 20);
430 struct scan_field field
;
433 field
.out_value
= (uint8_t *)&data
[0];
434 field
.in_value
= NULL
;
436 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
438 return jtag_execute_queue();
441 static int adbg_wb_burst_read(struct or1k_jtag
*jtag_info
, int size
,
442 int count
, uint32_t start_address
, uint8_t *data
)
444 int retry_full_crc
= 0;
445 int retry_full_busy
= 0;
449 LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32
,
450 size
, count
, start_address
);
452 /* Select the appropriate opcode */
453 switch (jtag_info
->or1k_jtag_module_selected
) {
456 opcode
= DBG_WB_CMD_BREAD8
;
458 opcode
= DBG_WB_CMD_BREAD16
;
460 opcode
= DBG_WB_CMD_BREAD32
;
462 LOG_WARNING("Tried burst read with invalid word size (%d),"
463 "defaulting to 4-byte words", size
);
464 opcode
= DBG_WB_CMD_BREAD32
;
469 opcode
= DBG_CPU0_CMD_BREAD32
;
471 LOG_WARNING("Tried burst read with invalid word size (%d),"
472 "defaulting to 4-byte words", size
);
473 opcode
= DBG_CPU0_CMD_BREAD32
;
478 opcode
= DBG_CPU1_CMD_BREAD32
;
480 LOG_WARNING("Tried burst read with invalid word size (%d),"
481 "defaulting to 4-byte words", size
);
482 opcode
= DBG_CPU0_CMD_BREAD32
;
486 LOG_ERROR("Illegal debug chain selected (%i) while doing burst read",
487 jtag_info
->or1k_jtag_module_selected
);
491 int total_size_bytes
= count
* size
;
492 struct scan_field field
;
493 uint8_t *in_buffer
= malloc(total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
);
497 /* Send the BURST READ command, returns TAP to idle state */
498 retval
= adbg_burst_command(jtag_info
, opcode
, start_address
, count
);
499 if (retval
!= ERROR_OK
)
502 field
.num_bits
= (total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
) * 8;
503 field
.out_value
= NULL
;
504 field
.in_value
= in_buffer
;
506 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
508 retval
= jtag_execute_queue();
509 if (retval
!= ERROR_OK
)
512 /* Look for the start bit in the first (STATUS_BYTES * 8) bits */
513 int shift
= find_status_bit(in_buffer
, STATUS_BYTES
);
515 /* We expect the status bit to be in the first byte */
517 if (retry_full_busy
++ < MAX_READ_BUSY_RETRY
) {
518 LOG_WARNING("Burst read timed out");
519 goto retry_read_full
;
521 LOG_ERROR("Burst read failed");
527 buffer_shr(in_buffer
, total_size_bytes
+ CRC_LEN
+ STATUS_BYTES
, shift
);
530 memcpy(data
, in_buffer
, total_size_bytes
);
531 memcpy(&crc_read
, &in_buffer
[total_size_bytes
], 4);
533 uint32_t crc_calc
= 0xffffffff;
534 for (int i
= 0; i
< total_size_bytes
; i
++)
535 crc_calc
= adbg_compute_crc(crc_calc
, data
[i
], 8);
537 if (crc_calc
!= crc_read
) {
538 LOG_WARNING("CRC ERROR! Computed 0x%08" PRIx32
", read CRC 0x%08" PRIx32
, crc_calc
, crc_read
);
539 if (retry_full_crc
++ < MAX_READ_CRC_RETRY
)
540 goto retry_read_full
;
542 LOG_ERROR("Burst read failed");
547 LOG_DEBUG("CRC OK!");
549 /* Now, read the error register, and retry/recompute as necessary */
550 if (jtag_info
->or1k_jtag_module_selected
== DC_WISHBONE
&&
551 !(or1k_du_adv
.options
& ADBG_USE_HISPEED
)) {
553 uint32_t err_data
[2] = {0, 0};
555 int bus_error_retries
= 0;
557 /* First, just get 1 bit...read address only if necessary */
558 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
559 if (retval
!= ERROR_OK
)
562 /* Then we have a problem */
563 if (err_data
[0] & 0x1) {
565 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 33);
566 if (retval
!= ERROR_OK
)
569 addr
= (err_data
[0] >> 1) | (err_data
[1] << 31);
570 LOG_WARNING("WB bus error during burst read, address 0x%08" PRIx32
", retrying!", addr
);
573 if (bus_error_retries
> MAX_BUS_ERRORS
) {
574 LOG_ERROR("Max WB bus errors reached during burst read");
579 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
580 /* Write 1 bit, to reset the error register */
582 retval
= adbg_ctrl_write(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
583 if (retval
!= ERROR_OK
)
586 goto retry_read_full
;
596 /* Set up and execute a burst write to a contiguous set of addresses */
597 static int adbg_wb_burst_write(struct or1k_jtag
*jtag_info
, const uint8_t *data
, int size
,
598 int count
, unsigned long start_address
)
600 int retry_full_crc
= 0;
604 LOG_DEBUG("Doing burst write, word size %d, word count %d,"
605 "start address 0x%08lx", size
, count
, start_address
);
607 /* Select the appropriate opcode */
608 switch (jtag_info
->or1k_jtag_module_selected
) {
611 opcode
= DBG_WB_CMD_BWRITE8
;
613 opcode
= DBG_WB_CMD_BWRITE16
;
615 opcode
= DBG_WB_CMD_BWRITE32
;
617 LOG_DEBUG("Tried WB burst write with invalid word size (%d),"
618 "defaulting to 4-byte words", size
);
619 opcode
= DBG_WB_CMD_BWRITE32
;
624 opcode
= DBG_CPU0_CMD_BWRITE32
;
626 LOG_DEBUG("Tried CPU0 burst write with invalid word size (%d),"
627 "defaulting to 4-byte words", size
);
628 opcode
= DBG_CPU0_CMD_BWRITE32
;
633 opcode
= DBG_CPU1_CMD_BWRITE32
;
635 LOG_DEBUG("Tried CPU1 burst write with invalid word size (%d),"
636 "defaulting to 4-byte words", size
);
637 opcode
= DBG_CPU0_CMD_BWRITE32
;
641 LOG_ERROR("Illegal debug chain selected (%i) while doing burst write",
642 jtag_info
->or1k_jtag_module_selected
);
648 /* Send the BURST WRITE command, returns TAP to idle state */
649 retval
= adbg_burst_command(jtag_info
, opcode
, start_address
, count
);
650 if (retval
!= ERROR_OK
)
653 struct scan_field field
[3];
655 /* Write a start bit so it knows when to start counting */
657 field
[0].num_bits
= 1;
658 field
[0].out_value
= &value
;
659 field
[0].in_value
= NULL
;
661 uint32_t crc_calc
= 0xffffffff;
662 for (int i
= 0; i
< (count
* size
); i
++)
663 crc_calc
= adbg_compute_crc(crc_calc
, data
[i
], 8);
665 field
[1].num_bits
= count
* size
* 8;
666 field
[1].out_value
= data
;
667 field
[1].in_value
= NULL
;
669 field
[2].num_bits
= 32;
670 field
[2].out_value
= (uint8_t *)&crc_calc
;
671 field
[2].in_value
= NULL
;
673 jtag_add_dr_scan(jtag_info
->tap
, 3, field
, TAP_DRSHIFT
);
675 /* Read the 'CRC match' bit, and go to idle */
676 field
[0].num_bits
= 1;
677 field
[0].out_value
= NULL
;
678 field
[0].in_value
= &value
;
679 jtag_add_dr_scan(jtag_info
->tap
, 1, field
, TAP_IDLE
);
681 retval
= jtag_execute_queue();
682 if (retval
!= ERROR_OK
)
686 LOG_WARNING("CRC ERROR! match bit after write is %" PRIi8
" (computed CRC 0x%08" PRIx32
")", value
, crc_calc
);
687 if (retry_full_crc
++ < MAX_WRITE_CRC_RETRY
)
688 goto retry_full_write
;
692 LOG_DEBUG("CRC OK!\n");
694 /* Now, read the error register, and retry/recompute as necessary */
695 if (jtag_info
->or1k_jtag_module_selected
== DC_WISHBONE
&&
696 !(or1k_du_adv
.options
& ADBG_USE_HISPEED
)) {
698 int bus_error_retries
= 0;
699 uint32_t err_data
[2] = {0, 0};
701 /* First, just get 1 bit...read address only if necessary */
702 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
703 if (retval
!= ERROR_OK
)
706 /* Then we have a problem */
707 if (err_data
[0] & 0x1) {
709 retval
= adbg_ctrl_read(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 33);
710 if (retval
!= ERROR_OK
)
713 addr
= (err_data
[0] >> 1) | (err_data
[1] << 31);
714 LOG_WARNING("WB bus error during burst write, address 0x%08" PRIx32
", retrying!", addr
);
717 if (bus_error_retries
> MAX_BUS_ERRORS
) {
718 LOG_ERROR("Max WB bus errors reached during burst read");
723 /* Don't call retry_do(), a JTAG reset won't help a WB bus error */
724 /* Write 1 bit, to reset the error register */
726 retval
= adbg_ctrl_write(jtag_info
, DBG_WB_REG_ERROR
, err_data
, 1);
727 if (retval
!= ERROR_OK
)
730 goto retry_full_write
;
737 /* Currently hard set in functions to 32-bits */
738 static int or1k_adv_jtag_read_cpu(struct or1k_jtag
*jtag_info
,
739 uint32_t addr
, int count
, uint32_t *value
)
742 if (!jtag_info
->or1k_jtag_inited
) {
743 retval
= or1k_adv_jtag_init(jtag_info
);
744 if (retval
!= ERROR_OK
)
748 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
749 if (retval
!= ERROR_OK
)
752 return adbg_wb_burst_read(jtag_info
, 4, count
, addr
, (uint8_t *)value
);
755 static int or1k_adv_jtag_write_cpu(struct or1k_jtag
*jtag_info
,
756 uint32_t addr
, int count
, const uint32_t *value
)
759 if (!jtag_info
->or1k_jtag_inited
) {
760 retval
= or1k_adv_jtag_init(jtag_info
);
761 if (retval
!= ERROR_OK
)
765 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
766 if (retval
!= ERROR_OK
)
769 return adbg_wb_burst_write(jtag_info
, (uint8_t *)value
, 4, count
, addr
);
772 static int or1k_adv_cpu_stall(struct or1k_jtag
*jtag_info
, int action
)
775 if (!jtag_info
->or1k_jtag_inited
) {
776 retval
= or1k_adv_jtag_init(jtag_info
);
777 if (retval
!= ERROR_OK
)
781 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
782 if (retval
!= ERROR_OK
)
786 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
787 if (retval
!= ERROR_OK
)
790 if (action
== CPU_STALL
)
791 cpu_cr
|= DBG_CPU_CR_STALL
;
793 cpu_cr
&= ~DBG_CPU_CR_STALL
;
795 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
796 if (retval
!= ERROR_OK
)
799 return adbg_ctrl_write(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
802 static int or1k_adv_is_cpu_running(struct or1k_jtag
*jtag_info
, int *running
)
805 if (!jtag_info
->or1k_jtag_inited
) {
806 retval
= or1k_adv_jtag_init(jtag_info
);
807 if (retval
!= ERROR_OK
)
811 int current
= jtag_info
->or1k_jtag_module_selected
;
813 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
814 if (retval
!= ERROR_OK
)
818 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
819 if (retval
!= ERROR_OK
)
822 if (cpu_cr
& DBG_CPU_CR_STALL
)
827 if (current
!= DC_NONE
) {
828 retval
= adbg_select_module(jtag_info
, current
);
829 if (retval
!= ERROR_OK
)
836 static int or1k_adv_cpu_reset(struct or1k_jtag
*jtag_info
, int action
)
839 if (!jtag_info
->or1k_jtag_inited
) {
840 retval
= or1k_adv_jtag_init(jtag_info
);
841 if (retval
!= ERROR_OK
)
845 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
846 if (retval
!= ERROR_OK
)
850 retval
= adbg_ctrl_read(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
851 if (retval
!= ERROR_OK
)
854 if (action
== CPU_RESET
)
855 cpu_cr
|= DBG_CPU_CR_RESET
;
857 cpu_cr
&= ~DBG_CPU_CR_RESET
;
859 retval
= adbg_select_module(jtag_info
, DC_CPU0
);
860 if (retval
!= ERROR_OK
)
863 return adbg_ctrl_write(jtag_info
, DBG_CPU0_REG_STATUS
, &cpu_cr
, 2);
866 static int or1k_adv_jtag_read_memory(struct or1k_jtag
*jtag_info
,
867 uint32_t addr
, uint32_t size
, int count
, uint8_t *buffer
)
869 LOG_DEBUG("Reading WB%" PRId32
" at 0x%08" PRIx32
, size
* 8, addr
);
872 if (!jtag_info
->or1k_jtag_inited
) {
873 retval
= or1k_adv_jtag_init(jtag_info
);
874 if (retval
!= ERROR_OK
)
878 retval
= adbg_select_module(jtag_info
, DC_WISHBONE
);
879 if (retval
!= ERROR_OK
)
882 int block_count_left
= count
;
883 uint32_t block_count_address
= addr
;
884 uint8_t *block_count_buffer
= buffer
;
886 while (block_count_left
) {
888 int blocks_this_round
= (block_count_left
> MAX_BURST_SIZE
) ?
889 MAX_BURST_SIZE
: block_count_left
;
891 retval
= adbg_wb_burst_read(jtag_info
, size
, blocks_this_round
,
892 block_count_address
, block_count_buffer
);
893 if (retval
!= ERROR_OK
)
896 block_count_left
-= blocks_this_round
;
897 block_count_address
+= size
* MAX_BURST_SIZE
;
898 block_count_buffer
+= size
* MAX_BURST_SIZE
;
901 /* The adv_debug_if always return words and half words in
902 * little-endian order no matter what the target endian is.
903 * So if the target endian is big, change the order.
906 struct target
*target
= jtag_info
->target
;
907 if ((target
->endianness
== TARGET_BIG_ENDIAN
) && (size
!= 1)) {
910 buf_bswap32(buffer
, buffer
, size
* count
);
913 buf_bswap16(buffer
, buffer
, size
* count
);
921 static int or1k_adv_jtag_write_memory(struct or1k_jtag
*jtag_info
,
922 uint32_t addr
, uint32_t size
, int count
, const uint8_t *buffer
)
924 LOG_DEBUG("Writing WB%" PRId32
" at 0x%08" PRIx32
, size
* 8, addr
);
927 if (!jtag_info
->or1k_jtag_inited
) {
928 retval
= or1k_adv_jtag_init(jtag_info
);
929 if (retval
!= ERROR_OK
)
933 retval
= adbg_select_module(jtag_info
, DC_WISHBONE
);
934 if (retval
!= ERROR_OK
)
937 /* The adv_debug_if wants words and half words in little-endian
938 * order no matter what the target endian is. So if the target
939 * endian is big, change the order.
943 struct target
*target
= jtag_info
->target
;
944 if ((target
->endianness
== TARGET_BIG_ENDIAN
) && (size
!= 1)) {
945 t
= malloc(count
* size
* sizeof(uint8_t));
947 LOG_ERROR("Out of memory");
953 buf_bswap32(t
, buffer
, size
* count
);
956 buf_bswap16(t
, buffer
, size
* count
);
962 int block_count_left
= count
;
963 uint32_t block_count_address
= addr
;
964 uint8_t *block_count_buffer
= (uint8_t *)buffer
;
966 while (block_count_left
) {
968 int blocks_this_round
= (block_count_left
> MAX_BURST_SIZE
) ?
969 MAX_BURST_SIZE
: block_count_left
;
971 retval
= adbg_wb_burst_write(jtag_info
, block_count_buffer
,
972 size
, blocks_this_round
,
973 block_count_address
);
974 if (retval
!= ERROR_OK
) {
980 block_count_left
-= blocks_this_round
;
981 block_count_address
+= size
* MAX_BURST_SIZE
;
982 block_count_buffer
+= size
* MAX_BURST_SIZE
;
991 int or1k_adv_jtag_jsp_xfer(struct or1k_jtag
*jtag_info
,
992 int *out_len
, unsigned char *out_buffer
,
993 int *in_len
, unsigned char *in_buffer
)
995 LOG_DEBUG("JSP transfert");
998 if (!jtag_info
->or1k_jtag_inited
)
1001 retval
= adbg_select_module(jtag_info
, DC_JSP
);
1002 if (retval
!= ERROR_OK
)
1005 /* return nb char xmit */
1010 xmitsize
= *out_len
;
1012 uint8_t out_data
[10];
1013 uint8_t in_data
[10];
1014 struct scan_field field
;
1015 int startbit
, stopbit
, wrapbit
;
1017 memset(out_data
, 0, 10);
1019 if (or1k_du_adv
.options
& ENABLE_JSP_MULTI
) {
1022 wrapbit
= (xmitsize
>> 3) & 0x1;
1023 out_data
[0] = (xmitsize
<< 5) | 0x1; /* set the start bit */
1026 /* don't copy off the end of the input array */
1027 for (i
= 0; i
< xmitsize
; i
++) {
1028 out_data
[i
+ 1] = (out_buffer
[i
] << 1) | wrapbit
;
1029 wrapbit
= (out_buffer
[i
] >> 7) & 0x1;
1033 out_data
[i
+ 1] = wrapbit
;
1035 out_data
[9] = wrapbit
;
1037 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1038 * won't treat the burst as a 'module select' command.
1040 stopbit
= !!(out_data
[9] & 0x01);
1044 /* First byte out has write count in upper nibble */
1045 out_data
[0] = 0x0 | (xmitsize
<< 4);
1047 memcpy(&out_data
[1], out_buffer
, xmitsize
);
1049 /* If the last data bit is a '1', then we need to append a '0' so the top-level module
1050 * won't treat the burst as a 'module select' command.
1052 stopbit
= !!(out_data
[8] & 0x80);
1055 field
.num_bits
= 72 + startbit
+ stopbit
;
1056 field
.out_value
= out_data
;
1057 field
.in_value
= in_data
;
1059 jtag_add_dr_scan(jtag_info
->tap
, 1, &field
, TAP_IDLE
);
1061 retval
= jtag_execute_queue();
1062 if (retval
!= ERROR_OK
)
1065 /* bytes available is in the upper nibble */
1066 *in_len
= (in_data
[0] >> 4) & 0xF;
1067 memcpy(in_buffer
, &in_data
[1], *in_len
);
1069 int bytes_free
= in_data
[0] & 0x0F;
1070 *out_len
= (bytes_free
< xmitsize
) ? bytes_free
: xmitsize
;
1075 static struct or1k_du or1k_du_adv
= {
1077 .options
= NO_OPTION
,
1078 .or1k_jtag_init
= or1k_adv_jtag_init
,
1080 .or1k_is_cpu_running
= or1k_adv_is_cpu_running
,
1081 .or1k_cpu_stall
= or1k_adv_cpu_stall
,
1082 .or1k_cpu_reset
= or1k_adv_cpu_reset
,
1084 .or1k_jtag_read_cpu
= or1k_adv_jtag_read_cpu
,
1085 .or1k_jtag_write_cpu
= or1k_adv_jtag_write_cpu
,
1087 .or1k_jtag_read_memory
= or1k_adv_jtag_read_memory
,
1088 .or1k_jtag_write_memory
= or1k_adv_jtag_write_memory
1091 int or1k_du_adv_register(void)
1093 list_add_tail(&or1k_du_adv
.list
, &du_list
);
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