src/target/riscv/riscv.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef RISCV_H
   4 #define RISCV_H
   5
   6 struct riscv_program;
   7
   8 #include <stdint.h>
   9 #include "opcodes.h"
  10 #include "gdb_regs.h"
  11 #include "jtag/jtag.h"
  12 #include "target/register.h"
  13 #include "target/semihosting_common.h"
  14 #include <helper/command.h>
  15
  16 /* The register cache is statically allocated. */
  17 #define RISCV_MAX_HARTS 1024
  18 #define RISCV_MAX_REGISTERS 5000
  19 #define RISCV_MAX_TRIGGERS 32
  20 #define RISCV_MAX_HWBPS 16
  21
  22 #define DEFAULT_COMMAND_TIMEOUT_SEC             2
  23 #define DEFAULT_RESET_TIMEOUT_SEC               30
  24
  25 #define RISCV_SATP_MODE(xlen)  ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
  26 #define RISCV_SATP_PPN(xlen)  ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
  27 #define RISCV_PGSHIFT 12
  28
  29 # define PG_MAX_LEVEL 4
  30
  31 #define RISCV_NUM_MEM_ACCESS_METHODS  3
  32
  33 extern struct target_type riscv011_target;
  34 extern struct target_type riscv013_target;
  35
  36 /*
  37  * Definitions shared by code supporting all RISC-V versions.
  38  */
  39 typedef uint64_t riscv_reg_t;
  40 typedef uint32_t riscv_insn_t;
  41 typedef uint64_t riscv_addr_t;
  42
  43 enum riscv_mem_access_method {
  44         RISCV_MEM_ACCESS_UNSPECIFIED,
  45         RISCV_MEM_ACCESS_PROGBUF,
  46         RISCV_MEM_ACCESS_SYSBUS,
  47         RISCV_MEM_ACCESS_ABSTRACT
  48 };
  49
  50 enum riscv_halt_reason {
  51         RISCV_HALT_INTERRUPT,
  52         RISCV_HALT_BREAKPOINT,
  53         RISCV_HALT_SINGLESTEP,
  54         RISCV_HALT_TRIGGER,
  55         RISCV_HALT_UNKNOWN,
  56         RISCV_HALT_GROUP,
  57         RISCV_HALT_ERROR
  58 };
  59
  60 typedef struct {
  61         struct target *target;
  62         unsigned custom_number;
  63 } riscv_reg_info_t;
  64
  65 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE       0x80
  66 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER        0x81
  67 struct riscv_sample_buf {
  68         uint8_t *buf;
  69         unsigned int used;
  70         unsigned int size;
  71 };
  72
  73 typedef struct {
  74         bool enabled;
  75         struct {
  76                 bool enabled;
  77                 target_addr_t address;
  78                 uint32_t size_bytes;
  79         } bucket[16];
  80 } riscv_sample_config_t;
  81
  82 typedef struct {
  83         struct list_head list;
  84         uint16_t low, high;
  85         char *name;
  86 } range_list_t;
  87
  88 typedef struct {
  89         unsigned dtm_version;
  90
  91         struct command_context *cmd_ctx;
  92         void *version_specific;
  93
  94         /* The hart that is currently being debugged.  Note that this is
  95          * different than the hartid that the RTOS is expected to use.  This
  96          * one will change all the time, it's more of a global argument to
  97          * every function than an actual */
  98         int current_hartid;
  99
 100         /* Single buffer that contains all register names, instead of calling
 101          * malloc for each register. Needs to be freed when reg_list is freed. */
 102         char *reg_names;
 103
 104         /* It's possible that each core has a different supported ISA set. */
 105         int xlen;
 106         riscv_reg_t misa;
 107         /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
 108         unsigned int vlenb;
 109
 110         /* The number of triggers per hart. */
 111         unsigned int trigger_count;
 112
 113         /* For each physical trigger, contains -1 if the hwbp is available, or the
 114          * unique_id of the breakpoint/watchpoint that is using it.
 115          * Note that in RTOS mode the triggers are the same across all harts the
 116          * target controls, while otherwise only a single hart is controlled. */
 117         int trigger_unique_id[RISCV_MAX_HWBPS];
 118
 119         /* The number of entries in the debug buffer. */
 120         int debug_buffer_size;
 121
 122         /* This hart contains an implicit ebreak at the end of the program buffer. */
 123         bool impebreak;
 124
 125         bool triggers_enumerated;
 126
 127         /* Decremented every scan, and when it reaches 0 we clear the learned
 128          * delays, causing them to be relearned. Used for testing. */
 129         int reset_delays_wait;
 130
 131         /* This target has been prepped and is ready to step/resume. */
 132         bool prepped;
 133         /* This target was selected using hasel. */
 134         bool selected;
 135
 136         /* Helper functions that target the various RISC-V debug spec
 137          * implementations. */
 138         int (*get_register)(struct target *target, riscv_reg_t *value, int regid);
 139         int (*set_register)(struct target *target, int regid, uint64_t value);
 140         int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
 141         int (*set_register_buf)(struct target *target, int regno,
 142                         const uint8_t *buf);
 143         int (*select_current_hart)(struct target *target);
 144         bool (*is_halted)(struct target *target);
 145         /* Resume this target, as well as every other prepped target that can be
 146          * resumed near-simultaneously. Clear the prepped flag on any target that
 147          * was resumed. */
 148         int (*resume_go)(struct target *target);
 149         int (*step_current_hart)(struct target *target);
 150         int (*on_halt)(struct target *target);
 151         /* Get this target as ready as possible to resume, without actually
 152          * resuming. */
 153         int (*resume_prep)(struct target *target);
 154         int (*halt_prep)(struct target *target);
 155         int (*halt_go)(struct target *target);
 156         int (*on_step)(struct target *target);
 157         enum riscv_halt_reason (*halt_reason)(struct target *target);
 158         int (*write_debug_buffer)(struct target *target, unsigned index,
 159                         riscv_insn_t d);
 160         riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
 161         int (*execute_debug_buffer)(struct target *target);
 162         int (*dmi_write_u64_bits)(struct target *target);
 163         void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
 164         void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
 165         void (*fill_dmi_nop_u64)(struct target *target, char *buf);
 166
 167         int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
 168         int (*authdata_write)(struct target *target, uint32_t value, unsigned int index);
 169
 170         int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
 171         int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
 172
 173         int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
 174                         uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
 175
 176         int (*sample_memory)(struct target *target,
 177                                                  struct riscv_sample_buf *buf,
 178                                                  riscv_sample_config_t *config,
 179                                                  int64_t until_ms);
 180
 181         int (*read_memory)(struct target *target, target_addr_t address,
 182                         uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
 183
 184         /* How many harts are attached to the DM that this target is attached to? */
 185         int (*hart_count)(struct target *target);
 186         unsigned (*data_bits)(struct target *target);
 187
 188         COMMAND_HELPER((*print_info), struct target *target);
 189
 190         /* Storage for vector register types. */
 191         struct reg_data_type_vector vector_uint8;
 192         struct reg_data_type_vector vector_uint16;
 193         struct reg_data_type_vector vector_uint32;
 194         struct reg_data_type_vector vector_uint64;
 195         struct reg_data_type_vector vector_uint128;
 196         struct reg_data_type type_uint8_vector;
 197         struct reg_data_type type_uint16_vector;
 198         struct reg_data_type type_uint32_vector;
 199         struct reg_data_type type_uint64_vector;
 200         struct reg_data_type type_uint128_vector;
 201         struct reg_data_type_union_field vector_fields[5];
 202         struct reg_data_type_union vector_union;
 203         struct reg_data_type type_vector;
 204
 205         /* Set when trigger registers are changed by the user. This indicates we eed
 206          * to beware that we may hit a trigger that we didn't realize had been set. */
 207         bool manual_hwbp_set;
 208
 209         /* Memory access methods to use, ordered by priority, highest to lowest. */
 210         int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS];
 211
 212         /* Different memory regions may need different methods but single configuration is applied
 213          * for all. Following flags are used to warn only once about failing memory access method. */
 214         bool mem_access_progbuf_warn;
 215         bool mem_access_sysbus_warn;
 216         bool mem_access_abstract_warn;
 217
 218         /* In addition to the ones in the standard spec, we'll also expose additional
 219          * CSRs in this list. */
 220         struct list_head expose_csr;
 221         /* Same, but for custom registers.
 222          * Custom registers are for non-standard extensions and use abstract register numbers
 223          * from range 0xc000 ... 0xffff. */
 224         struct list_head expose_custom;
 225
 226         riscv_sample_config_t sample_config;
 227         struct riscv_sample_buf sample_buf;
 228 } riscv_info_t;
 229
 230 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
 231                            unsigned int value);
 232
 233 typedef struct {
 234         uint8_t tunneled_dr_width;
 235         struct scan_field tunneled_dr[4];
 236 } riscv_bscan_tunneled_scan_context_t;
 237
 238 typedef struct {
 239         const char *name;
 240         int level;
 241         unsigned va_bits;
 242         unsigned pte_shift;
 243         unsigned vpn_shift[PG_MAX_LEVEL];
 244         unsigned vpn_mask[PG_MAX_LEVEL];
 245         unsigned pte_ppn_shift[PG_MAX_LEVEL];
 246         unsigned pte_ppn_mask[PG_MAX_LEVEL];
 247         unsigned pa_ppn_shift[PG_MAX_LEVEL];
 248         unsigned pa_ppn_mask[PG_MAX_LEVEL];
 249 } virt2phys_info_t;
 250
 251 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 252 extern int riscv_command_timeout_sec;
 253
 254 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 255 extern int riscv_reset_timeout_sec;
 256
 257 extern bool riscv_enable_virtual;
 258 extern bool riscv_ebreakm;
 259 extern bool riscv_ebreaks;
 260 extern bool riscv_ebreaku;
 261
 262 /* Everything needs the RISC-V specific info structure, so here's a nice macro
 263  * that provides that. */
 264 static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
 265 static inline riscv_info_t *riscv_info(const struct target *target)
 266 {
 267         assert(target->arch_info);
 268         return target->arch_info;
 269 }
 270 #define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
 271
 272 extern uint8_t ir_dtmcontrol[4];
 273 extern struct scan_field select_dtmcontrol;
 274 extern uint8_t ir_dbus[4];
 275 extern struct scan_field select_dbus;
 276 extern uint8_t ir_idcode[4];
 277 extern struct scan_field select_idcode;
 278
 279 extern struct scan_field select_user4;
 280 extern struct scan_field *bscan_tunneled_select_dmi;
 281 extern uint32_t bscan_tunneled_select_dmi_num_fields;
 282 typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
 283 extern int bscan_tunnel_ir_width;
 284 extern bscan_tunnel_type_t bscan_tunnel_type;
 285
 286 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
 287 void select_dmi_via_bscan(struct target *target);
 288
 289 /*** OpenOCD Interface */
 290 int riscv_openocd_poll(struct target *target);
 291
 292 int riscv_halt(struct target *target);
 293
 294 int riscv_resume(
 295         struct target *target,
 296         int current,
 297         target_addr_t address,
 298         int handle_breakpoints,
 299         int debug_execution,
 300         bool single_hart
 301 );
 302
 303 int riscv_openocd_step(
 304         struct target *target,
 305         int current,
 306         target_addr_t address,
 307         int handle_breakpoints
 308 );
 309
 310 int riscv_openocd_assert_reset(struct target *target);
 311 int riscv_openocd_deassert_reset(struct target *target);
 312
 313 /*** RISC-V Interface ***/
 314
 315 /* Initializes the shared RISC-V structure. */
 316 void riscv_info_init(struct target *target, riscv_info_t *r);
 317
 318 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
 319  * then the only hart. */
 320 int riscv_step_rtos_hart(struct target *target);
 321
 322 bool riscv_supports_extension(struct target *target, char letter);
 323
 324 /* Returns XLEN for the given (or current) hart. */
 325 unsigned riscv_xlen(const struct target *target);
 326 int riscv_xlen_of_hart(const struct target *target);
 327
 328 /* Sets the current hart, which is the hart that will actually be used when
 329  * issuing debug commands. */
 330 int riscv_set_current_hartid(struct target *target, int hartid);
 331 int riscv_select_current_hart(struct target *target);
 332 int riscv_current_hartid(const struct target *target);
 333
 334 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
 335  * without requiring multiple targets.  */
 336
 337 /* Lists the number of harts in the system, which are assumed to be
 338  * consecutive and start with mhartid=0. */
 339 int riscv_count_harts(struct target *target);
 340
 341 /** Set register, updating the cache. */
 342 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
 343 /** Get register, from the cache if it's in there. */
 344 int riscv_get_register(struct target *target, riscv_reg_t *value,
 345                 enum gdb_regno r);
 346
 347 /* Checks the state of the current hart -- "is_halted" checks the actual
 348  * on-device register. */
 349 bool riscv_is_halted(struct target *target);
 350 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
 351
 352 /* These helper functions let the generic program interface get target-specific
 353  * information. */
 354 size_t riscv_debug_buffer_size(struct target *target);
 355
 356 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
 357 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
 358 int riscv_execute_debug_buffer(struct target *target);
 359
 360 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
 361 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
 362 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
 363 int riscv_dmi_write_u64_bits(struct target *target);
 364
 365 /* Invalidates the register cache. */
 366 void riscv_invalidate_register_cache(struct target *target);
 367
 368 int riscv_enumerate_triggers(struct target *target);
 369
 370 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 371 int riscv_remove_breakpoint(struct target *target,
 372                 struct breakpoint *breakpoint);
 373 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 374 int riscv_remove_watchpoint(struct target *target,
 375                 struct watchpoint *watchpoint);
 376 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address);
 377
 378 int riscv_init_registers(struct target *target);
 379
 380 void riscv_semihosting_init(struct target *target);
 381
 382 enum semihosting_result riscv_semihosting(struct target *target, int *retval);
 383
 384 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
 385                 riscv_bscan_tunneled_scan_context_t *ctxt);
 386
 387 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
 388 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
 389
 390 #endif