1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2018 by Liviu Ionescu *
7 * Copyright (C) 2009 by Marvell Technology Group Ltd. *
8 * Written by Nicolas Pitre <nico@marvell.com> *
10 * Copyright (C) 2010 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
13 * Copyright (C) 2016 by Square, Inc. *
14 * Steven Stallion <stallion@squareup.com> *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * Hold RISC-V semihosting support.
34 * The RISC-V code is inspired from ARM semihosting.
36 * Details can be found in chapter 8 of DUI0203I_rvct_developer_guide.pdf
44 #include <helper/log.h>
46 #include "target/target.h"
47 #include "target/semihosting_common.h"
50 static int riscv_semihosting_setup(struct target
*target
, int enable
);
51 static int riscv_semihosting_post_result(struct target
*target
);
54 * Initialize RISC-V semihosting. Use common ARM code.
56 void riscv_semihosting_init(struct target
*target
)
58 semihosting_common_init(target
, riscv_semihosting_setup
,
59 riscv_semihosting_post_result
);
63 * Check for and process a semihosting request using the ARM protocol). This
64 * is meant to be called when the target is stopped due to a debug mode entry.
66 * @param target Pointer to the target to process.
67 * @param retval Pointer to a location where the return code will be stored
68 * @return non-zero value if a request was processed or an error encountered
70 semihosting_result_t
riscv_semihosting(struct target
*target
, int *retval
)
72 struct semihosting
*semihosting
= target
->semihosting
;
74 LOG_DEBUG(" -> NONE (!semihosting)");
78 if (!semihosting
->is_active
) {
79 LOG_DEBUG(" -> NONE (!semihosting->is_active)");
84 int result
= riscv_get_register(target
, &pc
, GDB_REGNO_PC
);
85 if (result
!= ERROR_OK
)
90 /* Read three uncompressed instructions: The previous, the current one (pointed to by PC) and the next one */
91 for (int i
= 0; i
< 3; i
++) {
92 /* Instruction memories may not support arbitrary read size. Use any size that will work. */
93 *retval
= riscv_read_by_any_size(target
, (pc
- 4) + 4 * i
, 4, tmp_buf
+ 4 * i
);
94 if (*retval
!= ERROR_OK
)
99 * The instructions that trigger a semihosting call,
100 * always uncompressed, should look like:
102 * 01f01013 slli zero,zero,0x1f
104 * 40705013 srai zero,zero,0x7
106 uint32_t pre
= target_buffer_get_u32(target
, tmp_buf
);
107 uint32_t ebreak
= target_buffer_get_u32(target
, tmp_buf
+ 4);
108 uint32_t post
= target_buffer_get_u32(target
, tmp_buf
+ 8);
109 LOG_DEBUG("check %08x %08x %08x from 0x%" PRIx64
"-4", pre
, ebreak
, post
, pc
);
111 if (pre
!= 0x01f01013 || ebreak
!= 0x00100073 || post
!= 0x40705013) {
112 /* Not the magic sequence defining semihosting. */
113 LOG_DEBUG(" -> NONE (no magic)");
118 * Perform semihosting call if we are not waiting on a fileio
119 * operation to complete.
121 if (!semihosting
->hit_fileio
) {
122 /* RISC-V uses A0 and A1 to pass function arguments */
126 result
= riscv_get_register(target
, &r0
, GDB_REGNO_A0
);
127 if (result
!= ERROR_OK
) {
128 LOG_DEBUG(" -> ERROR (couldn't read a0)");
132 result
= riscv_get_register(target
, &r1
, GDB_REGNO_A1
);
133 if (result
!= ERROR_OK
) {
134 LOG_DEBUG(" -> ERROR (couldn't read a1)");
138 semihosting
->op
= r0
;
139 semihosting
->param
= r1
;
140 semihosting
->word_size_bytes
= riscv_xlen(target
) / 8;
142 /* Check for ARM operation numbers. */
143 if (semihosting
->op
>= 0 && semihosting
->op
<= 0x31) {
144 *retval
= semihosting_common(target
);
145 if (*retval
!= ERROR_OK
) {
146 LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting
->op
);
150 /* Unknown operation number, not a semihosting call. */
151 LOG_DEBUG(" -> NONE (unknown operation number)");
157 * Resume target if we are not waiting on a fileio
158 * operation to complete.
160 if (semihosting
->is_resumable
&& !semihosting
->hit_fileio
) {
161 /* Resume right after the EBREAK 4 bytes instruction. */
162 *retval
= riscv_set_register(target
, GDB_REGNO_PC
, pc
+ 4);
163 if (*retval
!= ERROR_OK
)
166 LOG_DEBUG(" -> HANDLED");
170 LOG_DEBUG(" -> WAITING");
174 /* -------------------------------------------------------------------------
175 * Local functions. */
178 * Called via semihosting->setup() later, after the target is known,
179 * usually on the first semihosting command.
181 static int riscv_semihosting_setup(struct target
*target
, int enable
)
183 LOG_DEBUG("[%s] enable=%d", target_name(target
), enable
);
185 struct semihosting
*semihosting
= target
->semihosting
;
187 semihosting
->setup_time
= clock();
192 static int riscv_semihosting_post_result(struct target
*target
)
194 struct semihosting
*semihosting
= target
->semihosting
;
196 /* If not enabled, silently ignored. */
200 LOG_DEBUG("0x%" PRIx64
, semihosting
->result
);
201 riscv_set_register(target
, GDB_REGNO_A0
, semihosting
->result
);
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