2 OpenOCD STM8 target driver
3 Copyright (C) 2017 Ake Rehnman
4 ake.rehnman(at)gmail.com
6 This program is free software: you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <helper/log.h>
26 #include "target_type.h"
28 #include "jtag/jtag.h"
29 #include "jtag/hla/hla_transport.h"
30 #include "jtag/hla/hla_interface.h"
31 #include "jtag/hla/hla_layout.h"
33 #include "breakpoints.h"
34 #include "algorithm.h"
37 static struct reg_cache
*stm8_build_reg_cache(struct target
*target
);
38 static int stm8_read_core_reg(struct target
*target
, unsigned int num
);
39 static int stm8_write_core_reg(struct target
*target
, unsigned int num
);
40 static int stm8_save_context(struct target
*target
);
41 static void stm8_enable_breakpoints(struct target
*target
);
42 static int stm8_unset_breakpoint(struct target
*target
,
43 struct breakpoint
*breakpoint
);
44 static int stm8_set_breakpoint(struct target
*target
,
45 struct breakpoint
*breakpoint
);
46 static void stm8_enable_watchpoints(struct target
*target
);
47 static int stm8_unset_watchpoint(struct target
*target
,
48 struct watchpoint
*watchpoint
);
59 { 0, "pc", 32, REG_TYPE_UINT32
, "general", "org.gnu.gdb.stm8.core", 0 },
60 { 1, "a", 8, REG_TYPE_UINT8
, "general", "org.gnu.gdb.stm8.core", 0 },
61 { 2, "x", 16, REG_TYPE_UINT16
, "general", "org.gnu.gdb.stm8.core", 0 },
62 { 3, "y", 16, REG_TYPE_UINT16
, "general", "org.gnu.gdb.stm8.core", 0 },
63 { 4, "sp", 16, REG_TYPE_UINT16
, "general", "org.gnu.gdb.stm8.core", 0 },
64 { 5, "cc", 8, REG_TYPE_UINT8
, "general", "org.gnu.gdb.stm8.core", 0 },
67 #define STM8_NUM_REGS ARRAY_SIZE(stm8_regs)
78 #define DM_REGS 0x7f00
79 #define DM_REG_A 0x7f00
80 #define DM_REG_PC 0x7f01
81 #define DM_REG_X 0x7f04
82 #define DM_REG_Y 0x7f06
83 #define DM_REG_SP 0x7f08
84 #define DM_REG_CC 0x7f0a
86 #define DM_BKR1E 0x7f90
87 #define DM_BKR2E 0x7f93
90 #define DM_CSR1 0x7f98
91 #define DM_CSR2 0x7f99
105 #define FLASH_CR1_STM8S 0x505A
106 #define FLASH_CR2_STM8S 0x505B
107 #define FLASH_NCR2_STM8S 0x505C
108 #define FLASH_IAPSR_STM8S 0x505F
109 #define FLASH_PUKR_STM8S 0x5062
110 #define FLASH_DUKR_STM8S 0x5064
112 #define FLASH_CR1_STM8L 0x5050
113 #define FLASH_CR2_STM8L 0x5051
114 #define FLASH_NCR2_STM8L 0
115 #define FLASH_PUKR_STM8L 0x5052
116 #define FLASH_DUKR_STM8L 0x5053
117 #define FLASH_IAPSR_STM8L 0x5054
124 #define WR_PG_DIS 0x01
134 #define SAFE_MASK 0x80
135 #define NO_ACCESS 0x40
139 #define SWIM_RST 0x04
143 #define SWIM_CSR 0x7f80
145 #define STM8_BREAK 0x8B
154 struct stm8_algorithm
{
158 struct stm8_core_reg
{
160 struct target
*target
;
161 struct stm8_common
*stm8_common
;
165 /* break on execute */
171 /* break on read, write and execute */
175 struct stm8_comparator
{
178 uint32_t reg_address
;
179 enum hw_break_type type
;
182 static inline struct hl_interface_s
*target_to_adapter(struct target
*target
)
184 return target
->tap
->priv
;
187 static int stm8_adapter_read_memory(struct target
*target
,
188 uint32_t addr
, int size
, int count
, void *buf
)
191 struct hl_interface_s
*adapter
= target_to_adapter(target
);
193 ret
= adapter
->layout
->api
->read_mem(adapter
->handle
,
194 addr
, size
, count
, buf
);
200 static int stm8_adapter_write_memory(struct target
*target
,
201 uint32_t addr
, int size
, int count
, const void *buf
)
204 struct hl_interface_s
*adapter
= target_to_adapter(target
);
206 ret
= adapter
->layout
->api
->write_mem(adapter
->handle
,
207 addr
, size
, count
, buf
);
213 static int stm8_write_u8(struct target
*target
,
214 uint32_t addr
, uint8_t val
)
218 struct hl_interface_s
*adapter
= target_to_adapter(target
);
221 ret
= adapter
->layout
->api
->write_mem(adapter
->handle
, addr
, 1, 1, buf
);
227 static int stm8_read_u8(struct target
*target
,
228 uint32_t addr
, uint8_t *val
)
231 struct hl_interface_s
*adapter
= target_to_adapter(target
);
233 ret
= adapter
->layout
->api
->read_mem(adapter
->handle
, addr
, 1, 1, val
);
239 static int stm8_set_speed(struct target
*target
, int speed
)
241 struct hl_interface_s
*adapter
= target_to_adapter(target
);
242 adapter
->layout
->api
->speed(adapter
->handle
, speed
, 0);
247 <enable == 0> Disables interrupts.
248 If interrupts are enabled they are masked and the cc register
251 <enable == 1> Enables interrupts.
252 Enable interrupts is actually restoring I1 I0 state from previous
253 call with enable == 0. Note that if stepping and breaking on a sim
254 instruction will NOT work since the interrupt flags are restored on
255 debug_entry. We don't have any way for the debugger to exclusively
256 disable the interrupts
258 static int stm8_enable_interrupts(struct target
*target
, int enable
)
260 struct stm8_common
*stm8
= target_to_stm8(target
);
265 return ERROR_OK
; /* cc was not stashed */
266 /* fetch current cc */
267 stm8_read_u8(target
, DM_REG_CC
, &cc
);
269 cc
&= ~(CC_I0
+ CC_I1
);
270 /* restore I1 & I0 from stash*/
271 cc
|= (stm8
->cc
& (CC_I0
+CC_I1
));
272 /* update current cc */
273 stm8_write_u8(target
, DM_REG_CC
, cc
);
274 stm8
->cc_valid
= false;
276 stm8_read_u8(target
, DM_REG_CC
, &cc
);
277 if ((cc
& CC_I0
) && (cc
& CC_I1
))
278 return ERROR_OK
; /* interrupts already masked */
281 stm8
->cc_valid
= true;
282 /* mask interrupts (disable) */
283 cc
|= (CC_I0
+ CC_I1
);
284 stm8_write_u8(target
, DM_REG_CC
, cc
);
290 static int stm8_set_hwbreak(struct target
*target
,
291 struct stm8_comparator comparator_list
[])
296 /* Refer to Table 4 in UM0470 */
304 if (!comparator_list
[0].used
) {
305 comparator_list
[0].type
= HWBRK_EXEC
;
306 comparator_list
[0].bp_value
= -1;
309 if (!comparator_list
[1].used
) {
310 comparator_list
[1].type
= HWBRK_EXEC
;
311 comparator_list
[1].bp_value
= -1;
314 if ((comparator_list
[0].type
== HWBRK_EXEC
)
315 && (comparator_list
[1].type
== HWBRK_EXEC
)) {
316 comparator_list
[0].reg_address
= 0;
317 comparator_list
[1].reg_address
= 1;
320 if ((comparator_list
[0].type
== HWBRK_EXEC
)
321 && (comparator_list
[1].type
!= HWBRK_EXEC
)) {
322 comparator_list
[0].reg_address
= 0;
323 comparator_list
[1].reg_address
= 1;
324 switch (comparator_list
[1].type
) {
338 if ((comparator_list
[1].type
== HWBRK_EXEC
)
339 && (comparator_list
[0].type
!= HWBRK_EXEC
)) {
340 comparator_list
[0].reg_address
= 1;
341 comparator_list
[1].reg_address
= 0;
342 switch (comparator_list
[0].type
) {
356 if ((comparator_list
[0].type
!= HWBRK_EXEC
)
357 && (comparator_list
[1].type
!= HWBRK_EXEC
)) {
358 if ((comparator_list
[0].type
!= comparator_list
[1].type
)) {
359 LOG_ERROR("data hw breakpoints must be of same type");
360 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
364 for (i
= 0; i
< 2; i
++) {
365 data
= comparator_list
[i
].bp_value
;
366 addr
= comparator_list
[i
].reg_address
;
373 ret
= stm8_adapter_write_memory(target
, DM_BKR1E
, 1, 3, buf
);
374 LOG_DEBUG("DM_BKR1E=%" PRIx32
, data
);
375 } else if (addr
== 1) {
376 ret
= stm8_adapter_write_memory(target
, DM_BKR2E
, 1, 3, buf
);
377 LOG_DEBUG("DM_BKR2E=%" PRIx32
, data
);
379 LOG_DEBUG("addr=%" PRIu32
, addr
);
386 ret
= stm8_write_u8(target
, DM_CR1
,
387 (bc
<< 3) + (bir
<< 2) + (biw
<< 1));
388 LOG_DEBUG("DM_CR1=%" PRIx8
, buf
[0]);
396 /* read DM control and status regs */
397 static int stm8_read_dm_csrx(struct target
*target
, uint8_t *csr1
,
403 ret
= stm8_adapter_read_memory(target
, DM_CSR1
, 1, sizeof(buf
), buf
);
413 /* set or clear the single step flag in DM */
414 static int stm8_config_step(struct target
*target
, int enable
)
419 ret
= stm8_read_dm_csrx(target
, &csr1
, &csr2
);
427 ret
= stm8_write_u8(target
, DM_CSR1
, csr1
);
433 /* set the stall flag in DM */
434 static int stm8_debug_stall(struct target
*target
)
439 ret
= stm8_read_dm_csrx(target
, &csr1
, &csr2
);
443 ret
= stm8_write_u8(target
, DM_CSR2
, csr2
);
449 static int stm8_configure_break_unit(struct target
*target
)
451 /* get pointers to arch-specific information */
452 struct stm8_common
*stm8
= target_to_stm8(target
);
454 if (stm8
->bp_scanned
)
457 stm8
->num_hw_bpoints
= 2;
458 stm8
->num_hw_bpoints_avail
= stm8
->num_hw_bpoints
;
460 stm8
->hw_break_list
= calloc(stm8
->num_hw_bpoints
,
461 sizeof(struct stm8_comparator
));
463 stm8
->hw_break_list
[0].reg_address
= 0;
464 stm8
->hw_break_list
[1].reg_address
= 1;
466 LOG_DEBUG("hw breakpoints: numinst %i numdata %i", stm8
->num_hw_bpoints
,
467 stm8
->num_hw_bpoints
);
469 stm8
->bp_scanned
= true;
474 static int stm8_examine_debug_reason(struct target
*target
)
479 retval
= stm8_read_dm_csrx(target
, &csr1
, &csr2
);
480 if (retval
== ERROR_OK
)
481 LOG_DEBUG("csr1 = 0x%02X csr2 = 0x%02X", csr1
, csr2
);
483 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
484 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
486 if (retval
!= ERROR_OK
)
490 /* halted on reset */
491 target
->debug_reason
= DBG_REASON_UNDEFINED
;
493 if (csr1
& (BK1F
+BK2F
))
494 /* we have halted on a breakpoint (or wp)*/
495 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
498 /* we have halted on a breakpoint */
499 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
506 static int stm8_debug_entry(struct target
*target
)
508 struct stm8_common
*stm8
= target_to_stm8(target
);
510 /* restore interrupts */
511 stm8_enable_interrupts(target
, 1);
513 stm8_save_context(target
);
515 /* make sure stepping disabled STE bit in CSR1 cleared */
516 stm8_config_step(target
, 0);
518 /* attempt to find halt reason */
519 stm8_examine_debug_reason(target
);
521 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
522 buf_get_u32(stm8
->core_cache
->reg_list
[STM8_PC
].value
, 0, 32),
523 target_state_name(target
));
528 /* clear stall flag in DM and flush instruction pipe */
529 static int stm8_exit_debug(struct target
*target
)
534 ret
= stm8_read_dm_csrx(target
, &csr1
, &csr2
);
538 ret
= stm8_write_u8(target
, DM_CSR2
, csr2
);
544 ret
= stm8_write_u8(target
, DM_CSR2
, csr2
);
550 static int stm8_read_regs(struct target
*target
, uint32_t regs
[])
555 ret
= stm8_adapter_read_memory(target
, DM_REGS
, 1, sizeof(buf
), buf
);
559 regs
[0] = be_to_h_u24(buf
+DM_REG_PC
-DM_REGS
);
560 regs
[1] = buf
[DM_REG_A
-DM_REGS
];
561 regs
[2] = be_to_h_u16(buf
+DM_REG_X
-DM_REGS
);
562 regs
[3] = be_to_h_u16(buf
+DM_REG_Y
-DM_REGS
);
563 regs
[4] = be_to_h_u16(buf
+DM_REG_SP
-DM_REGS
);
564 regs
[5] = buf
[DM_REG_CC
-DM_REGS
];
569 static int stm8_write_regs(struct target
*target
, uint32_t regs
[])
574 h_u24_to_be(buf
+DM_REG_PC
-DM_REGS
, regs
[0]);
575 buf
[DM_REG_A
-DM_REGS
] = regs
[1];
576 h_u16_to_be(buf
+DM_REG_X
-DM_REGS
, regs
[2]);
577 h_u16_to_be(buf
+DM_REG_Y
-DM_REGS
, regs
[3]);
578 h_u16_to_be(buf
+DM_REG_SP
-DM_REGS
, regs
[4]);
579 buf
[DM_REG_CC
-DM_REGS
] = regs
[5];
581 ret
= stm8_adapter_write_memory(target
, DM_REGS
, 1, sizeof(buf
), buf
);
588 static int stm8_get_core_reg(struct reg
*reg
)
591 struct stm8_core_reg
*stm8_reg
= reg
->arch_info
;
592 struct target
*target
= stm8_reg
->target
;
593 struct stm8_common
*stm8_target
= target_to_stm8(target
);
595 if (target
->state
!= TARGET_HALTED
)
596 return ERROR_TARGET_NOT_HALTED
;
598 retval
= stm8_target
->read_core_reg(target
, stm8_reg
->num
);
603 static int stm8_set_core_reg(struct reg
*reg
, uint8_t *buf
)
605 struct stm8_core_reg
*stm8_reg
= reg
->arch_info
;
606 struct target
*target
= stm8_reg
->target
;
607 uint32_t value
= buf_get_u32(buf
, 0, reg
->size
);
609 if (target
->state
!= TARGET_HALTED
)
610 return ERROR_TARGET_NOT_HALTED
;
612 buf_set_u32(reg
->value
, 0, 32, value
);
619 static int stm8_save_context(struct target
*target
)
623 /* get pointers to arch-specific information */
624 struct stm8_common
*stm8
= target_to_stm8(target
);
626 /* read core registers */
627 stm8_read_regs(target
, stm8
->core_regs
);
629 for (i
= 0; i
< STM8_NUM_REGS
; i
++) {
630 if (!stm8
->core_cache
->reg_list
[i
].valid
)
631 stm8
->read_core_reg(target
, i
);
637 static int stm8_restore_context(struct target
*target
)
641 /* get pointers to arch-specific information */
642 struct stm8_common
*stm8
= target_to_stm8(target
);
644 for (i
= 0; i
< STM8_NUM_REGS
; i
++) {
645 if (stm8
->core_cache
->reg_list
[i
].dirty
)
646 stm8
->write_core_reg(target
, i
);
649 /* write core regs */
650 stm8_write_regs(target
, stm8
->core_regs
);
655 static int stm8_unlock_flash(struct target
*target
)
659 struct stm8_common
*stm8
= target_to_stm8(target
);
661 /* check if flash is unlocked */
662 stm8_read_u8(target
, stm8
->flash_iapsr
, data
);
663 if (~data
[0] & PUL
) {
665 stm8_write_u8(target
, stm8
->flash_pukr
, 0x56);
666 stm8_write_u8(target
, stm8
->flash_pukr
, 0xae);
669 stm8_read_u8(target
, stm8
->flash_iapsr
, data
);
675 static int stm8_unlock_eeprom(struct target
*target
)
679 struct stm8_common
*stm8
= target_to_stm8(target
);
681 /* check if eeprom is unlocked */
682 stm8_read_u8(target
, stm8
->flash_iapsr
, data
);
683 if (~data
[0] & DUL
) {
685 stm8_write_u8(target
, stm8
->flash_dukr
, 0xae);
686 stm8_write_u8(target
, stm8
->flash_dukr
, 0x56);
689 stm8_read_u8(target
, stm8
->flash_iapsr
, data
);
695 static int stm8_write_flash(struct target
*target
, enum mem_type type
,
697 uint32_t size
, uint32_t count
, uint32_t blocksize_param
,
698 const uint8_t *buffer
)
700 struct stm8_common
*stm8
= target_to_stm8(target
);
705 uint32_t blocksize
= 0;
711 stm8_unlock_flash(target
);
714 stm8_unlock_eeprom(target
);
717 stm8_unlock_eeprom(target
);
721 LOG_ERROR("BUG: wrong mem_type %d", type
);
726 /* we don't support short writes */
731 bytecnt
= count
* size
;
734 if ((bytecnt
>= blocksize_param
) && ((address
& (blocksize_param
-1)) == 0)) {
736 stm8_write_u8(target
, stm8
->flash_cr2
, PRG
+ opt
);
737 if (stm8
->flash_ncr2
)
738 stm8_write_u8(target
, stm8
->flash_ncr2
, ~(PRG
+ opt
));
739 blocksize
= blocksize_param
;
741 if ((bytecnt
>= 4) && ((address
& 0x3) == 0)) {
743 stm8_write_u8(target
, stm8
->flash_cr2
, WPRG
+ opt
);
744 if (stm8
->flash_ncr2
)
745 stm8_write_u8(target
, stm8
->flash_ncr2
, ~(WPRG
+ opt
));
748 if (blocksize
!= 1) {
750 stm8_write_u8(target
, stm8
->flash_cr2
, opt
);
751 if (stm8
->flash_ncr2
)
752 stm8_write_u8(target
, stm8
->flash_ncr2
, ~opt
);
756 res
= stm8_adapter_write_memory(target
, address
, 1, blocksize
, buffer
);
759 address
+= blocksize
;
761 bytecnt
-= blocksize
;
763 /* lets hang here until end of program (EOP) */
764 for (i
= 0; i
< 16; i
++) {
765 stm8_read_u8(target
, stm8
->flash_iapsr
, &iapsr
);
775 /* disable write access */
776 res
= stm8_write_u8(target
, stm8
->flash_iapsr
, 0x0);
784 static int stm8_write_memory(struct target
*target
, target_addr_t address
,
785 uint32_t size
, uint32_t count
,
786 const uint8_t *buffer
)
788 struct stm8_common
*stm8
= target_to_stm8(target
);
790 LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR
791 ", size: 0x%8.8" PRIx32
792 ", count: 0x%8.8" PRIx32
,
793 address
, size
, count
);
795 if (target
->state
!= TARGET_HALTED
)
796 LOG_WARNING("target not halted");
800 if ((address
>= stm8
->flashstart
) && (address
<= stm8
->flashend
))
801 retval
= stm8_write_flash(target
, FLASH
, address
, size
, count
,
802 stm8
->blocksize
, buffer
);
803 else if ((address
>= stm8
->eepromstart
) && (address
<= stm8
->eepromend
))
804 retval
= stm8_write_flash(target
, EEPROM
, address
, size
, count
,
805 stm8
->blocksize
, buffer
);
806 else if ((address
>= stm8
->optionstart
) && (address
<= stm8
->optionend
))
807 retval
= stm8_write_flash(target
, OPTION
, address
, size
, count
, 0, buffer
);
809 retval
= stm8_adapter_write_memory(target
, address
, size
, count
,
812 if (retval
!= ERROR_OK
)
813 return ERROR_TARGET_FAILURE
;
818 static int stm8_read_memory(struct target
*target
, target_addr_t address
,
819 uint32_t size
, uint32_t count
, uint8_t *buffer
)
821 LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR
822 ", size: 0x%8.8" PRIx32
823 ", count: 0x%8.8" PRIx32
,
824 address
, size
, count
);
826 if (target
->state
!= TARGET_HALTED
)
827 LOG_WARNING("target not halted");
830 retval
= stm8_adapter_read_memory(target
, address
, size
, count
, buffer
);
832 if (retval
!= ERROR_OK
)
833 return ERROR_TARGET_FAILURE
;
838 static int stm8_init(struct command_context
*cmd_ctx
, struct target
*target
)
840 stm8_build_reg_cache(target
);
845 static int stm8_poll(struct target
*target
)
847 int retval
= ERROR_OK
;
851 LOG_DEBUG("target->state=%d", target
->state
);
854 /* read dm_csrx control regs */
855 retval
= stm8_read_dm_csrx(target
, &csr1
, &csr2
);
856 if (retval
!= ERROR_OK
) {
857 LOG_DEBUG("stm8_read_dm_csrx failed retval=%d", retval
);
859 We return ERROR_OK here even if we didn't get an answer.
860 openocd will call target_wait_state until we get target state TARGET_HALTED
865 /* check for processor halted */
867 if (target
->state
!= TARGET_HALTED
) {
868 if (target
->state
== TARGET_UNKNOWN
)
869 LOG_DEBUG("DM_CSR2_STALL already set during server startup.");
871 retval
= stm8_debug_entry(target
);
872 if (retval
!= ERROR_OK
) {
873 LOG_DEBUG("stm8_debug_entry failed retval=%d", retval
);
874 return ERROR_TARGET_FAILURE
;
877 if (target
->state
== TARGET_DEBUG_RUNNING
) {
878 target
->state
= TARGET_HALTED
;
879 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
881 target
->state
= TARGET_HALTED
;
882 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
886 target
->state
= TARGET_RUNNING
;
888 LOG_DEBUG("csr1 = 0x%02X csr2 = 0x%02X", csr1
, csr2
);
893 static int stm8_halt(struct target
*target
)
895 LOG_DEBUG("target->state: %s", target_state_name(target
));
897 if (target
->state
== TARGET_HALTED
) {
898 LOG_DEBUG("target was already halted");
902 if (target
->state
== TARGET_UNKNOWN
)
903 LOG_WARNING("target was in unknown state when halt was requested");
905 if (target
->state
== TARGET_RESET
) {
906 /* we came here in a reset_halt or reset_init sequence
907 * debug entry was already prepared in stm8_assert_reset()
909 target
->debug_reason
= DBG_REASON_DBGRQ
;
915 /* break processor */
916 stm8_debug_stall(target
);
918 target
->debug_reason
= DBG_REASON_DBGRQ
;
923 static int stm8_reset_assert(struct target
*target
)
926 struct hl_interface_s
*adapter
= target_to_adapter(target
);
927 struct stm8_common
*stm8
= target_to_stm8(target
);
928 bool use_srst_fallback
= true;
930 enum reset_types jtag_reset_config
= jtag_get_reset_config();
932 if (jtag_reset_config
& RESET_HAS_SRST
) {
933 jtag_add_reset(0, 1);
934 res
= adapter
->layout
->api
->assert_srst(adapter
->handle
, 0);
937 /* hardware srst supported */
938 use_srst_fallback
= false;
939 else if (res
!= ERROR_COMMAND_NOTFOUND
)
940 /* some other failure */
944 if (use_srst_fallback
) {
945 LOG_DEBUG("Hardware srst not supported, falling back to swim reset");
946 res
= adapter
->layout
->api
->reset(adapter
->handle
);
951 /* registers are now invalid */
952 register_cache_invalidate(stm8
->core_cache
);
954 target
->state
= TARGET_RESET
;
955 target
->debug_reason
= DBG_REASON_NOTHALTED
;
957 if (target
->reset_halt
) {
958 res
= target_halt(target
);
966 static int stm8_reset_deassert(struct target
*target
)
969 struct hl_interface_s
*adapter
= target_to_adapter(target
);
971 enum reset_types jtag_reset_config
= jtag_get_reset_config();
973 if (jtag_reset_config
& RESET_HAS_SRST
) {
974 res
= adapter
->layout
->api
->assert_srst(adapter
->handle
, 1);
975 if ((res
!= ERROR_OK
) && (res
!= ERROR_COMMAND_NOTFOUND
))
979 /* virtual deassert reset, we need it for the internal
982 jtag_add_reset(0, 0);
984 /* The cpu should now be stalled. If halt was requested
985 let poll detect the stall */
986 if (target
->reset_halt
)
989 /* Instead of going thrugh saving context, polling and
990 then resuming target again just clear stall and proceed. */
991 target
->state
= TARGET_RUNNING
;
992 return stm8_exit_debug(target
);
995 /* stm8_single_step_core() is only used for stepping over breakpoints
996 from stm8_resume() */
997 static int stm8_single_step_core(struct target
*target
)
999 struct stm8_common
*stm8
= target_to_stm8(target
);
1001 /* configure single step mode */
1002 stm8_config_step(target
, 1);
1004 /* disable interrupts while stepping */
1005 if (!stm8
->enable_step_irq
)
1006 stm8_enable_interrupts(target
, 0);
1008 /* exit debug mode */
1009 stm8_exit_debug(target
);
1011 stm8_debug_entry(target
);
1016 static int stm8_resume(struct target
*target
, int current
,
1017 target_addr_t address
, int handle_breakpoints
,
1018 int debug_execution
)
1020 struct stm8_common
*stm8
= target_to_stm8(target
);
1021 struct breakpoint
*breakpoint
= NULL
;
1024 LOG_DEBUG("%d " TARGET_ADDR_FMT
" %d %d", current
, address
,
1025 handle_breakpoints
, debug_execution
);
1027 if (target
->state
!= TARGET_HALTED
) {
1028 LOG_WARNING("target not halted");
1029 return ERROR_TARGET_NOT_HALTED
;
1032 if (!debug_execution
) {
1033 target_free_all_working_areas(target
);
1034 stm8_enable_breakpoints(target
);
1035 stm8_enable_watchpoints(target
);
1036 struct stm8_comparator
*comparator_list
= stm8
->hw_break_list
;
1037 stm8_set_hwbreak(target
, comparator_list
);
1040 /* current = 1: continue on current pc,
1041 otherwise continue at <address> */
1043 buf_set_u32(stm8
->core_cache
->reg_list
[STM8_PC
].value
,
1045 stm8
->core_cache
->reg_list
[STM8_PC
].dirty
= true;
1046 stm8
->core_cache
->reg_list
[STM8_PC
].valid
= true;
1050 resume_pc
= address
;
1052 resume_pc
= buf_get_u32(
1053 stm8
->core_cache
->reg_list
[STM8_PC
].value
,
1056 stm8_restore_context(target
);
1058 /* the front-end may request us not to handle breakpoints */
1059 if (handle_breakpoints
) {
1060 /* Single step past breakpoint at current address */
1061 breakpoint
= breakpoint_find(target
, resume_pc
);
1063 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
,
1064 breakpoint
->address
);
1065 stm8_unset_breakpoint(target
, breakpoint
);
1066 stm8_single_step_core(target
);
1067 stm8_set_breakpoint(target
, breakpoint
);
1071 /* disable interrupts if we are debugging */
1072 if (debug_execution
)
1073 stm8_enable_interrupts(target
, 0);
1075 /* exit debug mode */
1076 stm8_exit_debug(target
);
1077 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1079 /* registers are now invalid */
1080 register_cache_invalidate(stm8
->core_cache
);
1082 if (!debug_execution
) {
1083 target
->state
= TARGET_RUNNING
;
1084 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1085 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
1087 target
->state
= TARGET_DEBUG_RUNNING
;
1088 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1089 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
1095 static int stm8_init_flash_regs(bool enable_stm8l
, struct stm8_common
*stm8
)
1097 stm8
->enable_stm8l
= enable_stm8l
;
1099 if (stm8
->enable_stm8l
) {
1100 stm8
->flash_cr2
= FLASH_CR2_STM8L
;
1101 stm8
->flash_ncr2
= FLASH_NCR2_STM8L
;
1102 stm8
->flash_iapsr
= FLASH_IAPSR_STM8L
;
1103 stm8
->flash_dukr
= FLASH_DUKR_STM8L
;
1104 stm8
->flash_pukr
= FLASH_PUKR_STM8L
;
1106 stm8
->flash_cr2
= FLASH_CR2_STM8S
;
1107 stm8
->flash_ncr2
= FLASH_NCR2_STM8S
;
1108 stm8
->flash_iapsr
= FLASH_IAPSR_STM8S
;
1109 stm8
->flash_dukr
= FLASH_DUKR_STM8S
;
1110 stm8
->flash_pukr
= FLASH_PUKR_STM8S
;
1115 static int stm8_init_arch_info(struct target
*target
,
1116 struct stm8_common
*stm8
, struct jtag_tap
*tap
)
1118 target
->endianness
= TARGET_BIG_ENDIAN
;
1119 target
->arch_info
= stm8
;
1120 stm8
->common_magic
= STM8_COMMON_MAGIC
;
1121 stm8
->fast_data_area
= NULL
;
1122 stm8
->blocksize
= 0x80;
1123 stm8
->flashstart
= 0x8000;
1124 stm8
->flashend
= 0xffff;
1125 stm8
->eepromstart
= 0x4000;
1126 stm8
->eepromend
= 0x43ff;
1127 stm8
->optionstart
= 0x4800;
1128 stm8
->optionend
= 0x487F;
1130 /* has breakpoint/watchpoint unit been scanned */
1131 stm8
->bp_scanned
= false;
1132 stm8
->hw_break_list
= NULL
;
1134 stm8
->read_core_reg
= stm8_read_core_reg
;
1135 stm8
->write_core_reg
= stm8_write_core_reg
;
1137 stm8_init_flash_regs(0, stm8
);
1142 static int stm8_target_create(struct target
*target
,
1146 struct stm8_common
*stm8
= calloc(1, sizeof(struct stm8_common
));
1148 stm8_init_arch_info(target
, stm8
, target
->tap
);
1149 stm8_configure_break_unit(target
);
1154 static int stm8_read_core_reg(struct target
*target
, unsigned int num
)
1158 /* get pointers to arch-specific information */
1159 struct stm8_common
*stm8
= target_to_stm8(target
);
1161 if (num
>= STM8_NUM_REGS
)
1162 return ERROR_COMMAND_SYNTAX_ERROR
;
1164 reg_value
= stm8
->core_regs
[num
];
1165 LOG_DEBUG("read core reg %i value 0x%" PRIx32
"", num
, reg_value
);
1166 buf_set_u32(stm8
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
1167 stm8
->core_cache
->reg_list
[num
].valid
= true;
1168 stm8
->core_cache
->reg_list
[num
].dirty
= false;
1173 static int stm8_write_core_reg(struct target
*target
, unsigned int num
)
1177 /* get pointers to arch-specific information */
1178 struct stm8_common
*stm8
= target_to_stm8(target
);
1180 if (num
>= STM8_NUM_REGS
)
1181 return ERROR_COMMAND_SYNTAX_ERROR
;
1183 reg_value
= buf_get_u32(stm8
->core_cache
->reg_list
[num
].value
, 0, 32);
1184 stm8
->core_regs
[num
] = reg_value
;
1185 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
1186 stm8
->core_cache
->reg_list
[num
].valid
= true;
1187 stm8
->core_cache
->reg_list
[num
].dirty
= false;
1192 static const char *stm8_get_gdb_arch(struct target
*target
)
1197 static int stm8_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
1198 int *reg_list_size
, enum target_register_class reg_class
)
1200 /* get pointers to arch-specific information */
1201 struct stm8_common
*stm8
= target_to_stm8(target
);
1204 *reg_list_size
= STM8_NUM_REGS
;
1205 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
1207 for (i
= 0; i
< STM8_NUM_REGS
; i
++)
1208 (*reg_list
)[i
] = &stm8
->core_cache
->reg_list
[i
];
1213 static const struct reg_arch_type stm8_reg_type
= {
1214 .get
= stm8_get_core_reg
,
1215 .set
= stm8_set_core_reg
,
1218 static struct reg_cache
*stm8_build_reg_cache(struct target
*target
)
1220 /* get pointers to arch-specific information */
1221 struct stm8_common
*stm8
= target_to_stm8(target
);
1223 int num_regs
= STM8_NUM_REGS
;
1224 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1225 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
1226 struct reg
*reg_list
= calloc(num_regs
, sizeof(struct reg
));
1227 struct stm8_core_reg
*arch_info
= malloc(
1228 sizeof(struct stm8_core_reg
) * num_regs
);
1229 struct reg_feature
*feature
;
1232 /* Build the process context cache */
1233 cache
->name
= "stm8 registers";
1235 cache
->reg_list
= reg_list
;
1236 cache
->num_regs
= num_regs
;
1238 stm8
->core_cache
= cache
;
1240 for (i
= 0; i
< num_regs
; i
++) {
1241 arch_info
[i
].num
= stm8_regs
[i
].id
;
1242 arch_info
[i
].target
= target
;
1243 arch_info
[i
].stm8_common
= stm8
;
1245 reg_list
[i
].name
= stm8_regs
[i
].name
;
1246 reg_list
[i
].size
= stm8_regs
[i
].bits
;
1248 reg_list
[i
].value
= calloc(1, 4);
1249 reg_list
[i
].valid
= false;
1250 reg_list
[i
].type
= &stm8_reg_type
;
1251 reg_list
[i
].arch_info
= &arch_info
[i
];
1253 reg_list
[i
].reg_data_type
= calloc(1, sizeof(struct reg_data_type
));
1254 if (reg_list
[i
].reg_data_type
)
1255 reg_list
[i
].reg_data_type
->type
= stm8_regs
[i
].type
;
1257 LOG_ERROR("unable to allocate reg type list");
1261 reg_list
[i
].dirty
= false;
1262 reg_list
[i
].group
= stm8_regs
[i
].group
;
1263 reg_list
[i
].number
= stm8_regs
[i
].id
;
1264 reg_list
[i
].exist
= true;
1265 reg_list
[i
].caller_save
= true; /* gdb defaults to true */
1267 feature
= calloc(1, sizeof(struct reg_feature
));
1269 feature
->name
= stm8_regs
[i
].feature
;
1270 reg_list
[i
].feature
= feature
;
1272 LOG_ERROR("unable to allocate feature list");
1278 static void stm8_free_reg_cache(struct target
*target
)
1280 struct stm8_common
*stm8
= target_to_stm8(target
);
1281 struct reg_cache
*cache
;
1285 cache
= stm8
->core_cache
;
1290 for (i
= 0; i
< cache
->num_regs
; i
++) {
1291 reg
= &cache
->reg_list
[i
];
1294 free(reg
->reg_data_type
);
1298 free(cache
->reg_list
[0].arch_info
);
1299 free(cache
->reg_list
);
1302 stm8
->core_cache
= NULL
;
1305 static void stm8_deinit(struct target
*target
)
1307 struct stm8_common
*stm8
= target_to_stm8(target
);
1309 free(stm8
->hw_break_list
);
1311 stm8_free_reg_cache(target
);
1316 static int stm8_arch_state(struct target
*target
)
1318 struct stm8_common
*stm8
= target_to_stm8(target
);
1320 LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32
"",
1321 debug_reason_name(target
),
1322 buf_get_u32(stm8
->core_cache
->reg_list
[STM8_PC
].value
, 0, 32));
1327 static int stm8_step(struct target
*target
, int current
,
1328 target_addr_t address
, int handle_breakpoints
)
1330 LOG_DEBUG("%" PRIx32
" " TARGET_ADDR_FMT
" %" PRIx32
,
1331 current
, address
, handle_breakpoints
);
1333 /* get pointers to arch-specific information */
1334 struct stm8_common
*stm8
= target_to_stm8(target
);
1335 struct breakpoint
*breakpoint
= NULL
;
1337 if (target
->state
!= TARGET_HALTED
) {
1338 LOG_WARNING("target not halted");
1339 return ERROR_TARGET_NOT_HALTED
;
1342 /* current = 1: continue on current pc, otherwise continue at <address> */
1344 buf_set_u32(stm8
->core_cache
->reg_list
[STM8_PC
].value
, 0, 32, address
);
1345 stm8
->core_cache
->reg_list
[STM8_PC
].dirty
= true;
1346 stm8
->core_cache
->reg_list
[STM8_PC
].valid
= true;
1349 /* the front-end may request us not to handle breakpoints */
1350 if (handle_breakpoints
) {
1351 breakpoint
= breakpoint_find(target
,
1352 buf_get_u32(stm8
->core_cache
->reg_list
[STM8_PC
].value
, 0, 32));
1354 stm8_unset_breakpoint(target
, breakpoint
);
1357 /* restore context */
1358 stm8_restore_context(target
);
1360 /* configure single step mode */
1361 stm8_config_step(target
, 1);
1363 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1365 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1367 /* disable interrupts while stepping */
1368 if (!stm8
->enable_step_irq
)
1369 stm8_enable_interrupts(target
, 0);
1371 /* exit debug mode */
1372 stm8_exit_debug(target
);
1374 /* registers are now invalid */
1375 register_cache_invalidate(stm8
->core_cache
);
1377 LOG_DEBUG("target stepped ");
1378 stm8_debug_entry(target
);
1381 stm8_set_breakpoint(target
, breakpoint
);
1383 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1388 static void stm8_enable_breakpoints(struct target
*target
)
1390 struct breakpoint
*breakpoint
= target
->breakpoints
;
1392 /* set any pending breakpoints */
1393 while (breakpoint
) {
1394 if (breakpoint
->set
== 0)
1395 stm8_set_breakpoint(target
, breakpoint
);
1396 breakpoint
= breakpoint
->next
;
1400 static int stm8_set_breakpoint(struct target
*target
,
1401 struct breakpoint
*breakpoint
)
1403 struct stm8_common
*stm8
= target_to_stm8(target
);
1404 struct stm8_comparator
*comparator_list
= stm8
->hw_break_list
;
1407 if (breakpoint
->set
) {
1408 LOG_WARNING("breakpoint already set");
1412 if (breakpoint
->type
== BKPT_HARD
) {
1415 while (comparator_list
[bp_num
].used
&& (bp_num
< stm8
->num_hw_bpoints
))
1417 if (bp_num
>= stm8
->num_hw_bpoints
) {
1418 LOG_ERROR("Can not find free breakpoint register (bpid: %" PRIu32
")",
1419 breakpoint
->unique_id
);
1420 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1422 breakpoint
->set
= bp_num
+ 1;
1423 comparator_list
[bp_num
].used
= true;
1424 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
1425 comparator_list
[bp_num
].type
= HWBRK_EXEC
;
1427 retval
= stm8_set_hwbreak(target
, comparator_list
);
1428 if (retval
!= ERROR_OK
)
1431 LOG_DEBUG("bpid: %" PRIu32
", bp_num %i bp_value 0x%" PRIx32
"",
1432 breakpoint
->unique_id
,
1433 bp_num
, comparator_list
[bp_num
].bp_value
);
1434 } else if (breakpoint
->type
== BKPT_SOFT
) {
1435 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1436 if (breakpoint
->length
== 1) {
1437 uint8_t verify
= 0x55;
1439 retval
= target_read_u8(target
, breakpoint
->address
,
1440 breakpoint
->orig_instr
);
1441 if (retval
!= ERROR_OK
)
1443 retval
= target_write_u8(target
, breakpoint
->address
, STM8_BREAK
);
1444 if (retval
!= ERROR_OK
)
1447 retval
= target_read_u8(target
, breakpoint
->address
, &verify
);
1448 if (retval
!= ERROR_OK
)
1450 if (verify
!= STM8_BREAK
) {
1451 LOG_ERROR("Unable to set breakpoint at address " TARGET_ADDR_FMT
1452 " - check that memory is read/writable",
1453 breakpoint
->address
);
1454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1457 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1459 breakpoint
->set
= 1; /* Any nice value but 0 */
1465 static int stm8_add_breakpoint(struct target
*target
,
1466 struct breakpoint
*breakpoint
)
1468 struct stm8_common
*stm8
= target_to_stm8(target
);
1471 if (breakpoint
->type
== BKPT_HARD
) {
1472 if (stm8
->num_hw_bpoints_avail
< 1) {
1473 LOG_INFO("no hardware breakpoint available");
1474 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1477 ret
= stm8_set_breakpoint(target
, breakpoint
);
1478 if (ret
!= ERROR_OK
)
1481 stm8
->num_hw_bpoints_avail
--;
1485 ret
= stm8_set_breakpoint(target
, breakpoint
);
1486 if (ret
!= ERROR_OK
)
1492 static int stm8_unset_breakpoint(struct target
*target
,
1493 struct breakpoint
*breakpoint
)
1495 /* get pointers to arch-specific information */
1496 struct stm8_common
*stm8
= target_to_stm8(target
);
1497 struct stm8_comparator
*comparator_list
= stm8
->hw_break_list
;
1500 if (!breakpoint
->set
) {
1501 LOG_WARNING("breakpoint not set");
1505 if (breakpoint
->type
== BKPT_HARD
) {
1506 int bp_num
= breakpoint
->set
- 1;
1507 if ((bp_num
< 0) || (bp_num
>= stm8
->num_hw_bpoints
)) {
1508 LOG_DEBUG("Invalid comparator number in breakpoint (bpid: %" PRIu32
")",
1509 breakpoint
->unique_id
);
1512 LOG_DEBUG("bpid: %" PRIu32
" - releasing hw: %d",
1513 breakpoint
->unique_id
,
1515 comparator_list
[bp_num
].used
= false;
1516 retval
= stm8_set_hwbreak(target
, comparator_list
);
1517 if (retval
!= ERROR_OK
)
1520 /* restore original instruction (kept in target endianness) */
1521 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
1522 if (breakpoint
->length
== 1) {
1523 uint8_t current_instr
;
1525 /* check that user program has not
1526 modified breakpoint instruction */
1527 retval
= target_read_memory(target
, breakpoint
->address
, 1, 1,
1528 (uint8_t *)¤t_instr
);
1529 if (retval
!= ERROR_OK
)
1532 if (current_instr
== STM8_BREAK
) {
1533 retval
= target_write_memory(target
, breakpoint
->address
, 1, 1,
1534 breakpoint
->orig_instr
);
1535 if (retval
!= ERROR_OK
)
1541 breakpoint
->set
= 0;
1546 static int stm8_remove_breakpoint(struct target
*target
,
1547 struct breakpoint
*breakpoint
)
1549 /* get pointers to arch-specific information */
1550 struct stm8_common
*stm8
= target_to_stm8(target
);
1552 if (target
->state
!= TARGET_HALTED
) {
1553 LOG_WARNING("target not halted");
1554 return ERROR_TARGET_NOT_HALTED
;
1557 if (breakpoint
->set
)
1558 stm8_unset_breakpoint(target
, breakpoint
);
1560 if (breakpoint
->type
== BKPT_HARD
)
1561 stm8
->num_hw_bpoints_avail
++;
1566 static int stm8_set_watchpoint(struct target
*target
,
1567 struct watchpoint
*watchpoint
)
1569 struct stm8_common
*stm8
= target_to_stm8(target
);
1570 struct stm8_comparator
*comparator_list
= stm8
->hw_break_list
;
1574 if (watchpoint
->set
) {
1575 LOG_WARNING("watchpoint already set");
1579 while (comparator_list
[wp_num
].used
&& (wp_num
< stm8
->num_hw_bpoints
))
1581 if (wp_num
>= stm8
->num_hw_bpoints
) {
1582 LOG_ERROR("Can not find free hw breakpoint");
1583 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1586 if (watchpoint
->length
!= 1) {
1587 LOG_ERROR("Only watchpoints of length 1 are supported");
1588 return ERROR_TARGET_UNALIGNED_ACCESS
;
1591 enum hw_break_type enable
= 0;
1593 switch (watchpoint
->rw
) {
1604 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
1607 comparator_list
[wp_num
].used
= true;
1608 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
1609 comparator_list
[wp_num
].type
= enable
;
1611 ret
= stm8_set_hwbreak(target
, comparator_list
);
1612 if (ret
!= ERROR_OK
) {
1613 comparator_list
[wp_num
].used
= false;
1617 watchpoint
->set
= wp_num
+ 1;
1619 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"",
1621 comparator_list
[wp_num
].bp_value
);
1626 static int stm8_add_watchpoint(struct target
*target
,
1627 struct watchpoint
*watchpoint
)
1630 struct stm8_common
*stm8
= target_to_stm8(target
);
1632 if (stm8
->num_hw_bpoints_avail
< 1) {
1633 LOG_INFO("no hardware watchpoints available");
1634 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1637 ret
= stm8_set_watchpoint(target
, watchpoint
);
1638 if (ret
!= ERROR_OK
)
1641 stm8
->num_hw_bpoints_avail
--;
1645 static void stm8_enable_watchpoints(struct target
*target
)
1647 struct watchpoint
*watchpoint
= target
->watchpoints
;
1649 /* set any pending watchpoints */
1650 while (watchpoint
) {
1651 if (watchpoint
->set
== 0)
1652 stm8_set_watchpoint(target
, watchpoint
);
1653 watchpoint
= watchpoint
->next
;
1657 static int stm8_unset_watchpoint(struct target
*target
,
1658 struct watchpoint
*watchpoint
)
1660 /* get pointers to arch-specific information */
1661 struct stm8_common
*stm8
= target_to_stm8(target
);
1662 struct stm8_comparator
*comparator_list
= stm8
->hw_break_list
;
1664 if (!watchpoint
->set
) {
1665 LOG_WARNING("watchpoint not set");
1669 int wp_num
= watchpoint
->set
- 1;
1670 if ((wp_num
< 0) || (wp_num
>= stm8
->num_hw_bpoints
)) {
1671 LOG_DEBUG("Invalid hw comparator number in watchpoint");
1674 comparator_list
[wp_num
].used
= false;
1675 watchpoint
->set
= 0;
1677 stm8_set_hwbreak(target
, comparator_list
);
1682 static int stm8_remove_watchpoint(struct target
*target
,
1683 struct watchpoint
*watchpoint
)
1685 /* get pointers to arch-specific information */
1686 struct stm8_common
*stm8
= target_to_stm8(target
);
1688 if (target
->state
!= TARGET_HALTED
) {
1689 LOG_WARNING("target not halted");
1690 return ERROR_TARGET_NOT_HALTED
;
1693 if (watchpoint
->set
)
1694 stm8_unset_watchpoint(target
, watchpoint
);
1696 stm8
->num_hw_bpoints_avail
++;
1701 static int stm8_examine(struct target
*target
)
1705 /* get pointers to arch-specific information */
1706 struct stm8_common
*stm8
= target_to_stm8(target
);
1707 struct hl_interface_s
*adapter
= target_to_adapter(target
);
1709 if (!target_was_examined(target
)) {
1710 if (!stm8
->swim_configured
) {
1711 /* set SWIM_CSR = 0xa0 (enable mem access & mask reset) */
1712 LOG_DEBUG("writing A0 to SWIM_CSR (SAFE_MASK + SWIM_DM)");
1713 retval
= stm8_write_u8(target
, SWIM_CSR
, SAFE_MASK
+ SWIM_DM
);
1714 if (retval
!= ERROR_OK
)
1716 /* set high speed */
1717 LOG_DEBUG("writing B0 to SWIM_CSR (SAFE_MASK + SWIM_DM + HS)");
1718 retval
= stm8_write_u8(target
, SWIM_CSR
, SAFE_MASK
+ SWIM_DM
+ HS
);
1719 if (retval
!= ERROR_OK
)
1721 retval
= stm8_set_speed(target
, 1);
1722 if (retval
== ERROR_OK
)
1723 stm8
->swim_configured
= true;
1725 Now is the time to deassert reset if connect_under_reset.
1726 Releasing reset line will cause the option bytes to load.
1727 The core will still be stalled.
1729 if (adapter
->param
.connect_under_reset
)
1730 stm8_reset_deassert(target
);
1732 LOG_INFO("trying to reconnect");
1734 retval
= adapter
->layout
->api
->state(adapter
->handle
);
1735 if (retval
!= ERROR_OK
) {
1736 LOG_ERROR("reconnect failed");
1740 /* read dm_csrx control regs */
1741 retval
= stm8_read_dm_csrx(target
, &csr1
, &csr2
);
1742 if (retval
!= ERROR_OK
) {
1743 LOG_ERROR("state query failed");
1748 target_set_examined(target
);
1756 /** Checks whether a memory region is erased. */
1757 static int stm8_blank_check_memory(struct target
*target
,
1758 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
)
1760 struct working_area
*erase_check_algorithm
;
1761 struct reg_param reg_params
[2];
1762 struct mem_param mem_params
[2];
1763 struct stm8_algorithm stm8_info
;
1765 static const uint8_t stm8_erase_check_code
[] = {
1766 #include "../../contrib/loaders/erase_check/stm8_erase_check.inc"
1769 if (erased_value
!= 0xff) {
1770 LOG_ERROR("Erase value 0x%02" PRIx8
" not yet supported for STM8",
1775 /* make sure we have a working area */
1776 if (target_alloc_working_area(target
, sizeof(stm8_erase_check_code
),
1777 &erase_check_algorithm
) != ERROR_OK
)
1778 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1780 target_write_buffer(target
, erase_check_algorithm
->address
,
1781 sizeof(stm8_erase_check_code
), stm8_erase_check_code
);
1783 stm8_info
.common_magic
= STM8_COMMON_MAGIC
;
1785 init_mem_param(&mem_params
[0], 0x0, 3, PARAM_OUT
);
1786 buf_set_u32(mem_params
[0].value
, 0, 24, blocks
[0].address
);
1788 init_mem_param(&mem_params
[1], 0x3, 3, PARAM_OUT
);
1789 buf_set_u32(mem_params
[1].value
, 0, 24, blocks
[0].size
);
1791 init_reg_param(®_params
[0], "a", 32, PARAM_IN_OUT
);
1792 buf_set_u32(reg_params
[0].value
, 0, 32, erased_value
);
1794 init_reg_param(®_params
[1], "sp", 32, PARAM_OUT
);
1795 buf_set_u32(reg_params
[1].value
, 0, 32, erase_check_algorithm
->address
);
1797 int retval
= target_run_algorithm(target
, 2, mem_params
, 2, reg_params
,
1798 erase_check_algorithm
->address
+ 6,
1799 erase_check_algorithm
->address
+ (sizeof(stm8_erase_check_code
) - 1),
1802 if (retval
== ERROR_OK
)
1803 blocks
[0].result
= (*(reg_params
[0].value
) == 0xff);
1805 destroy_mem_param(&mem_params
[0]);
1806 destroy_mem_param(&mem_params
[1]);
1807 destroy_reg_param(®_params
[0]);
1808 destroy_reg_param(®_params
[1]);
1810 target_free_working_area(target
, erase_check_algorithm
);
1812 if (retval
!= ERROR_OK
)
1815 return 1; /* only one block has been checked */
1818 static int stm8_checksum_memory(struct target
*target
, target_addr_t address
,
1819 uint32_t count
, uint32_t *checksum
)
1821 /* let image_calculate_checksum() take care of business */
1822 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1825 /* run to exit point. return error if exit point was not reached. */
1826 static int stm8_run_and_wait(struct target
*target
, uint32_t entry_point
,
1827 int timeout_ms
, uint32_t exit_point
, struct stm8_common
*stm8
)
1831 /* This code relies on the target specific resume() and
1832 poll()->debug_entry() sequence to write register values to the
1833 processor and the read them back */
1834 retval
= target_resume(target
, 0, entry_point
, 0, 1);
1835 if (retval
!= ERROR_OK
)
1838 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
1839 /* If the target fails to halt due to the breakpoint, force a halt */
1840 if (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
) {
1841 retval
= target_halt(target
);
1842 if (retval
!= ERROR_OK
)
1844 retval
= target_wait_state(target
, TARGET_HALTED
, 500);
1845 if (retval
!= ERROR_OK
)
1847 return ERROR_TARGET_TIMEOUT
;
1850 pc
= buf_get_u32(stm8
->core_cache
->reg_list
[STM8_PC
].value
, 0, 32);
1851 if (exit_point
&& (pc
!= exit_point
)) {
1852 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32
" ", pc
);
1853 return ERROR_TARGET_TIMEOUT
;
1859 static int stm8_run_algorithm(struct target
*target
, int num_mem_params
,
1860 struct mem_param
*mem_params
, int num_reg_params
,
1861 struct reg_param
*reg_params
, target_addr_t entry_point
,
1862 target_addr_t exit_point
, int timeout_ms
, void *arch_info
)
1864 struct stm8_common
*stm8
= target_to_stm8(target
);
1866 uint32_t context
[STM8_NUM_REGS
];
1867 int retval
= ERROR_OK
;
1869 LOG_DEBUG("Running algorithm");
1871 /* NOTE: stm8_run_algorithm requires that each
1872 algorithm uses a software breakpoint
1873 at the exit point */
1875 if (stm8
->common_magic
!= STM8_COMMON_MAGIC
) {
1876 LOG_ERROR("current target isn't a STM8 target");
1877 return ERROR_TARGET_INVALID
;
1880 if (target
->state
!= TARGET_HALTED
) {
1881 LOG_WARNING("target not halted");
1882 return ERROR_TARGET_NOT_HALTED
;
1885 /* refresh core register cache */
1886 for (unsigned int i
= 0; i
< STM8_NUM_REGS
; i
++) {
1887 if (!stm8
->core_cache
->reg_list
[i
].valid
)
1888 stm8
->read_core_reg(target
, i
);
1889 context
[i
] = buf_get_u32(stm8
->core_cache
->reg_list
[i
].value
, 0, 32);
1892 for (int i
= 0; i
< num_mem_params
; i
++) {
1893 if (mem_params
[i
].direction
== PARAM_IN
)
1895 retval
= target_write_buffer(target
, mem_params
[i
].address
,
1896 mem_params
[i
].size
, mem_params
[i
].value
);
1897 if (retval
!= ERROR_OK
)
1901 for (int i
= 0; i
< num_reg_params
; i
++) {
1902 if (reg_params
[i
].direction
== PARAM_IN
)
1905 struct reg
*reg
= register_get_by_name(stm8
->core_cache
,
1906 reg_params
[i
].reg_name
, 0);
1909 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1910 return ERROR_COMMAND_SYNTAX_ERROR
;
1913 if (reg_params
[i
].size
!= 32) {
1914 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1915 reg_params
[i
].reg_name
);
1916 return ERROR_COMMAND_SYNTAX_ERROR
;
1919 stm8_set_core_reg(reg
, reg_params
[i
].value
);
1922 retval
= stm8_run_and_wait(target
, entry_point
,
1923 timeout_ms
, exit_point
, stm8
);
1925 if (retval
!= ERROR_OK
)
1928 for (int i
= 0; i
< num_mem_params
; i
++) {
1929 if (mem_params
[i
].direction
!= PARAM_OUT
) {
1930 retval
= target_read_buffer(target
, mem_params
[i
].address
,
1931 mem_params
[i
].size
, mem_params
[i
].value
);
1932 if (retval
!= ERROR_OK
)
1937 for (int i
= 0; i
< num_reg_params
; i
++) {
1938 if (reg_params
[i
].direction
!= PARAM_OUT
) {
1939 struct reg
*reg
= register_get_by_name(stm8
->core_cache
,
1940 reg_params
[i
].reg_name
, 0);
1942 LOG_ERROR("BUG: register '%s' not found",
1943 reg_params
[i
].reg_name
);
1944 return ERROR_COMMAND_SYNTAX_ERROR
;
1947 if (reg_params
[i
].size
!= 32) {
1948 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1949 reg_params
[i
].reg_name
);
1950 return ERROR_COMMAND_SYNTAX_ERROR
;
1953 buf_set_u32(reg_params
[i
].value
,
1954 0, 32, buf_get_u32(reg
->value
, 0, 32));
1958 /* restore everything we saved before */
1959 for (unsigned int i
= 0; i
< STM8_NUM_REGS
; i
++) {
1961 regvalue
= buf_get_u32(stm8
->core_cache
->reg_list
[i
].value
, 0, 32);
1962 if (regvalue
!= context
[i
]) {
1963 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
,
1964 stm8
->core_cache
->reg_list
[i
].name
, context
[i
]);
1965 buf_set_u32(stm8
->core_cache
->reg_list
[i
].value
,
1967 stm8
->core_cache
->reg_list
[i
].valid
= true;
1968 stm8
->core_cache
->reg_list
[i
].dirty
= true;
1975 int stm8_jim_configure(struct target
*target
, Jim_GetOptInfo
*goi
)
1977 struct stm8_common
*stm8
= target_to_stm8(target
);
1982 arg
= Jim_GetString(goi
->argv
[0], NULL
);
1983 if (!strcmp(arg
, "-blocksize")) {
1984 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
1988 if (goi
->argc
== 0) {
1989 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
,
1990 "-blocksize ?bytes? ...");
1994 e
= Jim_GetOpt_Wide(goi
, &w
);
1998 stm8
->blocksize
= w
;
1999 LOG_DEBUG("blocksize=%8.8x", stm8
->blocksize
);
2002 if (!strcmp(arg
, "-flashstart")) {
2003 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2007 if (goi
->argc
== 0) {
2008 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
,
2009 "-flashstart ?address? ...");
2013 e
= Jim_GetOpt_Wide(goi
, &w
);
2017 stm8
->flashstart
= w
;
2018 LOG_DEBUG("flashstart=%8.8x", stm8
->flashstart
);
2021 if (!strcmp(arg
, "-flashend")) {
2022 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2026 if (goi
->argc
== 0) {
2027 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
,
2028 "-flashend ?address? ...");
2032 e
= Jim_GetOpt_Wide(goi
, &w
);
2037 LOG_DEBUG("flashend=%8.8x", stm8
->flashend
);
2040 if (!strcmp(arg
, "-eepromstart")) {
2041 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2045 if (goi
->argc
== 0) {
2046 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
,
2047 "-eepromstart ?address? ...");
2051 e
= Jim_GetOpt_Wide(goi
, &w
);
2055 stm8
->eepromstart
= w
;
2056 LOG_DEBUG("eepromstart=%8.8x", stm8
->eepromstart
);
2059 if (!strcmp(arg
, "-eepromend")) {
2060 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2064 if (goi
->argc
== 0) {
2065 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
,
2066 "-eepromend ?address? ...");
2070 e
= Jim_GetOpt_Wide(goi
, &w
);
2074 stm8
->eepromend
= w
;
2075 LOG_DEBUG("eepromend=%8.8x", stm8
->eepromend
);
2078 if (!strcmp(arg
, "-optionstart")) {
2079 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2083 if (goi
->argc
== 0) {
2084 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
,
2085 "-optionstart ?address? ...");
2089 e
= Jim_GetOpt_Wide(goi
, &w
);
2093 stm8
->optionstart
= w
;
2094 LOG_DEBUG("optionstart=%8.8x", stm8
->optionstart
);
2097 if (!strcmp(arg
, "-optionend")) {
2098 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2102 if (goi
->argc
== 0) {
2103 Jim_WrongNumArgs(goi
->interp
, goi
->argc
, goi
->argv
,
2104 "-optionend ?address? ...");
2108 e
= Jim_GetOpt_Wide(goi
, &w
);
2112 stm8
->optionend
= w
;
2113 LOG_DEBUG("optionend=%8.8x", stm8
->optionend
);
2116 if (!strcmp(arg
, "-enable_step_irq")) {
2117 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2121 stm8
->enable_step_irq
= true;
2122 LOG_DEBUG("enable_step_irq=%8.8x", stm8
->enable_step_irq
);
2125 if (!strcmp(arg
, "-enable_stm8l")) {
2126 e
= Jim_GetOpt_String(goi
, &arg
, NULL
);
2130 stm8
->enable_stm8l
= true;
2131 LOG_DEBUG("enable_stm8l=%8.8x", stm8
->enable_stm8l
);
2132 stm8_init_flash_regs(stm8
->enable_stm8l
, stm8
);
2135 return JIM_CONTINUE
;
2138 COMMAND_HANDLER(stm8_handle_enable_step_irq_command
)
2141 struct target
*target
= get_current_target(CMD_CTX
);
2142 struct stm8_common
*stm8
= target_to_stm8(target
);
2143 bool enable
= stm8
->enable_step_irq
;
2146 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
2147 stm8
->enable_step_irq
= enable
;
2149 msg
= stm8
->enable_step_irq
? "enabled" : "disabled";
2150 command_print(CMD_CTX
, "enable_step_irq = %s", msg
);
2154 COMMAND_HANDLER(stm8_handle_enable_stm8l_command
)
2157 struct target
*target
= get_current_target(CMD_CTX
);
2158 struct stm8_common
*stm8
= target_to_stm8(target
);
2159 bool enable
= stm8
->enable_stm8l
;
2162 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
2163 stm8
->enable_stm8l
= enable
;
2165 msg
= stm8
->enable_stm8l
? "enabled" : "disabled";
2166 command_print(CMD_CTX
, "enable_stm8l = %s", msg
);
2167 stm8_init_flash_regs(stm8
->enable_stm8l
, stm8
);
2171 static const struct command_registration stm8_exec_command_handlers
[] = {
2173 .name
= "enable_step_irq",
2174 .handler
= stm8_handle_enable_step_irq_command
,
2175 .mode
= COMMAND_ANY
,
2176 .help
= "Enable/disable irq handling during step",
2180 .name
= "enable_stm8l",
2181 .handler
= stm8_handle_enable_stm8l_command
,
2182 .mode
= COMMAND_ANY
,
2183 .help
= "Enable/disable STM8L flash programming",
2186 COMMAND_REGISTRATION_DONE
2189 const struct command_registration stm8_command_handlers
[] = {
2192 .mode
= COMMAND_ANY
,
2193 .help
= "stm8 command group",
2195 .chain
= stm8_exec_command_handlers
,
2197 COMMAND_REGISTRATION_DONE
2200 struct target_type stm8_target
= {
2204 .arch_state
= stm8_arch_state
,
2207 .resume
= stm8_resume
,
2210 .assert_reset
= stm8_reset_assert
,
2211 .deassert_reset
= stm8_reset_deassert
,
2213 .get_gdb_arch
= stm8_get_gdb_arch
,
2214 .get_gdb_reg_list
= stm8_get_gdb_reg_list
,
2216 .read_memory
= stm8_read_memory
,
2217 .write_memory
= stm8_write_memory
,
2218 .checksum_memory
= stm8_checksum_memory
,
2219 .blank_check_memory
= stm8_blank_check_memory
,
2221 .run_algorithm
= stm8_run_algorithm
,
2223 .add_breakpoint
= stm8_add_breakpoint
,
2224 .remove_breakpoint
= stm8_remove_breakpoint
,
2225 .add_watchpoint
= stm8_add_watchpoint
,
2226 .remove_watchpoint
= stm8_remove_watchpoint
,
2228 .commands
= stm8_command_handlers
,
2229 .target_create
= stm8_target_create
,
2230 .init_target
= stm8_init
,
2231 .examine
= stm8_examine
,
2233 .deinit_target
= stm8_deinit
,
2234 .target_jim_configure
= stm8_jim_configure
,
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