src/target/target/at91sam9260.cfg

   1 # Thanks to Pieter Conradie for this script!
   2 # Target:    Atmel AT91SAM9260
   3 ######################################
   4
   5 reset_config trst_and_srst
   6
   7 #jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
   8 jtag_device 4 0x1 0xf 0xe
   9
  10 jtag_nsrst_delay 200
  11 jtag_ntrst_delay 0
  12
  13 ######################
  14 # Target configuration
  15 ######################
  16
  17 target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
  18
  19 [new_target_name] configure -event reset-init {
  20         mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
  21         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
  22
  23         mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
  24         sleep 20                          # wait 20 ms
  25         mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
  26         sleep 10                          # wait 10 ms
  27         mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
  28         sleep 20                          # wait 20 ms
  29         mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
  30         sleep 10                          # wait 10 ms
  31         mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
  32         sleep 10                          # wait 10 ms
  33
  34         jtag_speed 0                      # Increase JTAG Speed to 6 MHz
  35         arm7_9 dcc_downloads enable       # Enable faster DCC downloads
  36
  37         mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
  38         mww 0xffffec04 0x09070806         # SMC_PULSE0
  39         mww 0xffffec08 0x000d000b         # SMC_CYCLE0
  40         mww 0xffffec0c 0x00001003         # SMC_MODE0
  41
  42         flash probe 0                     # Identify flash bank 0
  43
  44         mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
  45         mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
  46
  47         mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
  48
  49         #mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  50         mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
  51
  52         mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
  53         mww 0x20000000 0
  54         mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
  55         mww 0x20000000 0
  56         mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
  57         mww 0x20000000 0
  58         mww 0xffffea00 0x4
  59         mww 0x20000000 0
  60         mww 0xffffea00 0x4
  61         mww 0x20000000 0
  62         mww 0xffffea00 0x4
  63         mww 0x20000000 0
  64         mww 0xffffea00 0x4
  65         mww 0x20000000 0
  66         mww 0xffffea00 0x4
  67         mww 0x20000000 0
  68         mww 0xffffea00 0x4
  69         mww 0x20000000 0
  70         mww 0xffffea00 0x4
  71         mww 0x20000000 0
  72         mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
  73         mww 0x20000000 0
  74         mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
  75         mww 0x20000000 0
  76         mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
  77 }
  78
  79 [new_target_name] configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
  80
  81 #####################
  82 # Flash configuration
  83 #####################
  84
  85 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
  86 flash bank cfi 0x10000000 0x01000000 2 2 0
  87