src/target/target/wi-9c.cfg

   1 ######################################
   2 # Target: DIGI ConnectCore Wi-9C
   3 ######################################
   4
   5 reset_config trst_and_srst
   6
   7 #jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
   8 jtag_device 4 0x1 0xf 0xe
   9
  10 jtag_nsrst_delay 200
  11 jtag_ntrst_delay 0
  12
  13 ######################
  14 # Target configuration
  15 ######################
  16
  17 target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs
  18 [new_target_name] configure -event reset-init {
  19         mww 0x90600104 0x33313333
  20         mww 0xA0700000 0x00000001  # Enable the memory controller.
  21         mww 0xA0700024 0x00000006  # Set the refresh counter 6
  22         mww 0xA0700028 0x00000001  #
  23         mww 0xA0700030 0x00000001  # Set the precharge period
  24         mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles
  25         mww 0xA070003C 0x00000001  # tAPR
  26         mww 0xA0700040 0x00000005  # tDAL
  27         mww 0xA0700044 0x00000001  # tWR
  28         mww 0xA0700048 0x00000006  # tRC 32 clock cycles
  29         mww 0xA070004C 0x00000006  # tRFC 32 clock cycles
  30         mww 0xA0700054 0x00000001  # tRRD
  31         mww 0xA0700058 0x00000001  # tMRD
  32         mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4)
  33         mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)
  34         mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)
  35         mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)
  36         #
  37         mww 0xA0700104 0x00000203  # CAS latency is 2 at 100 MHz
  38         mww 0xA0700124 0x00000203  # CAS latency is 2 at 100 MHz
  39         mww 0xA0700144 0x00000203  # CAS latency is 2 at 100 MHz
  40         mww 0xA0700164 0x00000203  # CAS latency is 2 at 100 MHz
  41         #
  42         mww 0xA0700020 0x00000103  # issue SDRAM PALL command
  43         #
  44         mww 0xA0700024 0x00000001  # Set the refresh counter to be as small as possible
  45         #
  46         # Add some dummy writes to give the SDRAM time to settle, it needs two
  47         # AHB clock cycles, here we poke in the debugger flag, this lets
  48         # the software know that we are in the debugger
  49         mww 0xA0900000 0x00000002
  50         mww 0xA0900000 0x00000002
  51         mww 0xA0900000 0x00000002
  52         mww 0xA0900000 0x00000002
  53         mww 0xA0900000 0x00000002
  54         #
  55         mdw 0xA0900000
  56         mdw 0xA0900000
  57         mdw 0xA0900000
  58         mdw 0xA0900000
  59         mdw 0xA0900000
  60         #
  61         mww 0xA0700024 0x00000030 # Set the refresh counter to 30
  62         mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
  63         #
  64         # Next we perform a read of RAM.
  65         # mw = move word.
  66         mdw 0x00022000
  67         # mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
  68         #
  69         mww 0xA0700020 0x00000003   # issue SDRAM NORMAL command
  70         mww 0xA0700100 0x00084280   # Enable buffer access
  71         mww 0xA0700120 0x00084280   # Enable buffer access
  72         mww 0xA0700140 0x00084280   # Enable buffer access
  73         mww 0xA0700160 0x00084280   # Enable buffer access
  74
  75         #Set byte lane state (static mem 1)"
  76         mww 0xA0700220, 0x00000082
  77         #Flash Start
  78         mww 0xA09001F8, 0x50000000
  79         #Flash Mask Reg
  80         mww 0xA09001FC, 0xFF000001
  81         mww 0xA0700028, 0x00000001
  82
  83         #  RAMAddr = 0x00020000
  84         #  RAMSize = 0x00004000
  85
  86         # Set the processor mode
  87         reg cpsr 0xd3
  88 }
  89
  90 [new_target_name] configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
  91
  92 #####################
  93 # Flash configuration
  94 #####################
  95
  96 #M29DW323DB - not working
  97 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
  98 flash bank cfi 0x50000000 0x0400000 2 2 0
  99
 100
 101