1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "arm_simulator.h"
32 #include "arm_disassembler.h"
35 #include "binarybuffer.h"
36 #include "time_support.h"
37 #include "breakpoints.h"
43 #include <sys/types.h>
49 int xscale_register_commands(struct command_context_s
*cmd_ctx
);
51 /* forward declarations */
52 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
53 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
56 int xscale_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
57 enum target_state
xscale_poll(target_t
*target
);
58 int xscale_halt(target_t
*target
);
59 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
60 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
61 int xscale_debug_entry(target_t
*target
);
62 int xscale_restore_context(target_t
*target
);
64 int xscale_assert_reset(target_t
*target
);
65 int xscale_deassert_reset(target_t
*target
);
66 int xscale_soft_reset_halt(struct target_s
*target
);
67 int xscale_prepare_reset_halt(struct target_s
*target
);
69 int xscale_set_reg_u32(reg_t
*reg
, u32 value
);
71 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
72 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
);
74 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
75 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
76 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
);
77 int xscale_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
);
79 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
80 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
81 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
82 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
83 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
84 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
85 void xscale_enable_watchpoints(struct target_s
*target
);
86 void xscale_enable_breakpoints(struct target_s
*target
);
88 int xscale_read_trace(target_t
*target
);
90 target_type_t xscale_target
=
95 .arch_state
= xscale_arch_state
,
97 .target_request_data
= NULL
,
100 .resume
= xscale_resume
,
103 .assert_reset
= xscale_assert_reset
,
104 .deassert_reset
= xscale_deassert_reset
,
105 .soft_reset_halt
= xscale_soft_reset_halt
,
106 .prepare_reset_halt
= xscale_prepare_reset_halt
,
108 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
110 .read_memory
= xscale_read_memory
,
111 .write_memory
= xscale_write_memory
,
112 .bulk_write_memory
= xscale_bulk_write_memory
,
113 .checksum_memory
= xscale_checksum_memory
,
115 .run_algorithm
= armv4_5_run_algorithm
,
117 .add_breakpoint
= xscale_add_breakpoint
,
118 .remove_breakpoint
= xscale_remove_breakpoint
,
119 .add_watchpoint
= xscale_add_watchpoint
,
120 .remove_watchpoint
= xscale_remove_watchpoint
,
122 .register_commands
= xscale_register_commands
,
123 .target_command
= xscale_target_command
,
124 .init_target
= xscale_init_target
,
128 char* xscale_reg_list
[] =
130 "XSCALE_MAINID", /* 0 */
140 "XSCALE_IBCR0", /* 10 */
150 "XSCALE_RX", /* 20 */
154 xscale_reg_t xscale_reg_arch_info
[] =
156 {XSCALE_MAINID
, NULL
},
157 {XSCALE_CACHETYPE
, NULL
},
159 {XSCALE_AUXCTRL
, NULL
},
165 {XSCALE_CPACCESS
, NULL
},
166 {XSCALE_IBCR0
, NULL
},
167 {XSCALE_IBCR1
, NULL
},
170 {XSCALE_DBCON
, NULL
},
171 {XSCALE_TBREG
, NULL
},
172 {XSCALE_CHKPT0
, NULL
},
173 {XSCALE_CHKPT1
, NULL
},
174 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
175 {-1, NULL
}, /* TX accessed via JTAG */
176 {-1, NULL
}, /* RX accessed via JTAG */
177 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
180 int xscale_reg_arch_type
= -1;
182 int xscale_get_reg(reg_t
*reg
);
183 int xscale_set_reg(reg_t
*reg
, u8
*buf
);
185 int xscale_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
187 armv4_5_common_t
*armv4_5
= target
->arch_info
;
188 xscale_common_t
*xscale
= armv4_5
->arch_info
;
190 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
195 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
200 *armv4_5_p
= armv4_5
;
206 int xscale_jtag_set_instr(int chain_pos
, u32 new_instr
)
208 jtag_device_t
*device
= jtag_get_device(chain_pos
);
210 if (buf_get_u32(device
->cur_instr
, 0, device
->ir_length
) != new_instr
)
214 field
.device
= chain_pos
;
215 field
.num_bits
= device
->ir_length
;
216 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
217 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
218 field
.out_mask
= NULL
;
219 field
.in_value
= NULL
;
220 field
.in_check_value
= device
->expected
;
221 field
.in_check_mask
= device
->expected_mask
;
222 field
.in_handler
= NULL
;
223 field
.in_handler_priv
= NULL
;
225 jtag_add_ir_scan(1, &field
, -1, NULL
);
227 free(field
.out_value
);
233 int xscale_jtag_callback(enum jtag_event event
, void *priv
)
237 case JTAG_TRST_ASSERTED
:
239 case JTAG_TRST_RELEASED
:
241 case JTAG_SRST_ASSERTED
:
243 case JTAG_SRST_RELEASED
:
246 WARNING("unhandled JTAG event");
252 int xscale_read_dcsr(target_t
*target
)
254 armv4_5_common_t
*armv4_5
= target
->arch_info
;
255 xscale_common_t
*xscale
= armv4_5
->arch_info
;
259 scan_field_t fields
[3];
261 u8 field0_check_value
= 0x2;
262 u8 field0_check_mask
= 0x7;
264 u8 field2_check_value
= 0x0;
265 u8 field2_check_mask
= 0x1;
267 jtag_add_end_state(TAP_PD
);
268 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
270 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
271 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
273 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
274 fields
[0].num_bits
= 3;
275 fields
[0].out_value
= &field0
;
276 fields
[0].out_mask
= NULL
;
277 fields
[0].in_value
= NULL
;
278 fields
[0].in_check_value
= &field0_check_value
;
279 fields
[0].in_check_mask
= &field0_check_mask
;
280 fields
[0].in_handler
= NULL
;
281 fields
[0].in_handler_priv
= NULL
;
283 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
284 fields
[1].num_bits
= 32;
285 fields
[1].out_value
= NULL
;
286 fields
[1].out_mask
= NULL
;
287 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
288 fields
[1].in_handler
= NULL
;
289 fields
[1].in_handler_priv
= NULL
;
290 fields
[1].in_check_value
= NULL
;
291 fields
[1].in_check_mask
= NULL
;
293 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
294 fields
[2].num_bits
= 1;
295 fields
[2].out_value
= &field2
;
296 fields
[2].out_mask
= NULL
;
297 fields
[2].in_value
= NULL
;
298 fields
[2].in_check_value
= &field2_check_value
;
299 fields
[2].in_check_mask
= &field2_check_mask
;
300 fields
[2].in_handler
= NULL
;
301 fields
[2].in_handler_priv
= NULL
;
303 jtag_add_dr_scan(3, fields
, -1, NULL
);
305 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
307 ERROR("JTAG error while reading DCSR");
311 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
312 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
314 /* write the register with the value we just read
315 * on this second pass, only the first bit of field0 is guaranteed to be 0)
317 field0_check_mask
= 0x1;
318 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
319 fields
[1].in_value
= NULL
;
321 jtag_add_end_state(TAP_RTI
);
323 jtag_add_dr_scan(3, fields
, -1, NULL
);
328 int xscale_receive(target_t
*target
, u32
*buffer
, int num_words
)
330 armv4_5_common_t
*armv4_5
= target
->arch_info
;
331 xscale_common_t
*xscale
= armv4_5
->arch_info
;
333 enum tap_state path
[3];
334 scan_field_t fields
[3];
336 u8
*field0
= malloc(num_words
* 1);
337 u8 field0_check_value
= 0x2;
338 u8 field0_check_mask
= 0x6;
339 u32
*field1
= malloc(num_words
* 4);
340 u8 field2_check_value
= 0x0;
341 u8 field2_check_mask
= 0x1;
343 int words_scheduled
= 0;
352 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
353 fields
[0].num_bits
= 3;
354 fields
[0].out_value
= NULL
;
355 fields
[0].out_mask
= NULL
;
356 /* fields[0].in_value = field0; */
357 fields
[0].in_check_value
= &field0_check_value
;
358 fields
[0].in_check_mask
= &field0_check_mask
;
359 fields
[0].in_handler
= NULL
;
360 fields
[0].in_handler_priv
= NULL
;
362 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
363 fields
[1].num_bits
= 32;
364 fields
[1].out_value
= NULL
;
365 fields
[1].out_mask
= NULL
;
366 fields
[1].in_value
= NULL
;
367 fields
[1].in_handler
= NULL
;
368 fields
[1].in_handler_priv
= NULL
;
369 fields
[1].in_check_value
= NULL
;
370 fields
[1].in_check_mask
= NULL
;
372 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
373 fields
[2].num_bits
= 1;
374 fields
[2].out_value
= NULL
;
375 fields
[2].out_mask
= NULL
;
376 fields
[2].in_value
= NULL
;
377 fields
[2].in_check_value
= &field2_check_value
;
378 fields
[2].in_check_mask
= &field2_check_mask
;
379 fields
[2].in_handler
= NULL
;
380 fields
[2].in_handler_priv
= NULL
;
382 jtag_add_end_state(TAP_RTI
);
383 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
384 jtag_add_runtest(1, -1);
386 /* repeat until all words have been collected */
387 while (words_done
< num_words
)
391 for (i
= words_done
; i
< num_words
; i
++)
393 fields
[0].in_value
= &field0
[i
];
394 fields
[1].in_handler
= buf_to_u32_handler
;
395 fields
[1].in_handler_priv
= (u8
*)&field1
[i
];
397 jtag_add_pathmove(3, path
);
398 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
402 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
404 ERROR("JTAG error while receiving data from debug handler");
408 /* examine results */
409 for (i
= words_done
; i
< num_words
; i
++)
411 if (!(field0
[0] & 1))
413 /* move backwards if necessary */
415 for (j
= i
; j
< num_words
- 1; j
++)
417 field0
[j
] = field0
[j
+1];
418 field1
[j
] = field1
[j
+1];
423 words_done
+= words_scheduled
;
426 for (i
= 0; i
< num_words
; i
++)
427 *(buffer
++) = buf_get_u32((u8
*)&field1
[i
], 0, 32);
434 int xscale_read_tx(target_t
*target
, int consume
)
436 armv4_5_common_t
*armv4_5
= target
->arch_info
;
437 xscale_common_t
*xscale
= armv4_5
->arch_info
;
438 enum tap_state path
[3];
441 struct timeval timeout
, now
;
443 scan_field_t fields
[3];
445 u8 field0_check_value
= 0x2;
446 u8 field0_check_mask
= 0x6;
447 u8 field2_check_value
= 0x0;
448 u8 field2_check_mask
= 0x1;
450 jtag_add_end_state(TAP_RTI
);
452 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
458 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
459 fields
[0].num_bits
= 3;
460 fields
[0].out_value
= NULL
;
461 fields
[0].out_mask
= NULL
;
462 fields
[0].in_value
= &field0_in
;
463 fields
[0].in_check_value
= &field0_check_value
;
464 fields
[0].in_check_mask
= &field0_check_mask
;
465 fields
[0].in_handler
= NULL
;
466 fields
[0].in_handler_priv
= NULL
;
468 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
469 fields
[1].num_bits
= 32;
470 fields
[1].out_value
= NULL
;
471 fields
[1].out_mask
= NULL
;
472 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
473 fields
[1].in_handler
= NULL
;
474 fields
[1].in_handler_priv
= NULL
;
475 fields
[1].in_check_value
= NULL
;
476 fields
[1].in_check_mask
= NULL
;
478 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
479 fields
[2].num_bits
= 1;
480 fields
[2].out_value
= NULL
;
481 fields
[2].out_mask
= NULL
;
482 fields
[2].in_value
= NULL
;
483 fields
[2].in_check_value
= &field2_check_value
;
484 fields
[2].in_check_mask
= &field2_check_mask
;
485 fields
[2].in_handler
= NULL
;
486 fields
[2].in_handler_priv
= NULL
;
488 gettimeofday(&timeout
, NULL
);
489 timeval_add_time(&timeout
, 5, 0);
493 /* if we want to consume the register content (i.e. clear TX_READY),
494 * we have to go straight from Capture-DR to Shift-DR
495 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
498 jtag_add_pathmove(3, path
);
500 jtag_add_statemove(TAP_PD
);
502 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
504 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
506 ERROR("JTAG error while reading TX");
510 gettimeofday(&now
, NULL
);
511 if ((now
.tv_sec
> timeout
.tv_sec
) && (now
.tv_usec
> timeout
.tv_usec
))
513 ERROR("time out reading TX register");
514 return ERROR_TARGET_TIMEOUT
;
516 } while ((!(field0_in
& 1)) && consume
);
518 if (!(field0_in
& 1))
519 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
524 int xscale_write_rx(target_t
*target
)
526 armv4_5_common_t
*armv4_5
= target
->arch_info
;
527 xscale_common_t
*xscale
= armv4_5
->arch_info
;
530 struct timeval timeout
, now
;
532 scan_field_t fields
[3];
535 u8 field0_check_value
= 0x2;
536 u8 field0_check_mask
= 0x6;
538 u8 field2_check_value
= 0x0;
539 u8 field2_check_mask
= 0x1;
541 jtag_add_end_state(TAP_RTI
);
543 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
545 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
546 fields
[0].num_bits
= 3;
547 fields
[0].out_value
= &field0_out
;
548 fields
[0].out_mask
= NULL
;
549 fields
[0].in_value
= &field0_in
;
550 fields
[0].in_check_value
= &field0_check_value
;
551 fields
[0].in_check_mask
= &field0_check_mask
;
552 fields
[0].in_handler
= NULL
;
553 fields
[0].in_handler_priv
= NULL
;
555 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
556 fields
[1].num_bits
= 32;
557 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
558 fields
[1].out_mask
= NULL
;
559 fields
[1].in_value
= NULL
;
560 fields
[1].in_handler
= NULL
;
561 fields
[1].in_handler_priv
= NULL
;
562 fields
[1].in_check_value
= NULL
;
563 fields
[1].in_check_mask
= NULL
;
565 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
566 fields
[2].num_bits
= 1;
567 fields
[2].out_value
= &field2
;
568 fields
[2].out_mask
= NULL
;
569 fields
[2].in_value
= NULL
;
570 fields
[2].in_check_value
= &field2_check_value
;
571 fields
[2].in_check_mask
= &field2_check_mask
;
572 fields
[2].in_handler
= NULL
;
573 fields
[2].in_handler_priv
= NULL
;
575 gettimeofday(&timeout
, NULL
);
576 timeval_add_time(&timeout
, 5, 0);
578 /* poll until rx_read is low */
582 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
584 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
586 ERROR("JTAG error while writing RX");
590 gettimeofday(&now
, NULL
);
591 if ((now
.tv_sec
> timeout
.tv_sec
) && (now
.tv_usec
> timeout
.tv_usec
))
593 ERROR("time out writing RX register");
594 return ERROR_TARGET_TIMEOUT
;
596 } while (field0_in
& 1);
600 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
602 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
604 ERROR("JTAG error while writing RX");
611 /* send count elements of size byte to the debug handler */
612 int xscale_send(target_t
*target
, u8
*buffer
, int count
, int size
)
614 armv4_5_common_t
*armv4_5
= target
->arch_info
;
615 xscale_common_t
*xscale
= armv4_5
->arch_info
;
620 u8 output
[4] = {0, 0, 0, 0};
622 scan_field_t fields
[3];
625 u8 field0_check_value
= 0x2;
626 u8 field0_check_mask
= 0x6;
628 u8 field2_check_value
= 0x0;
629 u8 field2_check_mask
= 0x1;
631 jtag_add_end_state(TAP_RTI
);
633 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
635 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
636 fields
[0].num_bits
= 3;
637 fields
[0].out_value
= &field0_out
;
638 fields
[0].out_mask
= NULL
;
639 fields
[0].in_value
= &field0_in
;
640 fields
[0].in_check_value
= &field0_check_value
;
641 fields
[0].in_check_mask
= &field0_check_mask
;
642 fields
[0].in_handler
= NULL
;
643 fields
[0].in_handler_priv
= NULL
;
645 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
646 fields
[1].num_bits
= 32;
647 fields
[1].out_value
= output
;
648 fields
[1].out_mask
= NULL
;
649 fields
[1].in_value
= NULL
;
650 fields
[1].in_handler
= NULL
;
651 fields
[1].in_handler_priv
= NULL
;
652 fields
[1].in_check_value
= NULL
;
653 fields
[1].in_check_mask
= NULL
;
655 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
656 fields
[2].num_bits
= 1;
657 fields
[2].out_value
= &field2
;
658 fields
[2].out_mask
= NULL
;
659 fields
[2].in_value
= NULL
;
660 fields
[2].in_check_value
= &field2_check_value
;
661 fields
[2].in_check_mask
= &field2_check_mask
;
662 fields
[2].in_handler
= NULL
;
663 fields
[2].in_handler_priv
= NULL
;
665 while (done_count
++ < count
)
667 /* extract sized element from target-endian buffer, and put it
668 * into little-endian output buffer
673 buf_set_u32(output
, 0, 32, target_buffer_get_u32(target
, buffer
));
676 buf_set_u32(output
, 0, 32, target_buffer_get_u16(target
, buffer
));
682 ERROR("BUG: size neither 4, 2 nor 1");
686 jtag_add_dr_scan(3, fields
, TAP_RTI
, NULL
);
690 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
692 ERROR("JTAG error while sending data to debug handler");
699 int xscale_send_u32(target_t
*target
, u32 value
)
701 armv4_5_common_t
*armv4_5
= target
->arch_info
;
702 xscale_common_t
*xscale
= armv4_5
->arch_info
;
704 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
705 return xscale_write_rx(target
);
708 int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
710 armv4_5_common_t
*armv4_5
= target
->arch_info
;
711 xscale_common_t
*xscale
= armv4_5
->arch_info
;
715 scan_field_t fields
[3];
717 u8 field0_check_value
= 0x2;
718 u8 field0_check_mask
= 0x7;
720 u8 field2_check_value
= 0x0;
721 u8 field2_check_mask
= 0x1;
724 xscale
->hold_rst
= hold_rst
;
726 if (ext_dbg_brk
!= -1)
727 xscale
->external_debug_break
= ext_dbg_brk
;
729 jtag_add_end_state(TAP_RTI
);
730 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
732 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
733 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
735 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
736 fields
[0].num_bits
= 3;
737 fields
[0].out_value
= &field0
;
738 fields
[0].out_mask
= NULL
;
739 fields
[0].in_value
= NULL
;
740 fields
[0].in_check_value
= &field0_check_value
;
741 fields
[0].in_check_mask
= &field0_check_mask
;
742 fields
[0].in_handler
= NULL
;
743 fields
[0].in_handler_priv
= NULL
;
745 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
746 fields
[1].num_bits
= 32;
747 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
748 fields
[1].out_mask
= NULL
;
749 fields
[1].in_value
= NULL
;
750 fields
[1].in_handler
= NULL
;
751 fields
[1].in_handler_priv
= NULL
;
752 fields
[1].in_check_value
= NULL
;
753 fields
[1].in_check_mask
= NULL
;
755 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
756 fields
[2].num_bits
= 1;
757 fields
[2].out_value
= &field2
;
758 fields
[2].out_mask
= NULL
;
759 fields
[2].in_value
= NULL
;
760 fields
[2].in_check_value
= &field2_check_value
;
761 fields
[2].in_check_mask
= &field2_check_mask
;
762 fields
[2].in_handler
= NULL
;
763 fields
[2].in_handler_priv
= NULL
;
765 jtag_add_dr_scan(3, fields
, -1, NULL
);
767 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
769 ERROR("JTAG error while writing DCSR");
773 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
774 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
779 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
780 unsigned int parity (unsigned int v
)
787 DEBUG("parity of 0x%x is %i", ov
, (0x6996 >> v
) & 1);
788 return (0x6996 >> v
) & 1;
791 int xscale_load_ic(target_t
*target
, int mini
, u32 va
, u32 buffer
[8])
793 armv4_5_common_t
*armv4_5
= target
->arch_info
;
794 xscale_common_t
*xscale
= armv4_5
->arch_info
;
799 scan_field_t fields
[2];
801 DEBUG("loading miniIC at 0x%8.8x", va
);
803 jtag_add_end_state(TAP_RTI
);
804 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
806 /* CMD is b010 for Main IC and b011 for Mini IC */
808 buf_set_u32(&cmd
, 0, 3, 0x3);
810 buf_set_u32(&cmd
, 0, 3, 0x2);
812 buf_set_u32(&cmd
, 3, 3, 0x0);
814 /* virtual address of desired cache line */
815 buf_set_u32(packet
, 0, 27, va
>> 5);
817 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
818 fields
[0].num_bits
= 6;
819 fields
[0].out_value
= &cmd
;
820 fields
[0].out_mask
= NULL
;
821 fields
[0].in_value
= NULL
;
822 fields
[0].in_check_value
= NULL
;
823 fields
[0].in_check_mask
= NULL
;
824 fields
[0].in_handler
= NULL
;
825 fields
[0].in_handler_priv
= NULL
;
827 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
828 fields
[1].num_bits
= 27;
829 fields
[1].out_value
= packet
;
830 fields
[1].out_mask
= NULL
;
831 fields
[1].in_value
= NULL
;
832 fields
[1].in_check_value
= NULL
;
833 fields
[1].in_check_mask
= NULL
;
834 fields
[1].in_handler
= NULL
;
835 fields
[1].in_handler_priv
= NULL
;
837 jtag_add_dr_scan(2, fields
, -1, NULL
);
839 fields
[0].num_bits
= 32;
840 fields
[0].out_value
= packet
;
842 fields
[1].num_bits
= 1;
843 fields
[1].out_value
= &cmd
;
845 for (word
= 0; word
< 8; word
++)
847 buf_set_u32(packet
, 0, 32, buffer
[word
]);
848 cmd
= parity(*((u32
*)packet
));
849 jtag_add_dr_scan(2, fields
, -1, NULL
);
852 jtag_execute_queue();
857 int xscale_invalidate_ic_line(target_t
*target
, u32 va
)
859 armv4_5_common_t
*armv4_5
= target
->arch_info
;
860 xscale_common_t
*xscale
= armv4_5
->arch_info
;
864 scan_field_t fields
[2];
866 jtag_add_end_state(TAP_RTI
);
867 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
869 /* CMD for invalidate IC line b000, bits [6:4] b000 */
870 buf_set_u32(&cmd
, 0, 6, 0x0);
872 /* virtual address of desired cache line */
873 buf_set_u32(packet
, 0, 27, va
>> 5);
875 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
876 fields
[0].num_bits
= 6;
877 fields
[0].out_value
= &cmd
;
878 fields
[0].out_mask
= NULL
;
879 fields
[0].in_value
= NULL
;
880 fields
[0].in_check_value
= NULL
;
881 fields
[0].in_check_mask
= NULL
;
882 fields
[0].in_handler
= NULL
;
883 fields
[0].in_handler_priv
= NULL
;
885 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
886 fields
[1].num_bits
= 27;
887 fields
[1].out_value
= packet
;
888 fields
[1].out_mask
= NULL
;
889 fields
[1].in_value
= NULL
;
890 fields
[1].in_check_value
= NULL
;
891 fields
[1].in_check_mask
= NULL
;
892 fields
[1].in_handler
= NULL
;
893 fields
[1].in_handler_priv
= NULL
;
895 jtag_add_dr_scan(2, fields
, -1, NULL
);
900 int xscale_update_vectors(target_t
*target
)
902 armv4_5_common_t
*armv4_5
= target
->arch_info
;
903 xscale_common_t
*xscale
= armv4_5
->arch_info
;
906 u32 low_reset_branch
, high_reset_branch
;
908 for (i
= 1; i
< 8; i
++)
910 /* if there's a static vector specified for this exception, override */
911 if (xscale
->static_high_vectors_set
& (1 << i
))
913 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
917 if (target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]) != ERROR_OK
)
919 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
924 for (i
= 1; i
< 8; i
++)
926 if (xscale
->static_low_vectors_set
& (1 << i
))
928 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
932 if (target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]) != ERROR_OK
)
934 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
939 /* calculate branches to debug handler */
940 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
941 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
943 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
944 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
946 /* invalidate and load exception vectors in mini i-cache */
947 xscale_invalidate_ic_line(target
, 0x0);
948 xscale_invalidate_ic_line(target
, 0xffff0000);
950 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
951 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
956 int xscale_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
958 armv4_5_common_t
*armv4_5
= target
->arch_info
;
959 xscale_common_t
*xscale
= armv4_5
->arch_info
;
963 "disabled", "enabled"
966 char *arch_dbg_reason
[] =
968 "", "\n(processor reset)", "\n(trace buffer full)"
971 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
973 ERROR("BUG: called for a non-ARMv4/5 target");
977 snprintf(buf
, buf_size
,
978 "target halted in %s state due to %s, current mode: %s\n"
979 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
980 "MMU: %s, D-Cache: %s, I-Cache: %s"
982 armv4_5_state_strings
[armv4_5
->core_state
],
983 target_debug_reason_strings
[target
->debug_reason
],
984 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
985 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
986 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
987 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
988 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
989 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
990 arch_dbg_reason
[xscale
->arch_debug_reason
]);
995 enum target_state
xscale_poll(target_t
*target
)
998 armv4_5_common_t
*armv4_5
= target
->arch_info
;
999 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1001 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
1003 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
1005 enum target_state previous_state
= target
->state
;
1007 /* there's data to read from the tx register, we entered debug state */
1008 xscale
->handler_running
= 1;
1010 target
->state
= TARGET_HALTED
;
1012 /* process debug entry, fetching current mode regs */
1013 if ((retval
= xscale_debug_entry(target
)) != ERROR_OK
)
1016 /* debug_entry could have overwritten target state (i.e. immediate resume)
1017 * don't signal event handlers in that case
1019 if (target
->state
!= TARGET_HALTED
)
1020 return target
->state
;
1022 /* if target was running, signal that we halted
1023 * otherwise we reentered from debug execution */
1024 if (previous_state
== TARGET_RUNNING
)
1025 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1027 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1029 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1031 ERROR("error while polling TX register");
1036 return target
->state
;
1039 int xscale_debug_entry(target_t
*target
)
1041 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1042 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1044 u32
*buffer
= malloc(4 * 10);
1049 /* clear external dbg break (will be written on next DCSR read) */
1050 xscale
->external_debug_break
= 0;
1051 xscale_read_dcsr(target
);
1053 /* get r0, pc, r1 to r7 and cpsr */
1054 xscale_receive(target
, buffer
, 10);
1056 /* move r0 from buffer to register cache */
1057 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
1058 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1059 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1060 DEBUG("r0: 0x%8.8x", buffer
[0]);
1062 /* move pc from buffer to register cache */
1063 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
1064 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1065 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1066 DEBUG("pc: 0x%8.8x", buffer
[1]);
1068 /* move data from buffer to register cache */
1069 for (i
= 1; i
<= 7; i
++)
1071 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
1072 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
1073 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
1074 DEBUG("r%i: 0x%8.8x", i
, buffer
[i
+ 1]);
1077 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
1078 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1079 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1080 DEBUG("cpsr: 0x%8.8x", buffer
[9]);
1082 armv4_5
->core_mode
= buffer
[9] & 0x1f;
1083 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1085 target
->state
= TARGET_UNKNOWN
;
1086 ERROR("cpsr contains invalid mode value - communication failure");
1087 return ERROR_TARGET_FAILURE
;
1089 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1091 if (buffer
[9] & 0x20)
1092 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1094 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1096 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1097 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1099 xscale_receive(target
, buffer
, 8);
1100 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1101 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1102 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1106 /* r8 to r14, but no spsr */
1107 xscale_receive(target
, buffer
, 7);
1110 /* move data from buffer to register cache */
1111 for (i
= 8; i
<= 14; i
++)
1113 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1114 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1115 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1118 /* examine debug reason */
1119 xscale_read_dcsr(target
);
1120 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1122 /* stored PC (for calculating fixup) */
1123 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1127 case 0x0: /* Processor reset */
1128 target
->debug_reason
= DBG_REASON_DBGRQ
;
1129 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1132 case 0x1: /* Instruction breakpoint hit */
1133 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1134 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1137 case 0x2: /* Data breakpoint hit */
1138 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1139 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1142 case 0x3: /* BKPT instruction executed */
1143 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1144 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1147 case 0x4: /* Ext. debug event */
1148 target
->debug_reason
= DBG_REASON_DBGRQ
;
1149 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1152 case 0x5: /* Vector trap occured */
1153 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1154 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1157 case 0x6: /* Trace buffer full break */
1158 target
->debug_reason
= DBG_REASON_DBGRQ
;
1159 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1162 case 0x7: /* Reserved */
1164 ERROR("Method of Entry is 'Reserved'");
1169 /* apply PC fixup */
1170 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1172 /* on the first debug entry, identify cache type */
1173 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1177 /* read cp15 cache type register */
1178 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1179 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1181 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1184 /* examine MMU and Cache settings */
1185 /* read cp15 control register */
1186 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1187 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1188 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1189 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1190 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1192 /* tracing enabled, read collected trace data */
1193 if (xscale
->trace
.buffer_enabled
)
1195 xscale_read_trace(target
);
1196 xscale
->trace
.buffer_fill
--;
1198 /* resume if we're still collecting trace data */
1199 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1200 && (xscale
->trace
.buffer_fill
> 0))
1202 xscale_resume(target
, 1, 0x0, 1, 0);
1206 xscale
->trace
.buffer_enabled
= 0;
1213 int xscale_halt(target_t
*target
)
1215 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1216 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1218 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1220 if (target
->state
== TARGET_HALTED
)
1222 WARNING("target was already halted");
1223 return ERROR_TARGET_ALREADY_HALTED
;
1225 else if (target
->state
== TARGET_UNKNOWN
)
1227 /* this must not happen for a xscale target */
1228 ERROR("target was in unknown state when halt was requested");
1231 else if (target
->state
== TARGET_RESET
)
1233 DEBUG("target->state == TARGET_RESET");
1237 /* assert external dbg break */
1238 xscale
->external_debug_break
= 1;
1239 xscale_read_dcsr(target
);
1241 target
->debug_reason
= DBG_REASON_DBGRQ
;
1247 int xscale_enable_single_step(struct target_s
*target
, u32 next_pc
)
1249 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1250 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1251 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1253 if (xscale
->ibcr0_used
)
1255 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1259 xscale_unset_breakpoint(target
, ibcr0_bp
);
1263 ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1268 xscale_set_reg_u32(ibcr0
, next_pc
| 0x1);
1273 int xscale_disable_single_step(struct target_s
*target
)
1275 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1276 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1277 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1279 xscale_set_reg_u32(ibcr0
, 0x0);
1284 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1286 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1287 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1288 breakpoint_t
*breakpoint
= target
->breakpoints
;
1297 if (target
->state
!= TARGET_HALTED
)
1299 WARNING("target not halted");
1300 return ERROR_TARGET_NOT_HALTED
;
1303 if (!debug_execution
)
1305 target_free_all_working_areas(target
);
1308 /* update vector tables */
1309 xscale_update_vectors(target
);
1311 /* current = 1: continue on current pc, otherwise continue at <address> */
1313 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1315 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1317 /* if we're at the reset vector, we have to simulate the branch */
1318 if (current_pc
== 0x0)
1320 arm_simulate_step(target
, NULL
);
1321 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1324 /* the front-end may request us not to handle breakpoints */
1325 if (handle_breakpoints
)
1327 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1331 /* there's a breakpoint at the current PC, we have to step over it */
1332 DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1333 xscale_unset_breakpoint(target
, breakpoint
);
1335 /* calculate PC of next instruction */
1336 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1339 target_read_u32(target
, current_pc
, ¤t_opcode
);
1340 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1343 DEBUG("enable single-step");
1344 xscale_enable_single_step(target
, next_pc
);
1346 /* restore banked registers */
1347 xscale_restore_context(target
);
1349 /* send resume request (command 0x30 or 0x31)
1350 * clean the trace buffer if it is to be enabled (0x62) */
1351 if (xscale
->trace
.buffer_enabled
)
1353 xscale_send_u32(target
, 0x62);
1354 xscale_send_u32(target
, 0x31);
1357 xscale_send_u32(target
, 0x30);
1360 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1361 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1363 for (i
= 7; i
>= 0; i
--)
1366 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1367 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1371 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1372 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1374 /* wait for and process debug entry */
1375 xscale_debug_entry(target
);
1377 DEBUG("disable single-step");
1378 xscale_disable_single_step(target
);
1380 DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1381 xscale_set_breakpoint(target
, breakpoint
);
1385 /* enable any pending breakpoints and watchpoints */
1386 xscale_enable_breakpoints(target
);
1387 xscale_enable_watchpoints(target
);
1389 /* restore banked registers */
1390 xscale_restore_context(target
);
1392 /* send resume request (command 0x30 or 0x31)
1393 * clean the trace buffer if it is to be enabled (0x62) */
1394 if (xscale
->trace
.buffer_enabled
)
1396 xscale_send_u32(target
, 0x62);
1397 xscale_send_u32(target
, 0x31);
1400 xscale_send_u32(target
, 0x30);
1403 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1404 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1406 for (i
= 7; i
>= 0; i
--)
1409 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1410 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1414 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1415 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1417 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1419 if (!debug_execution
)
1421 /* registers are now invalid */
1422 armv4_5_invalidate_core_regs(target
);
1423 target
->state
= TARGET_RUNNING
;
1424 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1428 target
->state
= TARGET_DEBUG_RUNNING
;
1429 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1432 DEBUG("target resumed");
1434 xscale
->handler_running
= 1;
1439 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1441 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1442 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1443 breakpoint_t
*breakpoint
= target
->breakpoints
;
1445 u32 current_pc
, next_pc
;
1449 if (target
->state
!= TARGET_HALTED
)
1451 WARNING("target not halted");
1452 return ERROR_TARGET_NOT_HALTED
;
1455 /* current = 1: continue on current pc, otherwise continue at <address> */
1457 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1459 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1461 /* if we're at the reset vector, we have to simulate the step */
1462 if (current_pc
== 0x0)
1464 arm_simulate_step(target
, NULL
);
1465 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1467 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1468 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1473 /* the front-end may request us not to handle breakpoints */
1474 if (handle_breakpoints
)
1475 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1477 xscale_unset_breakpoint(target
, breakpoint
);
1480 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1482 /* calculate PC of next instruction */
1483 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1486 target_read_u32(target
, current_pc
, ¤t_opcode
);
1487 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1490 DEBUG("enable single-step");
1491 xscale_enable_single_step(target
, next_pc
);
1493 /* restore banked registers */
1494 xscale_restore_context(target
);
1496 /* send resume request (command 0x30 or 0x31)
1497 * clean the trace buffer if it is to be enabled (0x62) */
1498 if (xscale
->trace
.buffer_enabled
)
1500 xscale_send_u32(target
, 0x62);
1501 xscale_send_u32(target
, 0x31);
1504 xscale_send_u32(target
, 0x30);
1507 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1508 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1510 for (i
= 7; i
>= 0; i
--)
1513 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1514 DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1518 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1519 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1521 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1523 /* registers are now invalid */
1524 armv4_5_invalidate_core_regs(target
);
1526 /* wait for and process debug entry */
1527 xscale_debug_entry(target
);
1529 DEBUG("disable single-step");
1530 xscale_disable_single_step(target
);
1532 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1536 xscale_set_breakpoint(target
, breakpoint
);
1539 DEBUG("target stepped");
1545 int xscale_assert_reset(target_t
*target
)
1547 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1548 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1550 DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1552 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1553 * end up in T-L-R, which would reset JTAG
1555 jtag_add_end_state(TAP_RTI
);
1556 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
1558 /* set Hold reset, Halt mode and Trap Reset */
1559 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1560 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1561 xscale_write_dcsr(target
, 1, 0);
1563 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1564 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, 0x7f);
1565 jtag_execute_queue();
1568 jtag_add_reset(0, 1);
1570 /* sleep 1ms, to be sure we fulfill any requirements */
1571 jtag_add_sleep(1000);
1572 jtag_execute_queue();
1574 target
->state
= TARGET_RESET
;
1579 int xscale_deassert_reset(target_t
*target
)
1581 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1582 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1584 fileio_t debug_handler
;
1592 breakpoint_t
*breakpoint
= target
->breakpoints
;
1596 xscale
->ibcr_available
= 2;
1597 xscale
->ibcr0_used
= 0;
1598 xscale
->ibcr1_used
= 0;
1600 xscale
->dbr_available
= 2;
1601 xscale
->dbr0_used
= 0;
1602 xscale
->dbr1_used
= 0;
1604 /* mark all hardware breakpoints as unset */
1607 if (breakpoint
->type
== BKPT_HARD
)
1609 breakpoint
->set
= 0;
1611 breakpoint
= breakpoint
->next
;
1614 if (!xscale
->handler_installed
)
1617 jtag_add_reset(0, 0);
1619 /* wait 300ms; 150 and 100ms were not enough */
1620 jtag_add_sleep(3000000);
1622 jtag_add_runtest(2030, TAP_RTI
);
1623 jtag_execute_queue();
1625 /* set Hold reset, Halt mode and Trap Reset */
1626 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1627 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1628 xscale_write_dcsr(target
, 1, 0);
1630 /* Load debug handler */
1631 if (fileio_open(&debug_handler
, PKGLIBDIR
"/xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1633 ERROR("file open error: %s", debug_handler
.error_str
);
1637 if ((binary_size
= debug_handler
.size
) % 4)
1639 ERROR("debug_handler.bin: size not a multiple of 4");
1643 if (binary_size
> 0x800)
1645 ERROR("debug_handler.bin: larger than 2kb");
1649 binary_size
= CEIL(binary_size
, 32) * 32;
1651 address
= xscale
->handler_address
;
1652 while (binary_size
> 0)
1657 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1659 ERROR("reading debug handler failed: %s", debug_handler
.error_str
);
1662 for (i
= 0; i
< buf_cnt
; i
+= 4)
1664 /* convert LE buffer to host-endian u32 */
1665 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1668 for (; buf_cnt
< 32; buf_cnt
+= 4)
1670 cache_line
[buf_cnt
/ 4] = 0xe1a08008;
1673 /* only load addresses other than the reset vectors */
1674 if ((address
% 0x400) != 0x0)
1676 xscale_load_ic(target
, 1, address
, cache_line
);
1680 binary_size
-= buf_cnt
;
1683 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
1684 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
1686 jtag_add_runtest(30, TAP_RTI
);
1688 jtag_add_sleep(100000);
1690 /* set Hold reset, Halt mode and Trap Reset */
1691 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1692 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1693 xscale_write_dcsr(target
, 1, 0);
1695 /* clear Hold reset to let the target run (should enter debug handler) */
1696 xscale_write_dcsr(target
, 0, 1);
1697 target
->state
= TARGET_RUNNING
;
1699 if ((target
->reset_mode
!= RESET_HALT
) && (target
->reset_mode
!= RESET_INIT
))
1701 jtag_add_sleep(10000);
1703 /* we should have entered debug now */
1704 xscale_debug_entry(target
);
1705 target
->state
= TARGET_HALTED
;
1707 /* resume the target */
1708 xscale_resume(target
, 1, 0x0, 1, 0);
1713 jtag_add_reset(0, 0);
1720 int xscale_soft_reset_halt(struct target_s
*target
)
1726 int xscale_prepare_reset_halt(struct target_s
*target
)
1728 /* nothing to be done for reset_halt on XScale targets
1729 * we always halt after a reset to upload the debug handler
1734 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1740 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1746 int xscale_full_context(target_t
*target
)
1748 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1756 if (target
->state
!= TARGET_HALTED
)
1758 WARNING("target not halted");
1759 return ERROR_TARGET_NOT_HALTED
;
1762 buffer
= malloc(4 * 8);
1764 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1765 * we can't enter User mode on an XScale (unpredictable),
1766 * but User shares registers with SYS
1768 for(i
= 1; i
< 7; i
++)
1772 /* check if there are invalid registers in the current mode
1774 for (j
= 0; j
<= 16; j
++)
1776 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1784 /* request banked registers */
1785 xscale_send_u32(target
, 0x0);
1788 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1789 tmp_cpsr
|= 0xc0; /* I/F bits */
1791 /* send CPSR for desired mode */
1792 xscale_send_u32(target
, tmp_cpsr
);
1794 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1795 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1797 xscale_receive(target
, buffer
, 8);
1798 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1799 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1800 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1804 xscale_receive(target
, buffer
, 7);
1807 /* move data from buffer to register cache */
1808 for (j
= 8; j
<= 14; j
++)
1810 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1811 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1812 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1822 int xscale_restore_context(target_t
*target
)
1824 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1830 if (target
->state
!= TARGET_HALTED
)
1832 WARNING("target not halted");
1833 return ERROR_TARGET_NOT_HALTED
;
1836 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1837 * we can't enter User mode on an XScale (unpredictable),
1838 * but User shares registers with SYS
1840 for(i
= 1; i
< 7; i
++)
1844 /* check if there are invalid registers in the current mode
1846 for (j
= 8; j
<= 14; j
++)
1848 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1852 /* if not USR/SYS, check if the SPSR needs to be written */
1853 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1855 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1863 /* send banked registers */
1864 xscale_send_u32(target
, 0x1);
1867 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1868 tmp_cpsr
|= 0xc0; /* I/F bits */
1870 /* send CPSR for desired mode */
1871 xscale_send_u32(target
, tmp_cpsr
);
1873 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1874 for (j
= 8; j
<= 14; j
++)
1876 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1877 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1880 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1882 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1883 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1891 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1893 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1894 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1898 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1900 if (target
->state
!= TARGET_HALTED
)
1902 WARNING("target not halted");
1903 return ERROR_TARGET_NOT_HALTED
;
1906 /* sanitize arguments */
1907 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1908 return ERROR_INVALID_ARGUMENTS
;
1910 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1911 return ERROR_TARGET_UNALIGNED_ACCESS
;
1913 /* send memory read request (command 0x1n, n: access size) */
1914 xscale_send_u32(target
, 0x10 | size
);
1916 /* send base address for read request */
1917 xscale_send_u32(target
, address
);
1919 /* send number of requested data words */
1920 xscale_send_u32(target
, count
);
1922 /* receive data from target (count times 32-bit words in host endianness) */
1923 buf32
= malloc(4 * count
);
1924 xscale_receive(target
, buf32
, count
);
1926 /* extract data from host-endian buffer into byte stream */
1927 for (i
= 0; i
< count
; i
++)
1932 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1936 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1940 *buffer
++ = buf32
[i
] & 0xff;
1943 ERROR("should never get here");
1950 /* examine DCSR, to see if Sticky Abort (SA) got set */
1951 xscale_read_dcsr(target
);
1952 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1955 xscale_send_u32(target
, 0x60);
1957 return ERROR_TARGET_DATA_ABORT
;
1963 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1965 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1966 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1968 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1970 if (target
->state
!= TARGET_HALTED
)
1972 WARNING("target not halted");
1973 return ERROR_TARGET_NOT_HALTED
;
1976 /* sanitize arguments */
1977 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1978 return ERROR_INVALID_ARGUMENTS
;
1980 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1981 return ERROR_TARGET_UNALIGNED_ACCESS
;
1983 /* send memory write request (command 0x2n, n: access size) */
1984 xscale_send_u32(target
, 0x20 | size
);
1986 /* send base address for read request */
1987 xscale_send_u32(target
, address
);
1989 /* send number of requested data words to be written*/
1990 xscale_send_u32(target
, count
);
1992 /* extract data from host-endian buffer into byte stream */
1994 for (i
= 0; i
< count
; i
++)
1999 value
= target_buffer_get_u32(target
, buffer
);
2000 xscale_send_u32(target
, value
);
2004 value
= target_buffer_get_u16(target
, buffer
);
2005 xscale_send_u32(target
, value
);
2010 xscale_send_u32(target
, value
);
2014 ERROR("should never get here");
2019 xscale_send(target
, buffer
, count
, size
);
2021 /* examine DCSR, to see if Sticky Abort (SA) got set */
2022 xscale_read_dcsr(target
);
2023 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2026 xscale_send_u32(target
, 0x60);
2028 return ERROR_TARGET_DATA_ABORT
;
2034 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2036 xscale_write_memory(target
, address
, 4, count
, buffer
);
2041 int xscale_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
2043 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2046 u32
xscale_get_ttb(target_t
*target
)
2048 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2049 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2052 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2053 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2058 void xscale_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2060 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2061 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2064 /* read cp15 control register */
2065 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2066 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2069 cp15_control
&= ~0x1U
;
2074 xscale_send_u32(target
, 0x50);
2075 xscale_send_u32(target
, xscale
->cache_clean_address
);
2077 /* invalidate DCache */
2078 xscale_send_u32(target
, 0x51);
2080 cp15_control
&= ~0x4U
;
2085 /* invalidate ICache */
2086 xscale_send_u32(target
, 0x52);
2087 cp15_control
&= ~0x1000U
;
2090 /* write new cp15 control register */
2091 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2093 /* execute cpwait to ensure outstanding operations complete */
2094 xscale_send_u32(target
, 0x53);
2097 void xscale_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2099 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2100 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2103 /* read cp15 control register */
2104 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2105 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2108 cp15_control
|= 0x1U
;
2111 cp15_control
|= 0x4U
;
2114 cp15_control
|= 0x1000U
;
2116 /* write new cp15 control register */
2117 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2119 /* execute cpwait to ensure outstanding operations complete */
2120 xscale_send_u32(target
, 0x53);
2123 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2125 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2126 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2128 if (target
->state
!= TARGET_HALTED
)
2130 WARNING("target not halted");
2131 return ERROR_TARGET_NOT_HALTED
;
2134 if (xscale
->force_hw_bkpts
)
2135 breakpoint
->type
= BKPT_HARD
;
2137 if (breakpoint
->set
)
2139 WARNING("breakpoint already set");
2143 if (breakpoint
->type
== BKPT_HARD
)
2145 u32 value
= breakpoint
->address
| 1;
2146 if (!xscale
->ibcr0_used
)
2148 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2149 xscale
->ibcr0_used
= 1;
2150 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2152 else if (!xscale
->ibcr1_used
)
2154 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2155 xscale
->ibcr1_used
= 1;
2156 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2160 ERROR("BUG: no hardware comparator available");
2164 else if (breakpoint
->type
== BKPT_SOFT
)
2166 if (breakpoint
->length
== 4)
2168 /* keep the original instruction in target endianness */
2169 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2170 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2171 target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
);
2175 /* keep the original instruction in target endianness */
2176 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2177 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2178 target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
);
2180 breakpoint
->set
= 1;
2187 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2189 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2190 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2192 if (target
->state
!= TARGET_HALTED
)
2194 WARNING("target not halted");
2195 return ERROR_TARGET_NOT_HALTED
;
2198 if (xscale
->force_hw_bkpts
)
2200 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
2201 breakpoint
->type
= BKPT_HARD
;
2204 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2206 INFO("no breakpoint unit available for hardware breakpoint");
2207 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2211 xscale
->ibcr_available
--;
2214 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2216 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2217 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2223 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2225 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2226 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2228 if (target
->state
!= TARGET_HALTED
)
2230 WARNING("target not halted");
2231 return ERROR_TARGET_NOT_HALTED
;
2234 if (!breakpoint
->set
)
2236 WARNING("breakpoint not set");
2240 if (breakpoint
->type
== BKPT_HARD
)
2242 if (breakpoint
->set
== 1)
2244 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2245 xscale
->ibcr0_used
= 0;
2247 else if (breakpoint
->set
== 2)
2249 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2250 xscale
->ibcr1_used
= 0;
2252 breakpoint
->set
= 0;
2256 /* restore original instruction (kept in target endianness) */
2257 if (breakpoint
->length
== 4)
2259 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2263 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2265 breakpoint
->set
= 0;
2271 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2273 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2274 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2276 if (target
->state
!= TARGET_HALTED
)
2278 WARNING("target not halted");
2279 return ERROR_TARGET_NOT_HALTED
;
2282 if (breakpoint
->set
)
2284 xscale_unset_breakpoint(target
, breakpoint
);
2287 if (breakpoint
->type
== BKPT_HARD
)
2288 xscale
->ibcr_available
++;
2293 int xscale_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2295 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2296 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2298 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2299 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2301 if (target
->state
!= TARGET_HALTED
)
2303 WARNING("target not halted");
2304 return ERROR_TARGET_NOT_HALTED
;
2307 xscale_get_reg(dbcon
);
2309 switch (watchpoint
->rw
)
2321 ERROR("BUG: watchpoint->rw neither read, write nor access");
2324 if (!xscale
->dbr0_used
)
2326 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2327 dbcon_value
|= enable
;
2328 xscale_set_reg_u32(dbcon
, dbcon_value
);
2329 watchpoint
->set
= 1;
2330 xscale
->dbr0_used
= 1;
2332 else if (!xscale
->dbr1_used
)
2334 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2335 dbcon_value
|= enable
<< 2;
2336 xscale_set_reg_u32(dbcon
, dbcon_value
);
2337 watchpoint
->set
= 2;
2338 xscale
->dbr1_used
= 1;
2342 ERROR("BUG: no hardware comparator available");
2349 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2351 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2352 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2354 if (target
->state
!= TARGET_HALTED
)
2356 WARNING("target not halted");
2357 return ERROR_TARGET_NOT_HALTED
;
2360 if (xscale
->dbr_available
< 1)
2362 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2365 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2367 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2370 xscale
->dbr_available
--;
2375 int xscale_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2377 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2378 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2379 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2380 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2382 if (target
->state
!= TARGET_HALTED
)
2384 WARNING("target not halted");
2385 return ERROR_TARGET_NOT_HALTED
;
2388 if (!watchpoint
->set
)
2390 WARNING("breakpoint not set");
2394 if (watchpoint
->set
== 1)
2396 dbcon_value
&= ~0x3;
2397 xscale_set_reg_u32(dbcon
, dbcon_value
);
2398 xscale
->dbr0_used
= 0;
2400 else if (watchpoint
->set
== 2)
2402 dbcon_value
&= ~0xc;
2403 xscale_set_reg_u32(dbcon
, dbcon_value
);
2404 xscale
->dbr1_used
= 0;
2406 watchpoint
->set
= 0;
2411 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2413 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2414 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2416 if (target
->state
!= TARGET_HALTED
)
2418 WARNING("target not halted");
2419 return ERROR_TARGET_NOT_HALTED
;
2422 if (watchpoint
->set
)
2424 xscale_unset_watchpoint(target
, watchpoint
);
2427 xscale
->dbr_available
++;
2432 void xscale_enable_watchpoints(struct target_s
*target
)
2434 watchpoint_t
*watchpoint
= target
->watchpoints
;
2438 if (watchpoint
->set
== 0)
2439 xscale_set_watchpoint(target
, watchpoint
);
2440 watchpoint
= watchpoint
->next
;
2444 void xscale_enable_breakpoints(struct target_s
*target
)
2446 breakpoint_t
*breakpoint
= target
->breakpoints
;
2448 /* set any pending breakpoints */
2451 if (breakpoint
->set
== 0)
2452 xscale_set_breakpoint(target
, breakpoint
);
2453 breakpoint
= breakpoint
->next
;
2457 int xscale_get_reg(reg_t
*reg
)
2459 xscale_reg_t
*arch_info
= reg
->arch_info
;
2460 target_t
*target
= arch_info
->target
;
2461 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2462 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2464 /* DCSR, TX and RX are accessible via JTAG */
2465 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2467 return xscale_read_dcsr(arch_info
->target
);
2469 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2471 /* 1 = consume register content */
2472 return xscale_read_tx(arch_info
->target
, 1);
2474 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2476 /* can't read from RX register (host -> debug handler) */
2479 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2481 /* can't (explicitly) read from TXRXCTRL register */
2484 else /* Other DBG registers have to be transfered by the debug handler */
2486 /* send CP read request (command 0x40) */
2487 xscale_send_u32(target
, 0x40);
2489 /* send CP register number */
2490 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2492 /* read register value */
2493 xscale_read_tx(target
, 1);
2494 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2503 int xscale_set_reg(reg_t
*reg
, u8
* buf
)
2505 xscale_reg_t
*arch_info
= reg
->arch_info
;
2506 target_t
*target
= arch_info
->target
;
2507 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2508 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2509 u32 value
= buf_get_u32(buf
, 0, 32);
2511 /* DCSR, TX and RX are accessible via JTAG */
2512 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2514 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2515 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2517 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2519 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2520 return xscale_write_rx(arch_info
->target
);
2522 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2524 /* can't write to TX register (debug-handler -> host) */
2527 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2529 /* can't (explicitly) write to TXRXCTRL register */
2532 else /* Other DBG registers have to be transfered by the debug handler */
2534 /* send CP write request (command 0x41) */
2535 xscale_send_u32(target
, 0x41);
2537 /* send CP register number */
2538 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2540 /* send CP register value */
2541 xscale_send_u32(target
, value
);
2542 buf_set_u32(reg
->value
, 0, 32, value
);
2548 /* convenience wrapper to access XScale specific registers */
2549 int xscale_set_reg_u32(reg_t
*reg
, u32 value
)
2553 buf_set_u32(buf
, 0, 32, value
);
2555 return xscale_set_reg(reg
, buf
);
2558 int xscale_write_dcsr_sw(target_t
*target
, u32 value
)
2560 /* get pointers to arch-specific information */
2561 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2562 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2563 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2564 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2566 /* send CP write request (command 0x41) */
2567 xscale_send_u32(target
, 0x41);
2569 /* send CP register number */
2570 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2572 /* send CP register value */
2573 xscale_send_u32(target
, value
);
2574 buf_set_u32(dcsr
->value
, 0, 32, value
);
2579 int xscale_read_trace(target_t
*target
)
2581 /* get pointers to arch-specific information */
2582 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2583 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2584 xscale_trace_data_t
**trace_data_p
;
2586 /* 258 words from debug handler
2587 * 256 trace buffer entries
2588 * 2 checkpoint addresses
2590 u32 trace_buffer
[258];
2591 int is_address
[256];
2594 if (target
->state
!= TARGET_HALTED
)
2596 WARNING("target must be stopped to read trace data");
2597 return ERROR_TARGET_NOT_HALTED
;
2600 /* send read trace buffer command (command 0x61) */
2601 xscale_send_u32(target
, 0x61);
2603 /* receive trace buffer content */
2604 xscale_receive(target
, trace_buffer
, 258);
2606 /* parse buffer backwards to identify address entries */
2607 for (i
= 255; i
>= 0; i
--)
2610 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2611 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2614 is_address
[--i
] = 1;
2616 is_address
[--i
] = 1;
2618 is_address
[--i
] = 1;
2620 is_address
[--i
] = 1;
2625 /* search first non-zero entry */
2626 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2631 DEBUG("no trace data collected");
2632 return ERROR_XSCALE_NO_TRACE_DATA
;
2635 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2638 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2639 (*trace_data_p
)->next
= NULL
;
2640 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2641 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2642 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2643 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2644 (*trace_data_p
)->depth
= 256 - j
;
2646 for (i
= j
; i
< 256; i
++)
2648 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2650 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2652 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2658 int xscale_read_instruction(target_t
*target
, arm_instruction_t
*instruction
)
2660 /* get pointers to arch-specific information */
2661 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2662 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2669 if (!xscale
->trace
.image
)
2670 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2672 /* search for the section the current instruction belongs to */
2673 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2675 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2676 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2685 /* current instruction couldn't be found in the image */
2686 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2689 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2692 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2693 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2694 4, buf
, &size_read
)) != ERROR_OK
)
2696 ERROR("error while reading instruction: %i", retval
);
2697 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2699 opcode
= target_buffer_get_u32(target
, buf
);
2700 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2702 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2705 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2706 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2707 2, buf
, &size_read
)) != ERROR_OK
)
2709 ERROR("error while reading instruction: %i", retval
);
2710 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2712 opcode
= target_buffer_get_u16(target
, buf
);
2713 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2717 ERROR("BUG: unknown core state encountered");
2724 int xscale_branch_address(xscale_trace_data_t
*trace_data
, int i
, u32
*target
)
2726 /* if there are less than four entries prior to the indirect branch message
2727 * we can't extract the address */
2733 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2734 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2739 int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2741 /* get pointers to arch-specific information */
2742 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2743 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2746 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2755 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2760 for (i
= 0; i
< trace_data
->depth
; i
++)
2766 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2769 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2771 case 0: /* Exceptions */
2779 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2781 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2782 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2784 case 8: /* Direct Branch */
2787 case 9: /* Indirect Branch */
2789 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2794 case 13: /* Checkpointed Indirect Branch */
2795 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2798 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2799 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2800 WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2802 /* explicit fall-through */
2803 case 12: /* Checkpointed Direct Branch */
2808 next_pc
= trace_data
->chkpt0
;
2811 else if (chkpt
== 1)
2814 next_pc
= trace_data
->chkpt0
;
2819 WARNING("more than two checkpointed branches encountered");
2822 case 15: /* Roll-over */
2825 default: /* Reserved */
2826 command_print(cmd_ctx
, "--- reserved trace message ---");
2827 ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2831 if (xscale
->trace
.pc_ok
)
2833 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2834 arm_instruction_t instruction
;
2836 if ((exception
== 6) || (exception
== 7))
2838 /* IRQ or FIQ exception, no instruction executed */
2842 while (executed
-- >= 0)
2844 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2846 /* can't continue tracing with no image available */
2847 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2851 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2853 /* TODO: handle incomplete images */
2857 /* a precise abort on a load to the PC is included in the incremental
2858 * word count, other instructions causing data aborts are not included
2860 if ((executed
== 0) && (exception
== 4)
2861 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2863 if ((instruction
.type
== ARM_LDM
)
2864 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2868 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2869 && (instruction
.info
.load_store
.Rd
!= 15))
2875 /* only the last instruction executed
2876 * (the one that caused the control flow change)
2877 * could be a taken branch
2879 if (((executed
== -1) && (branch
== 1)) &&
2880 (((instruction
.type
== ARM_B
) ||
2881 (instruction
.type
== ARM_BL
) ||
2882 (instruction
.type
== ARM_BLX
)) &&
2883 (instruction
.info
.b_bl_bx_blx
.target_address
!= -1)))
2885 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2889 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2891 command_print(cmd_ctx
, "%s", instruction
.text
);
2899 xscale
->trace
.current_pc
= next_pc
;
2900 xscale
->trace
.pc_ok
= 1;
2904 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2906 arm_instruction_t instruction
;
2907 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2909 /* can't continue tracing with no image available */
2910 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2914 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2916 /* TODO: handle incomplete images */
2919 command_print(cmd_ctx
, "%s", instruction
.text
);
2922 trace_data
= trace_data
->next
;
2928 void xscale_build_reg_cache(target_t
*target
)
2930 /* get pointers to arch-specific information */
2931 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2932 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2934 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2935 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2937 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2939 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2940 armv4_5
->core_cache
= (*cache_p
);
2942 /* register a register arch-type for XScale dbg registers only once */
2943 if (xscale_reg_arch_type
== -1)
2944 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
2946 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
2947 cache_p
= &(*cache_p
)->next
;
2949 /* fill in values for the xscale reg cache */
2950 (*cache_p
)->name
= "XScale registers";
2951 (*cache_p
)->next
= NULL
;
2952 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
2953 (*cache_p
)->num_regs
= num_regs
;
2955 for (i
= 0; i
< num_regs
; i
++)
2957 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2958 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2959 (*cache_p
)->reg_list
[i
].dirty
= 0;
2960 (*cache_p
)->reg_list
[i
].valid
= 0;
2961 (*cache_p
)->reg_list
[i
].size
= 32;
2962 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
2963 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
2964 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2965 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
2966 arch_info
[i
] = xscale_reg_arch_info
[i
];
2967 arch_info
[i
].target
= target
;
2970 xscale
->reg_cache
= (*cache_p
);
2973 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
2975 if (startup_mode
!= DAEMON_RESET
)
2977 ERROR("XScale target requires a reset");
2978 ERROR("Reset target to enable debug");
2981 /* assert TRST once during startup */
2982 jtag_add_reset(1, 0);
2983 jtag_add_sleep(5000);
2984 jtag_add_reset(0, 0);
2985 jtag_execute_queue();
2996 int xscale_init_arch_info(target_t
*target
, xscale_common_t
*xscale
, int chain_pos
, char *variant
)
2998 armv4_5_common_t
*armv4_5
;
2999 u32 high_reset_branch
, low_reset_branch
;
3002 armv4_5
= &xscale
->armv4_5_common
;
3004 /* store architecture specfic data (none so far) */
3005 xscale
->arch_info
= NULL
;
3006 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
3008 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3009 xscale
->variant
= strdup(variant
);
3011 /* prepare JTAG information for the new target */
3012 xscale
->jtag_info
.chain_pos
= chain_pos
;
3013 jtag_register_event_callback(xscale_jtag_callback
, target
);
3015 xscale
->jtag_info
.dbgrx
= 0x02;
3016 xscale
->jtag_info
.dbgtx
= 0x10;
3017 xscale
->jtag_info
.dcsr
= 0x09;
3018 xscale
->jtag_info
.ldic
= 0x07;
3020 if ((strcmp(xscale
->variant
, "pxa250") == 0) ||
3021 (strcmp(xscale
->variant
, "pxa255") == 0) ||
3022 (strcmp(xscale
->variant
, "pxa26x") == 0))
3024 xscale
->jtag_info
.ir_length
= 5;
3026 else if ((strcmp(xscale
->variant
, "pxa27x") == 0) ||
3027 (strcmp(xscale
->variant
, "ixp42x") == 0) ||
3028 (strcmp(xscale
->variant
, "ixp45x") == 0) ||
3029 (strcmp(xscale
->variant
, "ixp46x") == 0))
3031 xscale
->jtag_info
.ir_length
= 7;
3034 /* the debug handler isn't installed (and thus not running) at this time */
3035 xscale
->handler_installed
= 0;
3036 xscale
->handler_running
= 0;
3037 xscale
->handler_address
= 0xfe000800;
3039 /* clear the vectors we keep locally for reference */
3040 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
3041 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
3043 /* no user-specified vectors have been configured yet */
3044 xscale
->static_low_vectors_set
= 0x0;
3045 xscale
->static_high_vectors_set
= 0x0;
3047 /* calculate branches to debug handler */
3048 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
3049 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3051 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3052 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3054 for (i
= 1; i
<= 7; i
++)
3056 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3057 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3060 /* 64kB aligned region used for DCache cleaning */
3061 xscale
->cache_clean_address
= 0xfffe0000;
3063 xscale
->hold_rst
= 0;
3064 xscale
->external_debug_break
= 0;
3066 xscale
->force_hw_bkpts
= 1;
3068 xscale
->ibcr_available
= 2;
3069 xscale
->ibcr0_used
= 0;
3070 xscale
->ibcr1_used
= 0;
3072 xscale
->dbr_available
= 2;
3073 xscale
->dbr0_used
= 0;
3074 xscale
->dbr1_used
= 0;
3076 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3077 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3079 xscale
->vector_catch
= 0x1;
3081 xscale
->trace
.capture_status
= TRACE_IDLE
;
3082 xscale
->trace
.data
= NULL
;
3083 xscale
->trace
.image
= NULL
;
3084 xscale
->trace
.buffer_enabled
= 0;
3085 xscale
->trace
.buffer_fill
= 0;
3087 /* prepare ARMv4/5 specific information */
3088 armv4_5
->arch_info
= xscale
;
3089 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3090 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3091 armv4_5
->full_context
= xscale_full_context
;
3093 armv4_5_init_arch_info(target
, armv4_5
);
3095 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3096 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3097 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3098 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3099 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3100 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3101 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3102 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3107 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3108 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
3111 char *variant
= NULL
;
3112 xscale_common_t
*xscale
= malloc(sizeof(xscale_common_t
));
3116 ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
3120 chain_pos
= strtoul(args
[3], NULL
, 0);
3124 xscale_init_arch_info(target
, xscale
, chain_pos
, variant
);
3125 xscale_build_reg_cache(target
);
3130 int xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3132 target_t
*target
= NULL
;
3133 armv4_5_common_t
*armv4_5
;
3134 xscale_common_t
*xscale
;
3136 u32 handler_address
;
3140 ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3144 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3146 ERROR("no target '%s' configured", args
[0]);
3150 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3152 command_print(cmd_ctx
, "target isn't an ARM920t target");
3156 handler_address
= strtoul(args
[1], NULL
, 0);
3158 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3159 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3161 xscale
->handler_address
= handler_address
;
3165 ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3171 int xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3173 target_t
*target
= NULL
;
3174 armv4_5_common_t
*armv4_5
;
3175 xscale_common_t
*xscale
;
3177 u32 cache_clean_address
;
3181 ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3185 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3187 ERROR("no target '%s' configured", args
[0]);
3191 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3193 command_print(cmd_ctx
, "target isn't an XScale target");
3197 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3199 if (cache_clean_address
& 0xffff)
3201 ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3205 xscale
->cache_clean_address
= cache_clean_address
;
3211 int xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3213 target_t
*target
= get_current_target(cmd_ctx
);
3214 armv4_5_common_t
*armv4_5
;
3215 xscale_common_t
*xscale
;
3217 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3219 command_print(cmd_ctx
, "target isn't an XScale target");
3223 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3226 int xscale_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3228 target_t
*target
= get_current_target(cmd_ctx
);
3229 armv4_5_common_t
*armv4_5
;
3230 xscale_common_t
*xscale
;
3232 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3234 command_print(cmd_ctx
, "target isn't an XScale target");
3238 if (target
->state
!= TARGET_HALTED
)
3240 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3244 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &xscale
->armv4_5_mmu
);
3247 int xscale_handle_mmu_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3249 target_t
*target
= get_current_target(cmd_ctx
);
3250 armv4_5_common_t
*armv4_5
;
3251 xscale_common_t
*xscale
;
3253 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3255 command_print(cmd_ctx
, "target isn't an XScale target");
3259 if (target
->state
!= TARGET_HALTED
)
3261 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3267 if (strcmp("enable", args
[0]) == 0)
3269 xscale_enable_mmu_caches(target
, 1, 0, 0);
3270 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3272 else if (strcmp("disable", args
[0]) == 0)
3274 xscale_disable_mmu_caches(target
, 1, 0, 0);
3275 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3279 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3284 int xscale_handle_idcache_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3286 target_t
*target
= get_current_target(cmd_ctx
);
3287 armv4_5_common_t
*armv4_5
;
3288 xscale_common_t
*xscale
;
3289 int icache
= 0, dcache
= 0;
3291 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3293 command_print(cmd_ctx
, "target isn't an XScale target");
3297 if (target
->state
!= TARGET_HALTED
)
3299 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3303 if (strcmp(cmd
, "icache") == 0)
3305 else if (strcmp(cmd
, "dcache") == 0)
3310 if (strcmp("enable", args
[0]) == 0)
3312 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3315 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3317 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3319 else if (strcmp("disable", args
[0]) == 0)
3321 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3324 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3326 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3331 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3334 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3339 int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3341 target_t
*target
= get_current_target(cmd_ctx
);
3342 armv4_5_common_t
*armv4_5
;
3343 xscale_common_t
*xscale
;
3345 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3347 command_print(cmd_ctx
, "target isn't an XScale target");
3353 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3357 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3358 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3359 xscale_write_dcsr(target
, -1, -1);
3362 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3367 int xscale_handle_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3369 target_t
*target
= get_current_target(cmd_ctx
);
3370 armv4_5_common_t
*armv4_5
;
3371 xscale_common_t
*xscale
;
3373 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3375 command_print(cmd_ctx
, "target isn't an XScale target");
3379 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3381 xscale
->force_hw_bkpts
= 1;
3383 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3385 xscale
->force_hw_bkpts
= 0;
3389 command_print(cmd_ctx
, "usage: xscale force_hw_bkpts <enable|disable>");
3392 command_print(cmd_ctx
, "force hardware breakpoints %s", (xscale
->force_hw_bkpts
) ? "enabled" : "disabled");
3397 int xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3399 target_t
*target
= get_current_target(cmd_ctx
);
3400 armv4_5_common_t
*armv4_5
;
3401 xscale_common_t
*xscale
;
3404 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3406 command_print(cmd_ctx
, "target isn't an XScale target");
3410 if (target
->state
!= TARGET_HALTED
)
3412 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3416 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3418 xscale_trace_data_t
*td
, *next_td
;
3419 xscale
->trace
.buffer_enabled
= 1;
3421 /* free old trace data */
3422 td
= xscale
->trace
.data
;
3432 xscale
->trace
.data
= NULL
;
3434 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3436 xscale
->trace
.buffer_enabled
= 0;
3439 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3442 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3444 xscale
->trace
.buffer_fill
= 1;
3446 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3448 xscale
->trace
.buffer_fill
= -1;
3451 if (xscale
->trace
.buffer_enabled
)
3453 /* if we enable the trace buffer in fill-once
3454 * mode we know the address of the first instruction */
3455 xscale
->trace
.pc_ok
= 1;
3456 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3460 /* otherwise the address is unknown, and we have no known good PC */
3461 xscale
->trace
.pc_ok
= 0;
3464 command_print(cmd_ctx
, "trace buffer %s (%s)",
3465 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3466 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3468 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3469 if (xscale
->trace
.buffer_fill
>= 0)
3470 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3472 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3477 int xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3480 armv4_5_common_t
*armv4_5
;
3481 xscale_common_t
*xscale
;
3485 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3489 target
= get_current_target(cmd_ctx
);
3491 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3493 command_print(cmd_ctx
, "target isn't an XScale target");
3497 if (xscale
->trace
.image
)
3499 image_close(xscale
->trace
.image
);
3500 free(xscale
->trace
.image
);
3501 command_print(cmd_ctx
, "previously loaded image found and closed");
3504 xscale
->trace
.image
= malloc(sizeof(image_t
));
3505 xscale
->trace
.image
->base_address_set
= 0;
3506 xscale
->trace
.image
->start_address_set
= 0;
3508 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3511 xscale
->trace
.image
->base_address_set
= 1;
3512 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3516 xscale
->trace
.image
->base_address_set
= 0;
3519 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3521 command_print(cmd_ctx
, "image opening error: %s", xscale
->trace
.image
->error_str
);
3522 free(xscale
->trace
.image
);
3523 xscale
->trace
.image
= NULL
;
3530 int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3532 target_t
*target
= get_current_target(cmd_ctx
);
3533 armv4_5_common_t
*armv4_5
;
3534 xscale_common_t
*xscale
;
3535 xscale_trace_data_t
*trace_data
;
3538 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3540 command_print(cmd_ctx
, "target isn't an XScale target");
3544 if (target
->state
!= TARGET_HALTED
)
3546 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3552 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3556 trace_data
= xscale
->trace
.data
;
3560 command_print(cmd_ctx
, "no trace data collected");
3564 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3566 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
3574 fileio_write_u32(&file
, trace_data
->chkpt0
);
3575 fileio_write_u32(&file
, trace_data
->chkpt1
);
3576 fileio_write_u32(&file
, trace_data
->last_instruction
);
3577 fileio_write_u32(&file
, trace_data
->depth
);
3579 for (i
= 0; i
< trace_data
->depth
; i
++)
3580 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3582 trace_data
= trace_data
->next
;
3585 fileio_close(&file
);
3590 int xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3592 target_t
*target
= get_current_target(cmd_ctx
);
3593 armv4_5_common_t
*armv4_5
;
3594 xscale_common_t
*xscale
;
3596 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3598 command_print(cmd_ctx
, "target isn't an XScale target");
3602 xscale_analyze_trace(target
, cmd_ctx
);
3607 int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3609 command_t
*xscale_cmd
;
3611 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3613 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_CONFIG
, NULL
);
3614 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3616 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3617 register_command(cmd_ctx
, xscale_cmd
, "virt2phys", xscale_handle_virt2phys_command
, COMMAND_EXEC
, NULL
);
3618 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3619 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3620 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3622 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_idcache_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3624 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable|disable> ['fill' [n]|'wrap']");
3626 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3627 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3628 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3629 COMMAND_EXEC
, "load image from <file> [base address]");
3631 armv4_5_register_commands(cmd_ctx
);
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