1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
31 #include "breakpoints.h"
33 #include "target_type.h"
35 #include "arm_simulator.h"
36 #include "arm_disassembler.h"
37 #include <helper/time_support.h>
40 #include "arm_opcodes.h"
44 * Important XScale documents available as of October 2009 include:
46 * Intel XScale® Core Developer’s Manual, January 2004
47 * Order Number: 273473-002
48 * This has a chapter detailing debug facilities, and punts some
49 * details to chip-specific microarchitecture documents.
51 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
52 * Document Number: 273539-005
53 * Less detailed than the developer's manual, but summarizes those
54 * missing details (for most XScales) and gives LOTS of notes about
55 * debugger/handler interaction issues. Presents a simpler reset
56 * and load-handler sequence than the arch doc. (Note, OpenOCD
57 * doesn't currently support "Hot-Debug" as defined there.)
59 * Chip-specific microarchitecture documents may also be useful.
62 /* forward declarations */
63 static int xscale_resume(struct target
*, int current
,
64 uint32_t address
, int handle_breakpoints
, int debug_execution
);
65 static int xscale_debug_entry(struct target
*);
66 static int xscale_restore_banked(struct target
*);
67 static int xscale_get_reg(struct reg
*reg
);
68 static int xscale_set_reg(struct reg
*reg
, uint8_t *buf
);
69 static int xscale_set_breakpoint(struct target
*, struct breakpoint
*);
70 static int xscale_set_watchpoint(struct target
*, struct watchpoint
*);
71 static int xscale_unset_breakpoint(struct target
*, struct breakpoint
*);
72 static int xscale_read_trace(struct target
*);
74 /* This XScale "debug handler" is loaded into the processor's
75 * mini-ICache, which is 2K of code writable only via JTAG.
77 static const uint8_t xscale_debug_handler
[] = {
78 #include "xscale_debug.inc"
81 static const char *const xscale_reg_list
[] = {
82 "XSCALE_MAINID", /* 0 */
92 "XSCALE_IBCR0", /* 10 */
102 "XSCALE_RX", /* 20 */
106 static const struct xscale_reg xscale_reg_arch_info
[] = {
107 {XSCALE_MAINID
, NULL
},
108 {XSCALE_CACHETYPE
, NULL
},
110 {XSCALE_AUXCTRL
, NULL
},
116 {XSCALE_CPACCESS
, NULL
},
117 {XSCALE_IBCR0
, NULL
},
118 {XSCALE_IBCR1
, NULL
},
121 {XSCALE_DBCON
, NULL
},
122 {XSCALE_TBREG
, NULL
},
123 {XSCALE_CHKPT0
, NULL
},
124 {XSCALE_CHKPT1
, NULL
},
125 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
126 {-1, NULL
}, /* TX accessed via JTAG */
127 {-1, NULL
}, /* RX accessed via JTAG */
128 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
131 /* convenience wrapper to access XScale specific registers */
132 static int xscale_set_reg_u32(struct reg
*reg
, uint32_t value
)
136 buf_set_u32(buf
, 0, 32, value
);
138 return xscale_set_reg(reg
, buf
);
141 static const char xscale_not
[] = "target is not an XScale";
143 static int xscale_verify_pointer(struct command_context
*cmd_ctx
,
144 struct xscale_common
*xscale
)
146 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
147 command_print(cmd_ctx
, xscale_not
);
148 return ERROR_TARGET_INVALID
;
153 static int xscale_jtag_set_instr(struct jtag_tap
*tap
, uint32_t new_instr
, tap_state_t end_state
)
157 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
) {
158 struct scan_field field
;
161 memset(&field
, 0, sizeof field
);
162 field
.num_bits
= tap
->ir_length
;
163 field
.out_value
= scratch
;
164 buf_set_u32(scratch
, 0, field
.num_bits
, new_instr
);
166 jtag_add_ir_scan(tap
, &field
, end_state
);
172 static int xscale_read_dcsr(struct target
*target
)
174 struct xscale_common
*xscale
= target_to_xscale(target
);
176 struct scan_field fields
[3];
177 uint8_t field0
= 0x0;
178 uint8_t field0_check_value
= 0x2;
179 uint8_t field0_check_mask
= 0x7;
180 uint8_t field2
= 0x0;
181 uint8_t field2_check_value
= 0x0;
182 uint8_t field2_check_mask
= 0x1;
184 xscale_jtag_set_instr(target
->tap
,
185 XSCALE_SELDCSR
<< xscale
->xscale_variant
,
188 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
189 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
191 memset(&fields
, 0, sizeof fields
);
193 fields
[0].num_bits
= 3;
194 fields
[0].out_value
= &field0
;
196 fields
[0].in_value
= &tmp
;
198 fields
[1].num_bits
= 32;
199 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
201 fields
[2].num_bits
= 1;
202 fields
[2].out_value
= &field2
;
204 fields
[2].in_value
= &tmp2
;
206 jtag_add_dr_scan(target
->tap
, 3, fields
, TAP_DRPAUSE
);
208 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
209 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
211 retval
= jtag_execute_queue();
212 if (retval
!= ERROR_OK
) {
213 LOG_ERROR("JTAG error while reading DCSR");
217 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
218 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
220 /* write the register with the value we just read
221 * on this second pass, only the first bit of field0 is guaranteed to be 0)
223 field0_check_mask
= 0x1;
224 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
225 fields
[1].in_value
= NULL
;
227 jtag_add_dr_scan(target
->tap
, 3, fields
, TAP_DRPAUSE
);
229 /* DANGER!!! this must be here. It will make sure that the arguments
230 * to jtag_set_check_value() does not go out of scope! */
231 return jtag_execute_queue();
235 static void xscale_getbuf(jtag_callback_data_t arg
)
237 uint8_t *in
= (uint8_t *)arg
;
238 *((uint32_t *)arg
) = buf_get_u32(in
, 0, 32);
241 static int xscale_receive(struct target
*target
, uint32_t *buffer
, int num_words
)
244 return ERROR_COMMAND_SYNTAX_ERROR
;
246 struct xscale_common
*xscale
= target_to_xscale(target
);
247 int retval
= ERROR_OK
;
249 struct scan_field fields
[3];
250 uint8_t *field0
= malloc(num_words
* 1);
251 uint8_t field0_check_value
= 0x2;
252 uint8_t field0_check_mask
= 0x6;
253 uint32_t *field1
= malloc(num_words
* 4);
254 uint8_t field2_check_value
= 0x0;
255 uint8_t field2_check_mask
= 0x1;
257 int words_scheduled
= 0;
260 path
[0] = TAP_DRSELECT
;
261 path
[1] = TAP_DRCAPTURE
;
262 path
[2] = TAP_DRSHIFT
;
264 memset(&fields
, 0, sizeof fields
);
266 fields
[0].num_bits
= 3;
268 fields
[0].in_value
= &tmp
;
269 fields
[0].check_value
= &field0_check_value
;
270 fields
[0].check_mask
= &field0_check_mask
;
272 fields
[1].num_bits
= 32;
274 fields
[2].num_bits
= 1;
276 fields
[2].in_value
= &tmp2
;
277 fields
[2].check_value
= &field2_check_value
;
278 fields
[2].check_mask
= &field2_check_mask
;
280 xscale_jtag_set_instr(target
->tap
,
281 XSCALE_DBGTX
<< xscale
->xscale_variant
,
283 jtag_add_runtest(1, TAP_IDLE
); /* ensures that we're in the TAP_IDLE state as the above
286 /* repeat until all words have been collected */
288 while (words_done
< num_words
) {
291 for (i
= words_done
; i
< num_words
; i
++) {
292 fields
[0].in_value
= &field0
[i
];
294 jtag_add_pathmove(3, path
);
296 fields
[1].in_value
= (uint8_t *)(field1
+ i
);
298 jtag_add_dr_scan_check(target
->tap
, 3, fields
, TAP_IDLE
);
300 jtag_add_callback(xscale_getbuf
, (jtag_callback_data_t
)(field1
+ i
));
305 retval
= jtag_execute_queue();
306 if (retval
!= ERROR_OK
) {
307 LOG_ERROR("JTAG error while receiving data from debug handler");
311 /* examine results */
312 for (i
= words_done
; i
< num_words
; i
++) {
313 if (!(field0
[i
] & 1)) {
314 /* move backwards if necessary */
316 for (j
= i
; j
< num_words
- 1; j
++) {
317 field0
[j
] = field0
[j
+ 1];
318 field1
[j
] = field1
[j
+ 1];
323 if (words_scheduled
== 0) {
324 if (attempts
++ == 1000) {
326 "Failed to receiving data from debug handler after 1000 attempts");
327 retval
= ERROR_TARGET_TIMEOUT
;
332 words_done
+= words_scheduled
;
335 for (i
= 0; i
< num_words
; i
++)
336 *(buffer
++) = buf_get_u32((uint8_t *)&field1
[i
], 0, 32);
343 static int xscale_read_tx(struct target
*target
, int consume
)
345 struct xscale_common
*xscale
= target_to_xscale(target
);
347 tap_state_t noconsume_path
[6];
349 struct timeval timeout
, now
;
350 struct scan_field fields
[3];
351 uint8_t field0_in
= 0x0;
352 uint8_t field0_check_value
= 0x2;
353 uint8_t field0_check_mask
= 0x6;
354 uint8_t field2_check_value
= 0x0;
355 uint8_t field2_check_mask
= 0x1;
357 xscale_jtag_set_instr(target
->tap
,
358 XSCALE_DBGTX
<< xscale
->xscale_variant
,
361 path
[0] = TAP_DRSELECT
;
362 path
[1] = TAP_DRCAPTURE
;
363 path
[2] = TAP_DRSHIFT
;
365 noconsume_path
[0] = TAP_DRSELECT
;
366 noconsume_path
[1] = TAP_DRCAPTURE
;
367 noconsume_path
[2] = TAP_DREXIT1
;
368 noconsume_path
[3] = TAP_DRPAUSE
;
369 noconsume_path
[4] = TAP_DREXIT2
;
370 noconsume_path
[5] = TAP_DRSHIFT
;
372 memset(&fields
, 0, sizeof fields
);
374 fields
[0].num_bits
= 3;
375 fields
[0].in_value
= &field0_in
;
377 fields
[1].num_bits
= 32;
378 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
380 fields
[2].num_bits
= 1;
382 fields
[2].in_value
= &tmp
;
384 gettimeofday(&timeout
, NULL
);
385 timeval_add_time(&timeout
, 1, 0);
388 /* if we want to consume the register content (i.e. clear TX_READY),
389 * we have to go straight from Capture-DR to Shift-DR
390 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
393 jtag_add_pathmove(3, path
);
395 jtag_add_pathmove(ARRAY_SIZE(noconsume_path
), noconsume_path
);
397 jtag_add_dr_scan(target
->tap
, 3, fields
, TAP_IDLE
);
399 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
400 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
402 retval
= jtag_execute_queue();
403 if (retval
!= ERROR_OK
) {
404 LOG_ERROR("JTAG error while reading TX");
405 return ERROR_TARGET_TIMEOUT
;
408 gettimeofday(&now
, NULL
);
409 if ((now
.tv_sec
> timeout
.tv_sec
) ||
410 ((now
.tv_sec
== timeout
.tv_sec
) && (now
.tv_usec
> timeout
.tv_usec
))) {
411 LOG_ERROR("time out reading TX register");
412 return ERROR_TARGET_TIMEOUT
;
414 if (!((!(field0_in
& 1)) && consume
))
416 if (debug_level
>= 3) {
417 LOG_DEBUG("waiting 100ms");
418 alive_sleep(100); /* avoid flooding the logs */
424 if (!(field0_in
& 1))
425 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
430 static int xscale_write_rx(struct target
*target
)
432 struct xscale_common
*xscale
= target_to_xscale(target
);
434 struct timeval timeout
, now
;
435 struct scan_field fields
[3];
436 uint8_t field0_out
= 0x0;
437 uint8_t field0_in
= 0x0;
438 uint8_t field0_check_value
= 0x2;
439 uint8_t field0_check_mask
= 0x6;
440 uint8_t field2
= 0x0;
441 uint8_t field2_check_value
= 0x0;
442 uint8_t field2_check_mask
= 0x1;
444 xscale_jtag_set_instr(target
->tap
,
445 XSCALE_DBGRX
<< xscale
->xscale_variant
,
448 memset(&fields
, 0, sizeof fields
);
450 fields
[0].num_bits
= 3;
451 fields
[0].out_value
= &field0_out
;
452 fields
[0].in_value
= &field0_in
;
454 fields
[1].num_bits
= 32;
455 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
457 fields
[2].num_bits
= 1;
458 fields
[2].out_value
= &field2
;
460 fields
[2].in_value
= &tmp
;
462 gettimeofday(&timeout
, NULL
);
463 timeval_add_time(&timeout
, 1, 0);
465 /* poll until rx_read is low */
466 LOG_DEBUG("polling RX");
468 jtag_add_dr_scan(target
->tap
, 3, fields
, TAP_IDLE
);
470 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
471 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
473 retval
= jtag_execute_queue();
474 if (retval
!= ERROR_OK
) {
475 LOG_ERROR("JTAG error while writing RX");
479 gettimeofday(&now
, NULL
);
480 if ((now
.tv_sec
> timeout
.tv_sec
) ||
481 ((now
.tv_sec
== timeout
.tv_sec
) && (now
.tv_usec
> timeout
.tv_usec
))) {
482 LOG_ERROR("time out writing RX register");
483 return ERROR_TARGET_TIMEOUT
;
485 if (!(field0_in
& 1))
487 if (debug_level
>= 3) {
488 LOG_DEBUG("waiting 100ms");
489 alive_sleep(100); /* avoid flooding the logs */
497 jtag_add_dr_scan(target
->tap
, 3, fields
, TAP_IDLE
);
499 retval
= jtag_execute_queue();
500 if (retval
!= ERROR_OK
) {
501 LOG_ERROR("JTAG error while writing RX");
508 /* send count elements of size byte to the debug handler */
509 static int xscale_send(struct target
*target
, const uint8_t *buffer
, int count
, int size
)
511 struct xscale_common
*xscale
= target_to_xscale(target
);
515 xscale_jtag_set_instr(target
->tap
,
516 XSCALE_DBGRX
<< xscale
->xscale_variant
,
519 static const uint8_t t0
;
521 static const uint8_t t2
= 1;
522 struct scan_field fields
[3] = {
523 { .num_bits
= 3, .out_value
= &t0
},
524 { .num_bits
= 32, .out_value
= t1
},
525 { .num_bits
= 1, .out_value
= &t2
},
528 int endianness
= target
->endianness
;
529 while (done_count
++ < count
) {
534 if (endianness
== TARGET_LITTLE_ENDIAN
)
535 t
= le_to_h_u32(buffer
);
537 t
= be_to_h_u32(buffer
);
540 if (endianness
== TARGET_LITTLE_ENDIAN
)
541 t
= le_to_h_u16(buffer
);
543 t
= be_to_h_u16(buffer
);
549 LOG_ERROR("BUG: size neither 4, 2 nor 1");
550 return ERROR_COMMAND_SYNTAX_ERROR
;
553 buf_set_u32(t1
, 0, 32, t
);
555 jtag_add_dr_scan(target
->tap
,
562 retval
= jtag_execute_queue();
563 if (retval
!= ERROR_OK
) {
564 LOG_ERROR("JTAG error while sending data to debug handler");
571 static int xscale_send_u32(struct target
*target
, uint32_t value
)
573 struct xscale_common
*xscale
= target_to_xscale(target
);
575 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
576 return xscale_write_rx(target
);
579 static int xscale_write_dcsr(struct target
*target
, int hold_rst
, int ext_dbg_brk
)
581 struct xscale_common
*xscale
= target_to_xscale(target
);
583 struct scan_field fields
[3];
584 uint8_t field0
= 0x0;
585 uint8_t field0_check_value
= 0x2;
586 uint8_t field0_check_mask
= 0x7;
587 uint8_t field2
= 0x0;
588 uint8_t field2_check_value
= 0x0;
589 uint8_t field2_check_mask
= 0x1;
592 xscale
->hold_rst
= hold_rst
;
594 if (ext_dbg_brk
!= -1)
595 xscale
->external_debug_break
= ext_dbg_brk
;
597 xscale_jtag_set_instr(target
->tap
,
598 XSCALE_SELDCSR
<< xscale
->xscale_variant
,
601 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
602 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
604 memset(&fields
, 0, sizeof fields
);
606 fields
[0].num_bits
= 3;
607 fields
[0].out_value
= &field0
;
609 fields
[0].in_value
= &tmp
;
611 fields
[1].num_bits
= 32;
612 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
614 fields
[2].num_bits
= 1;
615 fields
[2].out_value
= &field2
;
617 fields
[2].in_value
= &tmp2
;
619 jtag_add_dr_scan(target
->tap
, 3, fields
, TAP_IDLE
);
621 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
622 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
624 retval
= jtag_execute_queue();
625 if (retval
!= ERROR_OK
) {
626 LOG_ERROR("JTAG error while writing DCSR");
630 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
631 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
636 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
637 static unsigned int parity(unsigned int v
)
639 /* unsigned int ov = v; */
644 /* LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); */
645 return (0x6996 >> v
) & 1;
648 static int xscale_load_ic(struct target
*target
, uint32_t va
, uint32_t buffer
[8])
650 struct xscale_common
*xscale
= target_to_xscale(target
);
654 struct scan_field fields
[2];
656 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32
"", va
);
659 xscale_jtag_set_instr(target
->tap
,
660 XSCALE_LDIC
<< xscale
->xscale_variant
,
663 /* CMD is b011 to load a cacheline into the Mini ICache.
664 * Loading into the main ICache is deprecated, and unused.
665 * It's followed by three zero bits, and 27 address bits.
667 buf_set_u32(&cmd
, 0, 6, 0x3);
669 /* virtual address of desired cache line */
670 buf_set_u32(packet
, 0, 27, va
>> 5);
672 memset(&fields
, 0, sizeof fields
);
674 fields
[0].num_bits
= 6;
675 fields
[0].out_value
= &cmd
;
677 fields
[1].num_bits
= 27;
678 fields
[1].out_value
= packet
;
680 jtag_add_dr_scan(target
->tap
, 2, fields
, TAP_IDLE
);
682 /* rest of packet is a cacheline: 8 instructions, with parity */
683 fields
[0].num_bits
= 32;
684 fields
[0].out_value
= packet
;
686 fields
[1].num_bits
= 1;
687 fields
[1].out_value
= &cmd
;
689 for (word
= 0; word
< 8; word
++) {
690 buf_set_u32(packet
, 0, 32, buffer
[word
]);
693 memcpy(&value
, packet
, sizeof(uint32_t));
696 jtag_add_dr_scan(target
->tap
, 2, fields
, TAP_IDLE
);
699 return jtag_execute_queue();
702 static int xscale_invalidate_ic_line(struct target
*target
, uint32_t va
)
704 struct xscale_common
*xscale
= target_to_xscale(target
);
707 struct scan_field fields
[2];
709 xscale_jtag_set_instr(target
->tap
,
710 XSCALE_LDIC
<< xscale
->xscale_variant
,
713 /* CMD for invalidate IC line b000, bits [6:4] b000 */
714 buf_set_u32(&cmd
, 0, 6, 0x0);
716 /* virtual address of desired cache line */
717 buf_set_u32(packet
, 0, 27, va
>> 5);
719 memset(&fields
, 0, sizeof fields
);
721 fields
[0].num_bits
= 6;
722 fields
[0].out_value
= &cmd
;
724 fields
[1].num_bits
= 27;
725 fields
[1].out_value
= packet
;
727 jtag_add_dr_scan(target
->tap
, 2, fields
, TAP_IDLE
);
732 static int xscale_update_vectors(struct target
*target
)
734 struct xscale_common
*xscale
= target_to_xscale(target
);
738 uint32_t low_reset_branch
, high_reset_branch
;
740 for (i
= 1; i
< 8; i
++) {
741 /* if there's a static vector specified for this exception, override */
742 if (xscale
->static_high_vectors_set
& (1 << i
))
743 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
745 retval
= target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
746 if (retval
== ERROR_TARGET_TIMEOUT
)
748 if (retval
!= ERROR_OK
) {
749 /* Some of these reads will fail as part of normal execution */
750 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
755 for (i
= 1; i
< 8; i
++) {
756 if (xscale
->static_low_vectors_set
& (1 << i
))
757 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
759 retval
= target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
760 if (retval
== ERROR_TARGET_TIMEOUT
)
762 if (retval
!= ERROR_OK
) {
763 /* Some of these reads will fail as part of normal execution */
764 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
769 /* calculate branches to debug handler */
770 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
771 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
773 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
774 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
776 /* invalidate and load exception vectors in mini i-cache */
777 xscale_invalidate_ic_line(target
, 0x0);
778 xscale_invalidate_ic_line(target
, 0xffff0000);
780 xscale_load_ic(target
, 0x0, xscale
->low_vectors
);
781 xscale_load_ic(target
, 0xffff0000, xscale
->high_vectors
);
786 static int xscale_arch_state(struct target
*target
)
788 struct xscale_common
*xscale
= target_to_xscale(target
);
789 struct arm
*arm
= &xscale
->arm
;
791 static const char *state
[] = {
792 "disabled", "enabled"
795 static const char *arch_dbg_reason
[] = {
796 "", "\n(processor reset)", "\n(trace buffer full)"
799 if (arm
->common_magic
!= ARM_COMMON_MAGIC
) {
800 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
801 return ERROR_COMMAND_SYNTAX_ERROR
;
804 arm_arch_state(target
);
805 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
806 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
807 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
808 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
809 arch_dbg_reason
[xscale
->arch_debug_reason
]);
814 static int xscale_poll(struct target
*target
)
816 int retval
= ERROR_OK
;
818 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
)) {
819 enum target_state previous_state
= target
->state
;
820 retval
= xscale_read_tx(target
, 0);
821 if (retval
== ERROR_OK
) {
823 /* there's data to read from the tx register, we entered debug state */
824 target
->state
= TARGET_HALTED
;
826 /* process debug entry, fetching current mode regs */
827 retval
= xscale_debug_entry(target
);
828 } else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
829 LOG_USER("error while polling TX register, reset CPU");
830 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
831 target
->state
= TARGET_HALTED
;
834 /* debug_entry could have overwritten target state (i.e. immediate resume)
835 * don't signal event handlers in that case
837 if (target
->state
!= TARGET_HALTED
)
840 /* if target was running, signal that we halted
841 * otherwise we reentered from debug execution */
842 if (previous_state
== TARGET_RUNNING
)
843 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
845 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
851 static int xscale_debug_entry(struct target
*target
)
853 struct xscale_common
*xscale
= target_to_xscale(target
);
854 struct arm
*arm
= &xscale
->arm
;
861 /* clear external dbg break (will be written on next DCSR read) */
862 xscale
->external_debug_break
= 0;
863 retval
= xscale_read_dcsr(target
);
864 if (retval
!= ERROR_OK
)
867 /* get r0, pc, r1 to r7 and cpsr */
868 retval
= xscale_receive(target
, buffer
, 10);
869 if (retval
!= ERROR_OK
)
872 /* move r0 from buffer to register cache */
873 buf_set_u32(arm
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
874 arm
->core_cache
->reg_list
[0].dirty
= 1;
875 arm
->core_cache
->reg_list
[0].valid
= 1;
876 LOG_DEBUG("r0: 0x%8.8" PRIx32
"", buffer
[0]);
878 /* move pc from buffer to register cache */
879 buf_set_u32(arm
->pc
->value
, 0, 32, buffer
[1]);
882 LOG_DEBUG("pc: 0x%8.8" PRIx32
"", buffer
[1]);
884 /* move data from buffer to register cache */
885 for (i
= 1; i
<= 7; i
++) {
886 buf_set_u32(arm
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
887 arm
->core_cache
->reg_list
[i
].dirty
= 1;
888 arm
->core_cache
->reg_list
[i
].valid
= 1;
889 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, buffer
[i
+ 1]);
892 arm_set_cpsr(arm
, buffer
[9]);
893 LOG_DEBUG("cpsr: 0x%8.8" PRIx32
"", buffer
[9]);
895 if (!is_arm_mode(arm
->core_mode
)) {
896 target
->state
= TARGET_UNKNOWN
;
897 LOG_ERROR("cpsr contains invalid mode value - communication failure");
898 return ERROR_TARGET_FAILURE
;
900 LOG_DEBUG("target entered debug state in %s mode",
901 arm_mode_name(arm
->core_mode
));
903 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
905 xscale_receive(target
, buffer
, 8);
906 buf_set_u32(arm
->spsr
->value
, 0, 32, buffer
[7]);
907 arm
->spsr
->dirty
= false;
908 arm
->spsr
->valid
= true;
910 /* r8 to r14, but no spsr */
911 xscale_receive(target
, buffer
, 7);
914 /* move data from buffer to right banked register in cache */
915 for (i
= 8; i
<= 14; i
++) {
916 struct reg
*r
= arm_reg_current(arm
, i
);
918 buf_set_u32(r
->value
, 0, 32, buffer
[i
- 8]);
923 /* mark xscale regs invalid to ensure they are retrieved from the
924 * debug handler if requested */
925 for (i
= 0; i
< xscale
->reg_cache
->num_regs
; i
++)
926 xscale
->reg_cache
->reg_list
[i
].valid
= 0;
928 /* examine debug reason */
929 xscale_read_dcsr(target
);
930 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
932 /* stored PC (for calculating fixup) */
933 pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
936 case 0x0: /* Processor reset */
937 target
->debug_reason
= DBG_REASON_DBGRQ
;
938 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
941 case 0x1: /* Instruction breakpoint hit */
942 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
943 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
946 case 0x2: /* Data breakpoint hit */
947 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
948 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
951 case 0x3: /* BKPT instruction executed */
952 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
953 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
956 case 0x4: /* Ext. debug event */
957 target
->debug_reason
= DBG_REASON_DBGRQ
;
958 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
961 case 0x5: /* Vector trap occured */
962 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
963 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
966 case 0x6: /* Trace buffer full break */
967 target
->debug_reason
= DBG_REASON_DBGRQ
;
968 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
971 case 0x7: /* Reserved (may flag Hot-Debug support) */
973 LOG_ERROR("Method of Entry is 'Reserved'");
979 buf_set_u32(arm
->pc
->value
, 0, 32, pc
);
981 /* on the first debug entry, identify cache type */
982 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1) {
983 uint32_t cache_type_reg
;
985 /* read cp15 cache type register */
986 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
987 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
,
991 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
994 /* examine MMU and Cache settings
995 * read cp15 control register */
996 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
997 xscale
->cp15_control_reg
=
998 buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
999 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1000 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
=
1001 (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1002 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
=
1003 (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1005 /* tracing enabled, read collected trace data */
1006 if (xscale
->trace
.mode
!= XSCALE_TRACE_DISABLED
) {
1007 xscale_read_trace(target
);
1009 /* Resume if entered debug due to buffer fill and we're still collecting
1010 * trace data. Note that a debug exception due to trace buffer full
1011 * can only happen in fill mode. */
1012 if (xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
) {
1013 if (--xscale
->trace
.fill_counter
> 0)
1014 xscale_resume(target
, 1, 0x0, 1, 0);
1015 } else /* entered debug for other reason; reset counter */
1016 xscale
->trace
.fill_counter
= 0;
1022 static int xscale_halt(struct target
*target
)
1024 struct xscale_common
*xscale
= target_to_xscale(target
);
1026 LOG_DEBUG("target->state: %s",
1027 target_state_name(target
));
1029 if (target
->state
== TARGET_HALTED
) {
1030 LOG_DEBUG("target was already halted");
1032 } else if (target
->state
== TARGET_UNKNOWN
) {
1033 /* this must not happen for a xscale target */
1034 LOG_ERROR("target was in unknown state when halt was requested");
1035 return ERROR_TARGET_INVALID
;
1036 } else if (target
->state
== TARGET_RESET
)
1037 LOG_DEBUG("target->state == TARGET_RESET");
1039 /* assert external dbg break */
1040 xscale
->external_debug_break
= 1;
1041 xscale_read_dcsr(target
);
1043 target
->debug_reason
= DBG_REASON_DBGRQ
;
1049 static int xscale_enable_single_step(struct target
*target
, uint32_t next_pc
)
1051 struct xscale_common
*xscale
= target_to_xscale(target
);
1052 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1055 if (xscale
->ibcr0_used
) {
1056 struct breakpoint
*ibcr0_bp
=
1057 breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1060 xscale_unset_breakpoint(target
, ibcr0_bp
);
1063 "BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1068 retval
= xscale_set_reg_u32(ibcr0
, next_pc
| 0x1);
1069 if (retval
!= ERROR_OK
)
1075 static int xscale_disable_single_step(struct target
*target
)
1077 struct xscale_common
*xscale
= target_to_xscale(target
);
1078 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1081 retval
= xscale_set_reg_u32(ibcr0
, 0x0);
1082 if (retval
!= ERROR_OK
)
1088 static void xscale_enable_watchpoints(struct target
*target
)
1090 struct watchpoint
*watchpoint
= target
->watchpoints
;
1092 while (watchpoint
) {
1093 if (watchpoint
->set
== 0)
1094 xscale_set_watchpoint(target
, watchpoint
);
1095 watchpoint
= watchpoint
->next
;
1099 static void xscale_enable_breakpoints(struct target
*target
)
1101 struct breakpoint
*breakpoint
= target
->breakpoints
;
1103 /* set any pending breakpoints */
1104 while (breakpoint
) {
1105 if (breakpoint
->set
== 0)
1106 xscale_set_breakpoint(target
, breakpoint
);
1107 breakpoint
= breakpoint
->next
;
1111 static void xscale_free_trace_data(struct xscale_common
*xscale
)
1113 struct xscale_trace_data
*td
= xscale
->trace
.data
;
1115 struct xscale_trace_data
*next_td
= td
->next
;
1121 xscale
->trace
.data
= NULL
;
1124 static int xscale_resume(struct target
*target
, int current
,
1125 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1127 struct xscale_common
*xscale
= target_to_xscale(target
);
1128 struct arm
*arm
= &xscale
->arm
;
1129 uint32_t current_pc
;
1135 if (target
->state
!= TARGET_HALTED
) {
1136 LOG_WARNING("target not halted");
1137 return ERROR_TARGET_NOT_HALTED
;
1140 if (!debug_execution
)
1141 target_free_all_working_areas(target
);
1143 /* update vector tables */
1144 retval
= xscale_update_vectors(target
);
1145 if (retval
!= ERROR_OK
)
1148 /* current = 1: continue on current pc, otherwise continue at <address> */
1150 buf_set_u32(arm
->pc
->value
, 0, 32, address
);
1152 current_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
1154 /* if we're at the reset vector, we have to simulate the branch */
1155 if (current_pc
== 0x0) {
1156 arm_simulate_step(target
, NULL
);
1157 current_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
1160 /* the front-end may request us not to handle breakpoints */
1161 if (handle_breakpoints
) {
1162 struct breakpoint
*breakpoint
;
1163 breakpoint
= breakpoint_find(target
,
1164 buf_get_u32(arm
->pc
->value
, 0, 32));
1165 if (breakpoint
!= NULL
) {
1167 enum trace_mode saved_trace_mode
;
1169 /* there's a breakpoint at the current PC, we have to step over it */
1170 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1171 xscale_unset_breakpoint(target
, breakpoint
);
1173 /* calculate PC of next instruction */
1174 retval
= arm_simulate_step(target
, &next_pc
);
1175 if (retval
!= ERROR_OK
) {
1176 uint32_t current_opcode
;
1177 target_read_u32(target
, current_pc
, ¤t_opcode
);
1179 "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"",
1183 LOG_DEBUG("enable single-step");
1184 xscale_enable_single_step(target
, next_pc
);
1186 /* restore banked registers */
1187 retval
= xscale_restore_banked(target
);
1188 if (retval
!= ERROR_OK
)
1191 /* send resume request */
1192 xscale_send_u32(target
, 0x30);
1195 xscale_send_u32(target
,
1196 buf_get_u32(arm
->cpsr
->value
, 0, 32));
1197 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
,
1198 buf_get_u32(arm
->cpsr
->value
, 0, 32));
1200 for (i
= 7; i
>= 0; i
--) {
1202 xscale_send_u32(target
,
1203 buf_get_u32(arm
->core_cache
->reg_list
[i
].value
, 0, 32));
1204 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"",
1205 i
, buf_get_u32(arm
->core_cache
->reg_list
[i
].value
, 0, 32));
1209 xscale_send_u32(target
,
1210 buf_get_u32(arm
->pc
->value
, 0, 32));
1211 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
,
1212 buf_get_u32(arm
->pc
->value
, 0, 32));
1214 /* disable trace data collection in xscale_debug_entry() */
1215 saved_trace_mode
= xscale
->trace
.mode
;
1216 xscale
->trace
.mode
= XSCALE_TRACE_DISABLED
;
1218 /* wait for and process debug entry */
1219 xscale_debug_entry(target
);
1221 /* re-enable trace buffer, if enabled previously */
1222 xscale
->trace
.mode
= saved_trace_mode
;
1224 LOG_DEBUG("disable single-step");
1225 xscale_disable_single_step(target
);
1227 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1228 xscale_set_breakpoint(target
, breakpoint
);
1232 /* enable any pending breakpoints and watchpoints */
1233 xscale_enable_breakpoints(target
);
1234 xscale_enable_watchpoints(target
);
1236 /* restore banked registers */
1237 retval
= xscale_restore_banked(target
);
1238 if (retval
!= ERROR_OK
)
1241 /* send resume request (command 0x30 or 0x31)
1242 * clean the trace buffer if it is to be enabled (0x62) */
1243 if (xscale
->trace
.mode
!= XSCALE_TRACE_DISABLED
) {
1244 if (xscale
->trace
.mode
== XSCALE_TRACE_FILL
) {
1245 /* If trace enabled in fill mode and starting collection of new set
1246 * of buffers, initialize buffer counter and free previous buffers */
1247 if (xscale
->trace
.fill_counter
== 0) {
1248 xscale
->trace
.fill_counter
= xscale
->trace
.buffer_fill
;
1249 xscale_free_trace_data(xscale
);
1251 } else /* wrap mode; free previous buffer */
1252 xscale_free_trace_data(xscale
);
1254 xscale_send_u32(target
, 0x62);
1255 xscale_send_u32(target
, 0x31);
1257 xscale_send_u32(target
, 0x30);
1260 xscale_send_u32(target
, buf_get_u32(arm
->cpsr
->value
, 0, 32));
1261 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
,
1262 buf_get_u32(arm
->cpsr
->value
, 0, 32));
1264 for (i
= 7; i
>= 0; i
--) {
1266 xscale_send_u32(target
, buf_get_u32(arm
->core_cache
->reg_list
[i
].value
, 0, 32));
1267 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"",
1268 i
, buf_get_u32(arm
->core_cache
->reg_list
[i
].value
, 0, 32));
1272 xscale_send_u32(target
, buf_get_u32(arm
->pc
->value
, 0, 32));
1273 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32
,
1274 buf_get_u32(arm
->pc
->value
, 0, 32));
1276 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1278 if (!debug_execution
) {
1279 /* registers are now invalid */
1280 register_cache_invalidate(arm
->core_cache
);
1281 target
->state
= TARGET_RUNNING
;
1282 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1284 target
->state
= TARGET_DEBUG_RUNNING
;
1285 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1288 LOG_DEBUG("target resumed");
1293 static int xscale_step_inner(struct target
*target
, int current
,
1294 uint32_t address
, int handle_breakpoints
)
1296 struct xscale_common
*xscale
= target_to_xscale(target
);
1297 struct arm
*arm
= &xscale
->arm
;
1302 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1304 /* calculate PC of next instruction */
1305 retval
= arm_simulate_step(target
, &next_pc
);
1306 if (retval
!= ERROR_OK
) {
1307 uint32_t current_opcode
, current_pc
;
1308 current_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
1310 target_read_u32(target
, current_pc
, ¤t_opcode
);
1312 "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"",
1317 LOG_DEBUG("enable single-step");
1318 retval
= xscale_enable_single_step(target
, next_pc
);
1319 if (retval
!= ERROR_OK
)
1322 /* restore banked registers */
1323 retval
= xscale_restore_banked(target
);
1324 if (retval
!= ERROR_OK
)
1327 /* send resume request (command 0x30 or 0x31)
1328 * clean the trace buffer if it is to be enabled (0x62) */
1329 if (xscale
->trace
.mode
!= XSCALE_TRACE_DISABLED
) {
1330 retval
= xscale_send_u32(target
, 0x62);
1331 if (retval
!= ERROR_OK
)
1333 retval
= xscale_send_u32(target
, 0x31);
1334 if (retval
!= ERROR_OK
)
1337 retval
= xscale_send_u32(target
, 0x30);
1338 if (retval
!= ERROR_OK
)
1343 retval
= xscale_send_u32(target
,
1344 buf_get_u32(arm
->cpsr
->value
, 0, 32));
1345 if (retval
!= ERROR_OK
)
1347 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
,
1348 buf_get_u32(arm
->cpsr
->value
, 0, 32));
1350 for (i
= 7; i
>= 0; i
--) {
1352 retval
= xscale_send_u32(target
,
1353 buf_get_u32(arm
->core_cache
->reg_list
[i
].value
, 0, 32));
1354 if (retval
!= ERROR_OK
)
1356 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
,
1357 buf_get_u32(arm
->core_cache
->reg_list
[i
].value
, 0, 32));
1361 retval
= xscale_send_u32(target
,
1362 buf_get_u32(arm
->pc
->value
, 0, 32));
1363 if (retval
!= ERROR_OK
)
1365 LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32
,
1366 buf_get_u32(arm
->pc
->value
, 0, 32));
1368 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1370 /* registers are now invalid */
1371 register_cache_invalidate(arm
->core_cache
);
1373 /* wait for and process debug entry */
1374 retval
= xscale_debug_entry(target
);
1375 if (retval
!= ERROR_OK
)
1378 LOG_DEBUG("disable single-step");
1379 retval
= xscale_disable_single_step(target
);
1380 if (retval
!= ERROR_OK
)
1383 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1388 static int xscale_step(struct target
*target
, int current
,
1389 uint32_t address
, int handle_breakpoints
)
1391 struct arm
*arm
= target_to_arm(target
);
1392 struct breakpoint
*breakpoint
= NULL
;
1394 uint32_t current_pc
;
1397 if (target
->state
!= TARGET_HALTED
) {
1398 LOG_WARNING("target not halted");
1399 return ERROR_TARGET_NOT_HALTED
;
1402 /* current = 1: continue on current pc, otherwise continue at <address> */
1404 buf_set_u32(arm
->pc
->value
, 0, 32, address
);
1406 current_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
1408 /* if we're at the reset vector, we have to simulate the step */
1409 if (current_pc
== 0x0) {
1410 retval
= arm_simulate_step(target
, NULL
);
1411 if (retval
!= ERROR_OK
)
1413 current_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
1414 LOG_DEBUG("current pc %" PRIx32
, current_pc
);
1416 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1417 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1422 /* the front-end may request us not to handle breakpoints */
1423 if (handle_breakpoints
)
1424 breakpoint
= breakpoint_find(target
,
1425 buf_get_u32(arm
->pc
->value
, 0, 32));
1426 if (breakpoint
!= NULL
) {
1427 retval
= xscale_unset_breakpoint(target
, breakpoint
);
1428 if (retval
!= ERROR_OK
)
1432 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1433 if (retval
!= ERROR_OK
)
1437 xscale_set_breakpoint(target
, breakpoint
);
1439 LOG_DEBUG("target stepped");
1445 static int xscale_assert_reset(struct target
*target
)
1447 struct xscale_common
*xscale
= target_to_xscale(target
);
1449 LOG_DEBUG("target->state: %s",
1450 target_state_name(target
));
1453 jtag_add_reset(0, 1);
1455 /* sleep 1ms, to be sure we fulfill any requirements */
1456 jtag_add_sleep(1000);
1457 jtag_execute_queue();
1459 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1460 * end up in T-L-R, which would reset JTAG
1462 xscale_jtag_set_instr(target
->tap
,
1463 XSCALE_SELDCSR
<< xscale
->xscale_variant
,
1466 /* set Hold reset, Halt mode and Trap Reset */
1467 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1468 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1469 xscale_write_dcsr(target
, 1, 0);
1471 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1472 xscale_jtag_set_instr(target
->tap
, ~0, TAP_IDLE
);
1473 jtag_execute_queue();
1475 target
->state
= TARGET_RESET
;
1477 if (target
->reset_halt
) {
1478 int retval
= target_halt(target
);
1479 if (retval
!= ERROR_OK
)
1486 static int xscale_deassert_reset(struct target
*target
)
1488 struct xscale_common
*xscale
= target_to_xscale(target
);
1489 struct breakpoint
*breakpoint
= target
->breakpoints
;
1493 xscale
->ibcr_available
= 2;
1494 xscale
->ibcr0_used
= 0;
1495 xscale
->ibcr1_used
= 0;
1497 xscale
->dbr_available
= 2;
1498 xscale
->dbr0_used
= 0;
1499 xscale
->dbr1_used
= 0;
1501 /* mark all hardware breakpoints as unset */
1502 while (breakpoint
) {
1503 if (breakpoint
->type
== BKPT_HARD
)
1504 breakpoint
->set
= 0;
1505 breakpoint
= breakpoint
->next
;
1508 xscale
->trace
.mode
= XSCALE_TRACE_DISABLED
;
1509 xscale_free_trace_data(xscale
);
1511 register_cache_invalidate(xscale
->arm
.core_cache
);
1513 /* FIXME mark hardware watchpoints got unset too. Also,
1514 * at least some of the XScale registers are invalid...
1518 * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
1519 * contents got invalidated. Safer to force that, so writing new
1520 * contents can't ever fail..
1525 const uint8_t *buffer
= xscale_debug_handler
;
1529 jtag_add_reset(0, 0);
1531 /* wait 300ms; 150 and 100ms were not enough */
1532 jtag_add_sleep(300*1000);
1534 jtag_add_runtest(2030, TAP_IDLE
);
1535 jtag_execute_queue();
1537 /* set Hold reset, Halt mode and Trap Reset */
1538 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1539 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1540 xscale_write_dcsr(target
, 1, 0);
1542 /* Load the debug handler into the mini-icache. Since
1543 * it's using halt mode (not monitor mode), it runs in
1544 * "Special Debug State" for access to registers, memory,
1545 * coprocessors, trace data, etc.
1547 address
= xscale
->handler_address
;
1548 for (unsigned binary_size
= sizeof xscale_debug_handler
;
1550 binary_size
-= buf_cnt
, buffer
+= buf_cnt
) {
1551 uint32_t cache_line
[8];
1554 buf_cnt
= binary_size
;
1558 for (i
= 0; i
< buf_cnt
; i
+= 4) {
1559 /* convert LE buffer to host-endian uint32_t */
1560 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1563 for (; i
< 32; i
+= 4)
1564 cache_line
[i
/ 4] = 0xe1a08008;
1566 /* only load addresses other than the reset vectors */
1567 if ((address
% 0x400) != 0x0) {
1568 retval
= xscale_load_ic(target
, address
,
1570 if (retval
!= ERROR_OK
)
1577 retval
= xscale_load_ic(target
, 0x0,
1578 xscale
->low_vectors
);
1579 if (retval
!= ERROR_OK
)
1581 retval
= xscale_load_ic(target
, 0xffff0000,
1582 xscale
->high_vectors
);
1583 if (retval
!= ERROR_OK
)
1586 jtag_add_runtest(30, TAP_IDLE
);
1588 jtag_add_sleep(100000);
1590 /* set Hold reset, Halt mode and Trap Reset */
1591 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1592 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1593 xscale_write_dcsr(target
, 1, 0);
1595 /* clear Hold reset to let the target run (should enter debug handler) */
1596 xscale_write_dcsr(target
, 0, 1);
1597 target
->state
= TARGET_RUNNING
;
1599 if (!target
->reset_halt
) {
1600 jtag_add_sleep(10000);
1602 /* we should have entered debug now */
1603 xscale_debug_entry(target
);
1604 target
->state
= TARGET_HALTED
;
1606 /* resume the target */
1607 xscale_resume(target
, 1, 0x0, 1, 0);
1614 static int xscale_read_core_reg(struct target
*target
, struct reg
*r
,
1615 int num
, enum arm_mode mode
)
1617 /** \todo add debug handler support for core register reads */
1618 LOG_ERROR("not implemented");
1622 static int xscale_write_core_reg(struct target
*target
, struct reg
*r
,
1623 int num
, enum arm_mode mode
, uint8_t *value
)
1625 /** \todo add debug handler support for core register writes */
1626 LOG_ERROR("not implemented");
1630 static int xscale_full_context(struct target
*target
)
1632 struct arm
*arm
= target_to_arm(target
);
1640 if (target
->state
!= TARGET_HALTED
) {
1641 LOG_WARNING("target not halted");
1642 return ERROR_TARGET_NOT_HALTED
;
1645 buffer
= malloc(4 * 8);
1647 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1648 * we can't enter User mode on an XScale (unpredictable),
1649 * but User shares registers with SYS
1651 for (i
= 1; i
< 7; i
++) {
1652 enum arm_mode mode
= armv4_5_number_to_mode(i
);
1656 if (mode
== ARM_MODE_USR
)
1659 /* check if there are invalid registers in the current mode
1661 for (j
= 0; valid
&& j
<= 16; j
++) {
1662 if (!ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1669 /* request banked registers */
1670 xscale_send_u32(target
, 0x0);
1672 /* send CPSR for desired bank mode */
1673 xscale_send_u32(target
, mode
| 0xc0 /* I/F bits */);
1675 /* get banked registers: r8 to r14; and SPSR
1676 * except in USR/SYS mode
1678 if (mode
!= ARM_MODE_SYS
) {
1680 r
= &ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1683 xscale_receive(target
, buffer
, 8);
1685 buf_set_u32(r
->value
, 0, 32, buffer
[7]);
1689 xscale_receive(target
, buffer
, 7);
1691 /* move data from buffer to register cache */
1692 for (j
= 8; j
<= 14; j
++) {
1693 r
= &ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1696 buf_set_u32(r
->value
, 0, 32, buffer
[j
- 8]);
1707 static int xscale_restore_banked(struct target
*target
)
1709 struct arm
*arm
= target_to_arm(target
);
1713 if (target
->state
!= TARGET_HALTED
) {
1714 LOG_WARNING("target not halted");
1715 return ERROR_TARGET_NOT_HALTED
;
1718 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1719 * and check if any banked registers need to be written. Ignore
1720 * USR mode (number 0) in favor of SYS; we can't enter User mode on
1721 * an XScale (unpredictable), but they share all registers.
1723 for (i
= 1; i
< 7; i
++) {
1724 enum arm_mode mode
= armv4_5_number_to_mode(i
);
1727 if (mode
== ARM_MODE_USR
)
1730 /* check if there are dirty registers in this mode */
1731 for (j
= 8; j
<= 14; j
++) {
1732 if (ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1737 /* if not USR/SYS, check if the SPSR needs to be written */
1738 if (mode
!= ARM_MODE_SYS
) {
1739 if (ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1744 /* there's nothing to flush for this mode */
1748 /* command 0x1: "send banked registers" */
1749 xscale_send_u32(target
, 0x1);
1751 /* send CPSR for desired mode */
1752 xscale_send_u32(target
, mode
| 0xc0 /* I/F bits */);
1754 /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
1755 * but this protocol doesn't understand that nuance.
1757 for (j
= 8; j
<= 14; j
++) {
1758 r
= &ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1760 xscale_send_u32(target
, buf_get_u32(r
->value
, 0, 32));
1764 /* send spsr if not in USR/SYS mode */
1765 if (mode
!= ARM_MODE_SYS
) {
1766 r
= &ARMV4_5_CORE_REG_MODE(arm
->core_cache
,
1768 xscale_send_u32(target
, buf_get_u32(r
->value
, 0, 32));
1776 static int xscale_read_memory(struct target
*target
, uint32_t address
,
1777 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1779 struct xscale_common
*xscale
= target_to_xscale(target
);
1784 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
,
1789 if (target
->state
!= TARGET_HALTED
) {
1790 LOG_WARNING("target not halted");
1791 return ERROR_TARGET_NOT_HALTED
;
1794 /* sanitize arguments */
1795 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1796 return ERROR_COMMAND_SYNTAX_ERROR
;
1798 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1799 return ERROR_TARGET_UNALIGNED_ACCESS
;
1801 /* send memory read request (command 0x1n, n: access size) */
1802 retval
= xscale_send_u32(target
, 0x10 | size
);
1803 if (retval
!= ERROR_OK
)
1806 /* send base address for read request */
1807 retval
= xscale_send_u32(target
, address
);
1808 if (retval
!= ERROR_OK
)
1811 /* send number of requested data words */
1812 retval
= xscale_send_u32(target
, count
);
1813 if (retval
!= ERROR_OK
)
1816 /* receive data from target (count times 32-bit words in host endianness) */
1817 buf32
= malloc(4 * count
);
1818 retval
= xscale_receive(target
, buf32
, count
);
1819 if (retval
!= ERROR_OK
) {
1824 /* extract data from host-endian buffer into byte stream */
1825 for (i
= 0; i
< count
; i
++) {
1828 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1832 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1836 *buffer
++ = buf32
[i
] & 0xff;
1839 LOG_ERROR("invalid read size");
1840 return ERROR_COMMAND_SYNTAX_ERROR
;
1846 /* examine DCSR, to see if Sticky Abort (SA) got set */
1847 retval
= xscale_read_dcsr(target
);
1848 if (retval
!= ERROR_OK
)
1850 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1) {
1852 retval
= xscale_send_u32(target
, 0x60);
1853 if (retval
!= ERROR_OK
)
1856 return ERROR_TARGET_DATA_ABORT
;
1862 static int xscale_read_phys_memory(struct target
*target
, uint32_t address
,
1863 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1865 struct xscale_common
*xscale
= target_to_xscale(target
);
1867 /* with MMU inactive, there are only physical addresses */
1868 if (!xscale
->armv4_5_mmu
.mmu_enabled
)
1869 return xscale_read_memory(target
, address
, size
, count
, buffer
);
1871 /** \todo: provide a non-stub implementation of this routine. */
1872 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1873 target_name(target
), __func__
);
1877 static int xscale_write_memory(struct target
*target
, uint32_t address
,
1878 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1880 struct xscale_common
*xscale
= target_to_xscale(target
);
1883 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
,
1888 if (target
->state
!= TARGET_HALTED
) {
1889 LOG_WARNING("target not halted");
1890 return ERROR_TARGET_NOT_HALTED
;
1893 /* sanitize arguments */
1894 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1895 return ERROR_COMMAND_SYNTAX_ERROR
;
1897 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1898 return ERROR_TARGET_UNALIGNED_ACCESS
;
1900 /* send memory write request (command 0x2n, n: access size) */
1901 retval
= xscale_send_u32(target
, 0x20 | size
);
1902 if (retval
!= ERROR_OK
)
1905 /* send base address for read request */
1906 retval
= xscale_send_u32(target
, address
);
1907 if (retval
!= ERROR_OK
)
1910 /* send number of requested data words to be written*/
1911 retval
= xscale_send_u32(target
, count
);
1912 if (retval
!= ERROR_OK
)
1915 /* extract data from host-endian buffer into byte stream */
1917 for (i
= 0; i
< count
; i
++) {
1920 value
= target_buffer_get_u32(target
, buffer
);
1921 xscale_send_u32(target
, value
);
1925 value
= target_buffer_get_u16(target
, buffer
);
1926 xscale_send_u32(target
, value
);
1931 xscale_send_u32(target
, value
);
1935 LOG_ERROR("should never get here");
1940 retval
= xscale_send(target
, buffer
, count
, size
);
1941 if (retval
!= ERROR_OK
)
1944 /* examine DCSR, to see if Sticky Abort (SA) got set */
1945 retval
= xscale_read_dcsr(target
);
1946 if (retval
!= ERROR_OK
)
1948 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1) {
1950 retval
= xscale_send_u32(target
, 0x60);
1951 if (retval
!= ERROR_OK
)
1954 LOG_ERROR("data abort writing memory");
1955 return ERROR_TARGET_DATA_ABORT
;
1961 static int xscale_write_phys_memory(struct target
*target
, uint32_t address
,
1962 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1964 struct xscale_common
*xscale
= target_to_xscale(target
);
1966 /* with MMU inactive, there are only physical addresses */
1967 if (!xscale
->armv4_5_mmu
.mmu_enabled
)
1968 return xscale_write_memory(target
, address
, size
, count
, buffer
);
1970 /** \todo: provide a non-stub implementation of this routine. */
1971 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1972 target_name(target
), __func__
);
1976 static int xscale_get_ttb(struct target
*target
, uint32_t *result
)
1978 struct xscale_common
*xscale
= target_to_xscale(target
);
1982 retval
= xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
1983 if (retval
!= ERROR_OK
)
1985 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
1992 static int xscale_disable_mmu_caches(struct target
*target
, int mmu
,
1993 int d_u_cache
, int i_cache
)
1995 struct xscale_common
*xscale
= target_to_xscale(target
);
1996 uint32_t cp15_control
;
1999 /* read cp15 control register */
2000 retval
= xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2001 if (retval
!= ERROR_OK
)
2003 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2006 cp15_control
&= ~0x1U
;
2010 retval
= xscale_send_u32(target
, 0x50);
2011 if (retval
!= ERROR_OK
)
2013 retval
= xscale_send_u32(target
, xscale
->cache_clean_address
);
2014 if (retval
!= ERROR_OK
)
2017 /* invalidate DCache */
2018 retval
= xscale_send_u32(target
, 0x51);
2019 if (retval
!= ERROR_OK
)
2022 cp15_control
&= ~0x4U
;
2026 /* invalidate ICache */
2027 retval
= xscale_send_u32(target
, 0x52);
2028 if (retval
!= ERROR_OK
)
2030 cp15_control
&= ~0x1000U
;
2033 /* write new cp15 control register */
2034 retval
= xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2035 if (retval
!= ERROR_OK
)
2038 /* execute cpwait to ensure outstanding operations complete */
2039 retval
= xscale_send_u32(target
, 0x53);
2043 static int xscale_enable_mmu_caches(struct target
*target
, int mmu
,
2044 int d_u_cache
, int i_cache
)
2046 struct xscale_common
*xscale
= target_to_xscale(target
);
2047 uint32_t cp15_control
;
2050 /* read cp15 control register */
2051 retval
= xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2052 if (retval
!= ERROR_OK
)
2054 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2057 cp15_control
|= 0x1U
;
2060 cp15_control
|= 0x4U
;
2063 cp15_control
|= 0x1000U
;
2065 /* write new cp15 control register */
2066 retval
= xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2067 if (retval
!= ERROR_OK
)
2070 /* execute cpwait to ensure outstanding operations complete */
2071 retval
= xscale_send_u32(target
, 0x53);
2075 static int xscale_set_breakpoint(struct target
*target
,
2076 struct breakpoint
*breakpoint
)
2079 struct xscale_common
*xscale
= target_to_xscale(target
);
2081 if (target
->state
!= TARGET_HALTED
) {
2082 LOG_WARNING("target not halted");
2083 return ERROR_TARGET_NOT_HALTED
;
2086 if (breakpoint
->set
) {
2087 LOG_WARNING("breakpoint already set");
2091 if (breakpoint
->type
== BKPT_HARD
) {
2092 uint32_t value
= breakpoint
->address
| 1;
2093 if (!xscale
->ibcr0_used
) {
2094 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2095 xscale
->ibcr0_used
= 1;
2096 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2097 } else if (!xscale
->ibcr1_used
) {
2098 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2099 xscale
->ibcr1_used
= 1;
2100 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2101 } else {/* bug: availability previously verified in xscale_add_breakpoint() */
2102 LOG_ERROR("BUG: no hardware comparator available");
2103 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2105 } else if (breakpoint
->type
== BKPT_SOFT
) {
2106 if (breakpoint
->length
== 4) {
2107 /* keep the original instruction in target endianness */
2108 retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
2109 breakpoint
->orig_instr
);
2110 if (retval
!= ERROR_OK
)
2112 /* write the bkpt instruction in target endianness
2113 *(arm7_9->arm_bkpt is host endian) */
2114 retval
= target_write_u32(target
, breakpoint
->address
,
2116 if (retval
!= ERROR_OK
)
2119 /* keep the original instruction in target endianness */
2120 retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
2121 breakpoint
->orig_instr
);
2122 if (retval
!= ERROR_OK
)
2124 /* write the bkpt instruction in target endianness
2125 *(arm7_9->arm_bkpt is host endian) */
2126 retval
= target_write_u16(target
, breakpoint
->address
,
2127 xscale
->thumb_bkpt
);
2128 if (retval
!= ERROR_OK
)
2131 breakpoint
->set
= 1;
2133 xscale_send_u32(target
, 0x50); /* clean dcache */
2134 xscale_send_u32(target
, xscale
->cache_clean_address
);
2135 xscale_send_u32(target
, 0x51); /* invalidate dcache */
2136 xscale_send_u32(target
, 0x52); /* invalidate icache and flush fetch buffers */
2142 static int xscale_add_breakpoint(struct target
*target
,
2143 struct breakpoint
*breakpoint
)
2145 struct xscale_common
*xscale
= target_to_xscale(target
);
2147 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1)) {
2148 LOG_ERROR("no breakpoint unit available for hardware breakpoint");
2149 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2152 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4)) {
2153 LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2154 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2157 if (breakpoint
->type
== BKPT_HARD
)
2158 xscale
->ibcr_available
--;
2160 return xscale_set_breakpoint(target
, breakpoint
);
2163 static int xscale_unset_breakpoint(struct target
*target
,
2164 struct breakpoint
*breakpoint
)
2167 struct xscale_common
*xscale
= target_to_xscale(target
);
2169 if (target
->state
!= TARGET_HALTED
) {
2170 LOG_WARNING("target not halted");
2171 return ERROR_TARGET_NOT_HALTED
;
2174 if (!breakpoint
->set
) {
2175 LOG_WARNING("breakpoint not set");
2179 if (breakpoint
->type
== BKPT_HARD
) {
2180 if (breakpoint
->set
== 1) {
2181 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2182 xscale
->ibcr0_used
= 0;
2183 } else if (breakpoint
->set
== 2) {
2184 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2185 xscale
->ibcr1_used
= 0;
2187 breakpoint
->set
= 0;
2189 /* restore original instruction (kept in target endianness) */
2190 if (breakpoint
->length
== 4) {
2191 retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
2192 breakpoint
->orig_instr
);
2193 if (retval
!= ERROR_OK
)
2196 retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
2197 breakpoint
->orig_instr
);
2198 if (retval
!= ERROR_OK
)
2201 breakpoint
->set
= 0;
2203 xscale_send_u32(target
, 0x50); /* clean dcache */
2204 xscale_send_u32(target
, xscale
->cache_clean_address
);
2205 xscale_send_u32(target
, 0x51); /* invalidate dcache */
2206 xscale_send_u32(target
, 0x52); /* invalidate icache and flush fetch buffers */
2212 static int xscale_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
2214 struct xscale_common
*xscale
= target_to_xscale(target
);
2216 if (target
->state
!= TARGET_HALTED
) {
2217 LOG_ERROR("target not halted");
2218 return ERROR_TARGET_NOT_HALTED
;
2221 if (breakpoint
->set
)
2222 xscale_unset_breakpoint(target
, breakpoint
);
2224 if (breakpoint
->type
== BKPT_HARD
)
2225 xscale
->ibcr_available
++;
2230 static int xscale_set_watchpoint(struct target
*target
,
2231 struct watchpoint
*watchpoint
)
2233 struct xscale_common
*xscale
= target_to_xscale(target
);
2234 uint32_t enable
= 0;
2235 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2236 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2238 if (target
->state
!= TARGET_HALTED
) {
2239 LOG_ERROR("target not halted");
2240 return ERROR_TARGET_NOT_HALTED
;
2243 switch (watchpoint
->rw
) {
2254 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2257 /* For watchpoint across more than one word, both DBR registers must
2258 be enlisted, with the second used as a mask. */
2259 if (watchpoint
->length
> 4) {
2260 if (xscale
->dbr0_used
|| xscale
->dbr1_used
) {
2261 LOG_ERROR("BUG: sufficient hardware comparators unavailable");
2262 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2265 /* Write mask value to DBR1, based on the length argument.
2266 * Address bits ignored by the comparator are those set in mask. */
2267 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
],
2268 watchpoint
->length
- 1);
2269 xscale
->dbr1_used
= 1;
2270 enable
|= 0x100; /* DBCON[M] */
2273 if (!xscale
->dbr0_used
) {
2274 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2275 dbcon_value
|= enable
;
2276 xscale_set_reg_u32(dbcon
, dbcon_value
);
2277 watchpoint
->set
= 1;
2278 xscale
->dbr0_used
= 1;
2279 } else if (!xscale
->dbr1_used
) {
2280 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2281 dbcon_value
|= enable
<< 2;
2282 xscale_set_reg_u32(dbcon
, dbcon_value
);
2283 watchpoint
->set
= 2;
2284 xscale
->dbr1_used
= 1;
2286 LOG_ERROR("BUG: no hardware comparator available");
2287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2293 static int xscale_add_watchpoint(struct target
*target
,
2294 struct watchpoint
*watchpoint
)
2296 struct xscale_common
*xscale
= target_to_xscale(target
);
2298 if (xscale
->dbr_available
< 1) {
2299 LOG_ERROR("no more watchpoint registers available");
2300 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2303 if (watchpoint
->value
)
2304 LOG_WARNING("xscale does not support value, mask arguments; ignoring");
2306 /* check that length is a power of two */
2307 for (uint32_t len
= watchpoint
->length
; len
!= 1; len
/= 2) {
2309 LOG_ERROR("xscale requires that watchpoint length is a power of two");
2310 return ERROR_COMMAND_ARGUMENT_INVALID
;
2314 if (watchpoint
->length
== 4) { /* single word watchpoint */
2315 xscale
->dbr_available
--;/* one DBR reg used */
2319 /* watchpoints across multiple words require both DBR registers */
2320 if (xscale
->dbr_available
< 2) {
2321 LOG_ERROR("insufficient watchpoint registers available");
2322 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2325 if (watchpoint
->length
> watchpoint
->address
) {
2326 LOG_ERROR("xscale does not support watchpoints with length "
2327 "greater than address");
2328 return ERROR_COMMAND_ARGUMENT_INVALID
;
2331 xscale
->dbr_available
= 0;
2335 static int xscale_unset_watchpoint(struct target
*target
,
2336 struct watchpoint
*watchpoint
)
2338 struct xscale_common
*xscale
= target_to_xscale(target
);
2339 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2340 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2342 if (target
->state
!= TARGET_HALTED
) {
2343 LOG_WARNING("target not halted");
2344 return ERROR_TARGET_NOT_HALTED
;
2347 if (!watchpoint
->set
) {
2348 LOG_WARNING("breakpoint not set");
2352 if (watchpoint
->set
== 1) {
2353 if (watchpoint
->length
> 4) {
2354 dbcon_value
&= ~0x103; /* clear DBCON[M] as well */
2355 xscale
->dbr1_used
= 0; /* DBR1 was used for mask */
2357 dbcon_value
&= ~0x3;
2359 xscale_set_reg_u32(dbcon
, dbcon_value
);
2360 xscale
->dbr0_used
= 0;
2361 } else if (watchpoint
->set
== 2) {
2362 dbcon_value
&= ~0xc;
2363 xscale_set_reg_u32(dbcon
, dbcon_value
);
2364 xscale
->dbr1_used
= 0;
2366 watchpoint
->set
= 0;
2371 static int xscale_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2373 struct xscale_common
*xscale
= target_to_xscale(target
);
2375 if (target
->state
!= TARGET_HALTED
) {
2376 LOG_ERROR("target not halted");
2377 return ERROR_TARGET_NOT_HALTED
;
2380 if (watchpoint
->set
)
2381 xscale_unset_watchpoint(target
, watchpoint
);
2383 if (watchpoint
->length
> 4)
2384 xscale
->dbr_available
++;/* both DBR regs now available */
2386 xscale
->dbr_available
++;
2391 static int xscale_get_reg(struct reg
*reg
)
2393 struct xscale_reg
*arch_info
= reg
->arch_info
;
2394 struct target
*target
= arch_info
->target
;
2395 struct xscale_common
*xscale
= target_to_xscale(target
);
2397 /* DCSR, TX and RX are accessible via JTAG */
2398 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2399 return xscale_read_dcsr(arch_info
->target
);
2400 else if (strcmp(reg
->name
, "XSCALE_TX") == 0) {
2401 /* 1 = consume register content */
2402 return xscale_read_tx(arch_info
->target
, 1);
2403 } else if (strcmp(reg
->name
, "XSCALE_RX") == 0) {
2404 /* can't read from RX register (host -> debug handler) */
2406 } else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0) {
2407 /* can't (explicitly) read from TXRXCTRL register */
2409 } else {/* Other DBG registers have to be transfered by the debug handler
2410 * send CP read request (command 0x40) */
2411 xscale_send_u32(target
, 0x40);
2413 /* send CP register number */
2414 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2416 /* read register value */
2417 xscale_read_tx(target
, 1);
2418 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2427 static int xscale_set_reg(struct reg
*reg
, uint8_t *buf
)
2429 struct xscale_reg
*arch_info
= reg
->arch_info
;
2430 struct target
*target
= arch_info
->target
;
2431 struct xscale_common
*xscale
= target_to_xscale(target
);
2432 uint32_t value
= buf_get_u32(buf
, 0, 32);
2434 /* DCSR, TX and RX are accessible via JTAG */
2435 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0) {
2436 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2437 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2438 } else if (strcmp(reg
->name
, "XSCALE_RX") == 0) {
2439 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2440 return xscale_write_rx(arch_info
->target
);
2441 } else if (strcmp(reg
->name
, "XSCALE_TX") == 0) {
2442 /* can't write to TX register (debug-handler -> host) */
2444 } else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0) {
2445 /* can't (explicitly) write to TXRXCTRL register */
2447 } else {/* Other DBG registers have to be transfered by the debug handler
2448 * send CP write request (command 0x41) */
2449 xscale_send_u32(target
, 0x41);
2451 /* send CP register number */
2452 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2454 /* send CP register value */
2455 xscale_send_u32(target
, value
);
2456 buf_set_u32(reg
->value
, 0, 32, value
);
2462 static int xscale_write_dcsr_sw(struct target
*target
, uint32_t value
)
2464 struct xscale_common
*xscale
= target_to_xscale(target
);
2465 struct reg
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2466 struct xscale_reg
*dcsr_arch_info
= dcsr
->arch_info
;
2468 /* send CP write request (command 0x41) */
2469 xscale_send_u32(target
, 0x41);
2471 /* send CP register number */
2472 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2474 /* send CP register value */
2475 xscale_send_u32(target
, value
);
2476 buf_set_u32(dcsr
->value
, 0, 32, value
);
2481 static int xscale_read_trace(struct target
*target
)
2483 struct xscale_common
*xscale
= target_to_xscale(target
);
2484 struct arm
*arm
= &xscale
->arm
;
2485 struct xscale_trace_data
**trace_data_p
;
2487 /* 258 words from debug handler
2488 * 256 trace buffer entries
2489 * 2 checkpoint addresses
2491 uint32_t trace_buffer
[258];
2492 int is_address
[256];
2494 unsigned int num_checkpoints
= 0;
2496 if (target
->state
!= TARGET_HALTED
) {
2497 LOG_WARNING("target must be stopped to read trace data");
2498 return ERROR_TARGET_NOT_HALTED
;
2501 /* send read trace buffer command (command 0x61) */
2502 xscale_send_u32(target
, 0x61);
2504 /* receive trace buffer content */
2505 xscale_receive(target
, trace_buffer
, 258);
2507 /* parse buffer backwards to identify address entries */
2508 for (i
= 255; i
>= 0; i
--) {
2509 /* also count number of checkpointed entries */
2510 if ((trace_buffer
[i
] & 0xe0) == 0xc0)
2514 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2515 ((trace_buffer
[i
] & 0xf0) == 0xd0)) {
2517 is_address
[--i
] = 1;
2519 is_address
[--i
] = 1;
2521 is_address
[--i
] = 1;
2523 is_address
[--i
] = 1;
2528 /* search first non-zero entry that is not part of an address */
2529 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2533 LOG_DEBUG("no trace data collected");
2534 return ERROR_XSCALE_NO_TRACE_DATA
;
2537 /* account for possible partial address at buffer start (wrap mode only) */
2538 if (is_address
[0]) { /* first entry is address; complete set of 4? */
2541 if (!is_address
[i
++])
2544 j
+= i
; /* partial address; can't use it */
2547 /* if first valid entry is indirect branch, can't use that either (no address) */
2548 if (((trace_buffer
[j
] & 0xf0) == 0x90) || ((trace_buffer
[j
] & 0xf0) == 0xd0))
2551 /* walk linked list to terminating entry */
2552 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
;
2553 trace_data_p
= &(*trace_data_p
)->next
)
2556 *trace_data_p
= malloc(sizeof(struct xscale_trace_data
));
2557 (*trace_data_p
)->next
= NULL
;
2558 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2559 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2560 (*trace_data_p
)->last_instruction
= buf_get_u32(arm
->pc
->value
, 0, 32);
2561 (*trace_data_p
)->entries
= malloc(sizeof(struct xscale_trace_entry
) * (256 - j
));
2562 (*trace_data_p
)->depth
= 256 - j
;
2563 (*trace_data_p
)->num_checkpoints
= num_checkpoints
;
2565 for (i
= j
; i
< 256; i
++) {
2566 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2568 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2570 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2576 static int xscale_read_instruction(struct target
*target
, uint32_t pc
,
2577 struct arm_instruction
*instruction
)
2579 struct xscale_common
*const xscale
= target_to_xscale(target
);
2586 if (!xscale
->trace
.image
)
2587 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2589 /* search for the section the current instruction belongs to */
2590 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++) {
2591 if ((xscale
->trace
.image
->sections
[i
].base_address
<= pc
) &&
2592 (xscale
->trace
.image
->sections
[i
].base_address
+
2593 xscale
->trace
.image
->sections
[i
].size
> pc
)) {
2599 if (section
== -1) {
2600 /* current instruction couldn't be found in the image */
2601 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2604 if (xscale
->trace
.core_state
== ARM_STATE_ARM
) {
2606 retval
= image_read_section(xscale
->trace
.image
, section
,
2607 pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2608 4, buf
, &size_read
);
2609 if (retval
!= ERROR_OK
) {
2610 LOG_ERROR("error while reading instruction");
2611 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2613 opcode
= target_buffer_get_u32(target
, buf
);
2614 arm_evaluate_opcode(opcode
, pc
, instruction
);
2615 } else if (xscale
->trace
.core_state
== ARM_STATE_THUMB
) {
2617 retval
= image_read_section(xscale
->trace
.image
, section
,
2618 pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2619 2, buf
, &size_read
);
2620 if (retval
!= ERROR_OK
) {
2621 LOG_ERROR("error while reading instruction");
2622 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2624 opcode
= target_buffer_get_u16(target
, buf
);
2625 thumb_evaluate_opcode(opcode
, pc
, instruction
);
2627 LOG_ERROR("BUG: unknown core state encountered");
2634 /* Extract address encoded into trace data.
2635 * Write result to address referenced by argument 'target', or 0 if incomplete. */
2636 static inline void xscale_branch_address(struct xscale_trace_data
*trace_data
,
2637 int i
, uint32_t *target
)
2639 /* if there are less than four entries prior to the indirect branch message
2640 * we can't extract the address */
2644 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2645 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2649 static inline void xscale_display_instruction(struct target
*target
, uint32_t pc
,
2650 struct arm_instruction
*instruction
,
2651 struct command_context
*cmd_ctx
)
2653 int retval
= xscale_read_instruction(target
, pc
, instruction
);
2654 if (retval
== ERROR_OK
)
2655 command_print(cmd_ctx
, "%s", instruction
->text
);
2657 command_print(cmd_ctx
, "0x%8.8" PRIx32
"\t<not found in image>", pc
);
2660 static int xscale_analyze_trace(struct target
*target
, struct command_context
*cmd_ctx
)
2662 struct xscale_common
*xscale
= target_to_xscale(target
);
2663 struct xscale_trace_data
*trace_data
= xscale
->trace
.data
;
2665 uint32_t breakpoint_pc
;
2666 struct arm_instruction instruction
;
2667 uint32_t current_pc
= 0;/* initialized when address determined */
2669 if (!xscale
->trace
.image
)
2670 LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
2672 /* loop for each trace buffer that was loaded from target */
2673 while (trace_data
) {
2674 int chkpt
= 0; /* incremented as checkpointed entries found */
2677 /* FIXME: set this to correct mode when trace buffer is first enabled */
2678 xscale
->trace
.core_state
= ARM_STATE_ARM
;
2680 /* loop for each entry in this trace buffer */
2681 for (i
= 0; i
< trace_data
->depth
; i
++) {
2683 uint32_t chkpt_reg
= 0x0;
2684 uint32_t branch_target
= 0;
2687 /* trace entry type is upper nybble of 'message byte' */
2688 int trace_msg_type
= (trace_data
->entries
[i
].data
& 0xf0) >> 4;
2690 /* Target addresses of indirect branches are written into buffer
2691 * before the message byte representing the branch. Skip past it */
2692 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2695 switch (trace_msg_type
) {
2696 case 0: /* Exceptions */
2704 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2706 /* FIXME: vector table may be at ffff0000 */
2707 branch_target
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2710 case 8: /* Direct Branch */
2713 case 9: /* Indirect Branch */
2714 xscale_branch_address(trace_data
, i
, &branch_target
);
2717 case 13: /* Checkpointed Indirect Branch */
2718 xscale_branch_address(trace_data
, i
, &branch_target
);
2719 if ((trace_data
->num_checkpoints
== 2) && (chkpt
== 0))
2720 chkpt_reg
= trace_data
->chkpt1
; /* 2 chkpts, this is
2723 chkpt_reg
= trace_data
->chkpt0
; /* 1 chkpt, or 2 and
2729 case 12: /* Checkpointed Direct Branch */
2730 if ((trace_data
->num_checkpoints
== 2) && (chkpt
== 0))
2731 chkpt_reg
= trace_data
->chkpt1
; /* 2 chkpts, this is
2734 chkpt_reg
= trace_data
->chkpt0
; /* 1 chkpt, or 2 and
2737 /* if no current_pc, checkpoint will be starting point */
2738 if (current_pc
== 0)
2739 branch_target
= chkpt_reg
;
2744 case 15:/* Roll-over */
2747 default:/* Reserved */
2748 LOG_WARNING("trace is suspect: invalid trace message byte");
2753 /* If we don't have the current_pc yet, but we did get the branch target
2754 * (either from the trace buffer on indirect branch, or from a checkpoint reg),
2755 * then we can start displaying instructions at the next iteration, with
2756 * branch_target as the starting point.
2758 if (current_pc
== 0) {
2759 current_pc
= branch_target
; /* remains 0 unless branch_target *obtained */
2763 /* We have current_pc. Read and display the instructions from the image.
2764 * First, display count instructions (lower nybble of message byte). */
2765 count
= trace_data
->entries
[i
].data
& 0x0f;
2766 for (j
= 0; j
< count
; j
++) {
2767 xscale_display_instruction(target
, current_pc
, &instruction
,
2769 current_pc
+= xscale
->trace
.core_state
== ARM_STATE_ARM
? 4 : 2;
2772 /* An additional instruction is implicitly added to count for
2773 * rollover and some exceptions: undef, swi, prefetch abort. */
2774 if ((trace_msg_type
== 15) || (exception
> 0 && exception
< 4)) {
2775 xscale_display_instruction(target
, current_pc
, &instruction
,
2777 current_pc
+= xscale
->trace
.core_state
== ARM_STATE_ARM
? 4 : 2;
2780 if (trace_msg_type
== 15) /* rollover */
2784 command_print(cmd_ctx
, "--- exception %i ---", exception
);
2788 /* not exception or rollover; next instruction is a branch and is
2789 * not included in the count */
2790 xscale_display_instruction(target
, current_pc
, &instruction
, cmd_ctx
);
2792 /* for direct branches, extract branch destination from instruction */
2793 if ((trace_msg_type
== 8) || (trace_msg_type
== 12)) {
2794 retval
= xscale_read_instruction(target
, current_pc
, &instruction
);
2795 if (retval
== ERROR_OK
)
2796 current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2798 current_pc
= 0; /* branch destination unknown */
2800 /* direct branch w/ checkpoint; can also get from checkpoint reg */
2801 if (trace_msg_type
== 12) {
2802 if (current_pc
== 0)
2803 current_pc
= chkpt_reg
;
2804 else if (current_pc
!= chkpt_reg
) /* sanity check */
2805 LOG_WARNING("trace is suspect: checkpoint register "
2806 "inconsistent with adddress from image");
2809 if (current_pc
== 0)
2810 command_print(cmd_ctx
, "address unknown");
2815 /* indirect branch; the branch destination was read from trace buffer */
2816 if ((trace_msg_type
== 9) || (trace_msg_type
== 13)) {
2817 current_pc
= branch_target
;
2819 /* sanity check (checkpoint reg is redundant) */
2820 if ((trace_msg_type
== 13) && (chkpt_reg
!= branch_target
))
2821 LOG_WARNING("trace is suspect: checkpoint register "
2822 "inconsistent with address from trace buffer");
2825 } /* END: for (i = 0; i < trace_data->depth; i++) */
2827 breakpoint_pc
= trace_data
->last_instruction
; /* used below */
2828 trace_data
= trace_data
->next
;
2830 } /* END: while (trace_data) */
2832 /* Finally... display all instructions up to the value of the pc when the
2833 * debug break occurred (saved when trace data was collected from target).
2834 * This is necessary because the trace only records execution branches and 16
2835 * consecutive instructions (rollovers), so last few typically missed.
2837 if (current_pc
== 0)
2838 return ERROR_OK
;/* current_pc was never found */
2840 /* how many instructions remaining? */
2841 int gap_count
= (breakpoint_pc
- current_pc
) /
2842 (xscale
->trace
.core_state
== ARM_STATE_ARM
? 4 : 2);
2844 /* should never be negative or over 16, but verify */
2845 if (gap_count
< 0 || gap_count
> 16) {
2846 LOG_WARNING("trace is suspect: excessive gap at end of trace");
2847 return ERROR_OK
;/* bail; large number or negative value no good */
2850 /* display remaining instructions */
2851 for (i
= 0; i
< gap_count
; i
++) {
2852 xscale_display_instruction(target
, current_pc
, &instruction
, cmd_ctx
);
2853 current_pc
+= xscale
->trace
.core_state
== ARM_STATE_ARM
? 4 : 2;
2859 static const struct reg_arch_type xscale_reg_type
= {
2860 .get
= xscale_get_reg
,
2861 .set
= xscale_set_reg
,
2864 static void xscale_build_reg_cache(struct target
*target
)
2866 struct xscale_common
*xscale
= target_to_xscale(target
);
2867 struct arm
*arm
= &xscale
->arm
;
2868 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2869 struct xscale_reg
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2871 int num_regs
= ARRAY_SIZE(xscale_reg_arch_info
);
2873 (*cache_p
) = arm_build_reg_cache(target
, arm
);
2875 (*cache_p
)->next
= malloc(sizeof(struct reg_cache
));
2876 cache_p
= &(*cache_p
)->next
;
2878 /* fill in values for the xscale reg cache */
2879 (*cache_p
)->name
= "XScale registers";
2880 (*cache_p
)->next
= NULL
;
2881 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(struct reg
));
2882 (*cache_p
)->num_regs
= num_regs
;
2884 for (i
= 0; i
< num_regs
; i
++) {
2885 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2886 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2887 (*cache_p
)->reg_list
[i
].dirty
= 0;
2888 (*cache_p
)->reg_list
[i
].valid
= 0;
2889 (*cache_p
)->reg_list
[i
].size
= 32;
2890 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2891 (*cache_p
)->reg_list
[i
].type
= &xscale_reg_type
;
2892 arch_info
[i
] = xscale_reg_arch_info
[i
];
2893 arch_info
[i
].target
= target
;
2896 xscale
->reg_cache
= (*cache_p
);
2899 static int xscale_init_target(struct command_context
*cmd_ctx
,
2900 struct target
*target
)
2902 xscale_build_reg_cache(target
);
2906 static int xscale_init_arch_info(struct target
*target
,
2907 struct xscale_common
*xscale
, struct jtag_tap
*tap
)
2910 uint32_t high_reset_branch
, low_reset_branch
;
2915 /* store architecture specfic data */
2916 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
2918 /* PXA3xx with 11 bit IR shifts the JTAG instructions */
2919 if (tap
->ir_length
== 11)
2920 xscale
->xscale_variant
= XSCALE_PXA3XX
;
2922 xscale
->xscale_variant
= XSCALE_IXP4XX_PXA2XX
;
2924 /* the debug handler isn't installed (and thus not running) at this time */
2925 xscale
->handler_address
= 0xfe000800;
2927 /* clear the vectors we keep locally for reference */
2928 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
2929 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
2931 /* no user-specified vectors have been configured yet */
2932 xscale
->static_low_vectors_set
= 0x0;
2933 xscale
->static_high_vectors_set
= 0x0;
2935 /* calculate branches to debug handler */
2936 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
2937 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
2939 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
2940 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
2942 for (i
= 1; i
<= 7; i
++) {
2943 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2944 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2947 /* 64kB aligned region used for DCache cleaning */
2948 xscale
->cache_clean_address
= 0xfffe0000;
2950 xscale
->hold_rst
= 0;
2951 xscale
->external_debug_break
= 0;
2953 xscale
->ibcr_available
= 2;
2954 xscale
->ibcr0_used
= 0;
2955 xscale
->ibcr1_used
= 0;
2957 xscale
->dbr_available
= 2;
2958 xscale
->dbr0_used
= 0;
2959 xscale
->dbr1_used
= 0;
2961 LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
2962 target_name(target
));
2964 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
2965 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
2967 xscale
->vector_catch
= 0x1;
2969 xscale
->trace
.data
= NULL
;
2970 xscale
->trace
.image
= NULL
;
2971 xscale
->trace
.mode
= XSCALE_TRACE_DISABLED
;
2972 xscale
->trace
.buffer_fill
= 0;
2973 xscale
->trace
.fill_counter
= 0;
2975 /* prepare ARMv4/5 specific information */
2976 arm
->arch_info
= xscale
;
2977 arm
->core_type
= ARM_MODE_ANY
;
2978 arm
->read_core_reg
= xscale_read_core_reg
;
2979 arm
->write_core_reg
= xscale_write_core_reg
;
2980 arm
->full_context
= xscale_full_context
;
2982 arm_init_arch_info(target
, arm
);
2984 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
2985 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
2986 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
2987 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
2988 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
2989 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
2990 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
2991 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
2996 static int xscale_target_create(struct target
*target
, Jim_Interp
*interp
)
2998 struct xscale_common
*xscale
;
3000 if (sizeof xscale_debug_handler
> 0x800) {
3001 LOG_ERROR("debug_handler.bin: larger than 2kb");
3005 xscale
= calloc(1, sizeof(*xscale
));
3009 return xscale_init_arch_info(target
, xscale
, target
->tap
);
3012 COMMAND_HANDLER(xscale_handle_debug_handler_command
)
3014 struct target
*target
= NULL
;
3015 struct xscale_common
*xscale
;
3017 uint32_t handler_address
;
3020 return ERROR_COMMAND_SYNTAX_ERROR
;
3022 target
= get_target(CMD_ARGV
[0]);
3023 if (target
== NULL
) {
3024 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3028 xscale
= target_to_xscale(target
);
3029 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3030 if (retval
!= ERROR_OK
)
3033 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], handler_address
);
3035 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3036 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3037 xscale
->handler_address
= handler_address
;
3040 "xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3047 COMMAND_HANDLER(xscale_handle_cache_clean_address_command
)
3049 struct target
*target
= NULL
;
3050 struct xscale_common
*xscale
;
3052 uint32_t cache_clean_address
;
3055 return ERROR_COMMAND_SYNTAX_ERROR
;
3057 target
= get_target(CMD_ARGV
[0]);
3058 if (target
== NULL
) {
3059 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3062 xscale
= target_to_xscale(target
);
3063 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3064 if (retval
!= ERROR_OK
)
3067 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cache_clean_address
);
3069 if (cache_clean_address
& 0xffff)
3070 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3072 xscale
->cache_clean_address
= cache_clean_address
;
3077 COMMAND_HANDLER(xscale_handle_cache_info_command
)
3079 struct target
*target
= get_current_target(CMD_CTX
);
3080 struct xscale_common
*xscale
= target_to_xscale(target
);
3083 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3084 if (retval
!= ERROR_OK
)
3087 return armv4_5_handle_cache_info_command(CMD_CTX
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3090 static int xscale_virt2phys(struct target
*target
,
3091 uint32_t virtual, uint32_t *physical
)
3093 struct xscale_common
*xscale
= target_to_xscale(target
);
3096 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
3097 LOG_ERROR(xscale_not
);
3098 return ERROR_TARGET_INVALID
;
3102 int retval
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
,
3103 virtual, &cb
, &ret
);
3104 if (retval
!= ERROR_OK
)
3110 static int xscale_mmu(struct target
*target
, int *enabled
)
3112 struct xscale_common
*xscale
= target_to_xscale(target
);
3114 if (target
->state
!= TARGET_HALTED
) {
3115 LOG_ERROR("Target not halted");
3116 return ERROR_TARGET_INVALID
;
3118 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3122 COMMAND_HANDLER(xscale_handle_mmu_command
)
3124 struct target
*target
= get_current_target(CMD_CTX
);
3125 struct xscale_common
*xscale
= target_to_xscale(target
);
3128 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3129 if (retval
!= ERROR_OK
)
3132 if (target
->state
!= TARGET_HALTED
) {
3133 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3137 if (CMD_ARGC
>= 1) {
3139 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
3141 xscale_enable_mmu_caches(target
, 1, 0, 0);
3143 xscale_disable_mmu_caches(target
, 1, 0, 0);
3144 xscale
->armv4_5_mmu
.mmu_enabled
= enable
;
3147 command_print(CMD_CTX
, "mmu %s",
3148 (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3153 COMMAND_HANDLER(xscale_handle_idcache_command
)
3155 struct target
*target
= get_current_target(CMD_CTX
);
3156 struct xscale_common
*xscale
= target_to_xscale(target
);
3158 int retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3159 if (retval
!= ERROR_OK
)
3162 if (target
->state
!= TARGET_HALTED
) {
3163 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3167 bool icache
= false;
3168 if (strcmp(CMD_NAME
, "icache") == 0)
3170 if (CMD_ARGC
>= 1) {
3172 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
3174 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= enable
;
3176 xscale_enable_mmu_caches(target
, 0, 0, 1);
3178 xscale_disable_mmu_caches(target
, 0, 0, 1);
3180 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= enable
;
3182 xscale_enable_mmu_caches(target
, 0, 1, 0);
3184 xscale_disable_mmu_caches(target
, 0, 1, 0);
3188 bool enabled
= icache
?
3189 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
:
3190 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
;
3191 const char *msg
= enabled
? "enabled" : "disabled";
3192 command_print(CMD_CTX
, "%s %s", CMD_NAME
, msg
);
3197 static const struct {
3201 { "fiq", DCSR_TF
, },
3202 { "irq", DCSR_TI
, },
3203 { "dabt", DCSR_TD
, },
3204 { "pabt", DCSR_TA
, },
3205 { "swi", DCSR_TS
, },
3206 { "undef", DCSR_TU
, },
3207 { "reset", DCSR_TR
, },
3210 COMMAND_HANDLER(xscale_handle_vector_catch_command
)
3212 struct target
*target
= get_current_target(CMD_CTX
);
3213 struct xscale_common
*xscale
= target_to_xscale(target
);
3215 uint32_t dcsr_value
;
3217 struct reg
*dcsr_reg
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
3219 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3220 if (retval
!= ERROR_OK
)
3223 dcsr_value
= buf_get_u32(dcsr_reg
->value
, 0, 32);
3225 if (CMD_ARGC
== 1) {
3226 if (strcmp(CMD_ARGV
[0], "all") == 0) {
3227 catch = DCSR_TRAP_MASK
;
3229 } else if (strcmp(CMD_ARGV
[0], "none") == 0) {
3234 while (CMD_ARGC
-- > 0) {
3236 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
3237 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
))
3239 catch |= vec_ids
[i
].mask
;
3242 if (i
== ARRAY_SIZE(vec_ids
)) {
3243 LOG_ERROR("No vector '%s'", CMD_ARGV
[CMD_ARGC
]);
3244 return ERROR_COMMAND_SYNTAX_ERROR
;
3247 buf_set_u32(dcsr_reg
->value
, 0, 32,
3248 (buf_get_u32(dcsr_reg
->value
, 0, 32) & ~DCSR_TRAP_MASK
) | catch);
3249 xscale_write_dcsr(target
, -1, -1);
3252 dcsr_value
= buf_get_u32(dcsr_reg
->value
, 0, 32);
3253 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
3254 command_print(CMD_CTX
, "%15s: %s", vec_ids
[i
].name
,
3255 (dcsr_value
& vec_ids
[i
].mask
) ? "catch" : "ignore");
3262 COMMAND_HANDLER(xscale_handle_vector_table_command
)
3264 struct target
*target
= get_current_target(CMD_CTX
);
3265 struct xscale_common
*xscale
= target_to_xscale(target
);
3269 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3270 if (retval
!= ERROR_OK
)
3273 if (CMD_ARGC
== 0) { /* print current settings */
3276 command_print(CMD_CTX
, "active user-set static vectors:");
3277 for (idx
= 1; idx
< 8; idx
++)
3278 if (xscale
->static_low_vectors_set
& (1 << idx
))
3279 command_print(CMD_CTX
,
3280 "low %d: 0x%" PRIx32
,
3282 xscale
->static_low_vectors
[idx
]);
3283 for (idx
= 1; idx
< 8; idx
++)
3284 if (xscale
->static_high_vectors_set
& (1 << idx
))
3285 command_print(CMD_CTX
,
3286 "high %d: 0x%" PRIx32
,
3288 xscale
->static_high_vectors
[idx
]);
3296 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], idx
);
3298 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], vec
);
3300 if (idx
< 1 || idx
>= 8)
3303 if (!err
&& strcmp(CMD_ARGV
[0], "low") == 0) {
3304 xscale
->static_low_vectors_set
|= (1<<idx
);
3305 xscale
->static_low_vectors
[idx
] = vec
;
3306 } else if (!err
&& (strcmp(CMD_ARGV
[0], "high") == 0)) {
3307 xscale
->static_high_vectors_set
|= (1<<idx
);
3308 xscale
->static_high_vectors
[idx
] = vec
;
3314 return ERROR_COMMAND_SYNTAX_ERROR
;
3320 COMMAND_HANDLER(xscale_handle_trace_buffer_command
)
3322 struct target
*target
= get_current_target(CMD_CTX
);
3323 struct xscale_common
*xscale
= target_to_xscale(target
);
3324 uint32_t dcsr_value
;
3327 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3328 if (retval
!= ERROR_OK
)
3331 if (target
->state
!= TARGET_HALTED
) {
3332 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3336 if (CMD_ARGC
>= 1) {
3337 if (strcmp("enable", CMD_ARGV
[0]) == 0)
3338 xscale
->trace
.mode
= XSCALE_TRACE_WRAP
; /* default */
3339 else if (strcmp("disable", CMD_ARGV
[0]) == 0)
3340 xscale
->trace
.mode
= XSCALE_TRACE_DISABLED
;
3342 return ERROR_COMMAND_SYNTAX_ERROR
;
3345 if (CMD_ARGC
>= 2 && xscale
->trace
.mode
!= XSCALE_TRACE_DISABLED
) {
3346 if (strcmp("fill", CMD_ARGV
[1]) == 0) {
3347 int buffcount
= 1; /* default */
3349 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[2], buffcount
);
3350 if (buffcount
< 1) { /* invalid */
3351 command_print(CMD_CTX
, "fill buffer count must be > 0");
3352 xscale
->trace
.mode
= XSCALE_TRACE_DISABLED
;
3353 return ERROR_COMMAND_SYNTAX_ERROR
;
3355 xscale
->trace
.buffer_fill
= buffcount
;
3356 xscale
->trace
.mode
= XSCALE_TRACE_FILL
;
3357 } else if (strcmp("wrap", CMD_ARGV
[1]) == 0)
3358 xscale
->trace
.mode
= XSCALE_TRACE_WRAP
;
3360 xscale
->trace
.mode
= XSCALE_TRACE_DISABLED
;
3361 return ERROR_COMMAND_SYNTAX_ERROR
;
3365 if (xscale
->trace
.mode
!= XSCALE_TRACE_DISABLED
) {
3366 char fill_string
[12];
3367 sprintf(fill_string
, "fill %d", xscale
->trace
.buffer_fill
);
3368 command_print(CMD_CTX
, "trace buffer enabled (%s)",
3369 (xscale
->trace
.mode
== XSCALE_TRACE_FILL
)
3370 ? fill_string
: "wrap");
3372 command_print(CMD_CTX
, "trace buffer disabled");
3374 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3375 if (xscale
->trace
.mode
== XSCALE_TRACE_FILL
)
3376 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3378 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3383 COMMAND_HANDLER(xscale_handle_trace_image_command
)
3385 struct target
*target
= get_current_target(CMD_CTX
);
3386 struct xscale_common
*xscale
= target_to_xscale(target
);
3390 return ERROR_COMMAND_SYNTAX_ERROR
;
3392 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3393 if (retval
!= ERROR_OK
)
3396 if (xscale
->trace
.image
) {
3397 image_close(xscale
->trace
.image
);
3398 free(xscale
->trace
.image
);
3399 command_print(CMD_CTX
, "previously loaded image found and closed");
3402 xscale
->trace
.image
= malloc(sizeof(struct image
));
3403 xscale
->trace
.image
->base_address_set
= 0;
3404 xscale
->trace
.image
->start_address_set
= 0;
3406 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3407 if (CMD_ARGC
>= 2) {
3408 xscale
->trace
.image
->base_address_set
= 1;
3409 COMMAND_PARSE_NUMBER(llong
, CMD_ARGV
[1], xscale
->trace
.image
->base_address
);
3411 xscale
->trace
.image
->base_address_set
= 0;
3413 if (image_open(xscale
->trace
.image
, CMD_ARGV
[0],
3414 (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
) {
3415 free(xscale
->trace
.image
);
3416 xscale
->trace
.image
= NULL
;
3423 COMMAND_HANDLER(xscale_handle_dump_trace_command
)
3425 struct target
*target
= get_current_target(CMD_CTX
);
3426 struct xscale_common
*xscale
= target_to_xscale(target
);
3427 struct xscale_trace_data
*trace_data
;
3428 struct fileio
*file
;
3431 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3432 if (retval
!= ERROR_OK
)
3435 if (target
->state
!= TARGET_HALTED
) {
3436 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3441 return ERROR_COMMAND_SYNTAX_ERROR
;
3443 trace_data
= xscale
->trace
.data
;
3446 command_print(CMD_CTX
, "no trace data collected");
3450 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3453 while (trace_data
) {
3456 fileio_write_u32(file
, trace_data
->chkpt0
);
3457 fileio_write_u32(file
, trace_data
->chkpt1
);
3458 fileio_write_u32(file
, trace_data
->last_instruction
);
3459 fileio_write_u32(file
, trace_data
->depth
);
3461 for (i
= 0; i
< trace_data
->depth
; i
++)
3462 fileio_write_u32(file
, trace_data
->entries
[i
].data
|
3463 ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3465 trace_data
= trace_data
->next
;
3473 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command
)
3475 struct target
*target
= get_current_target(CMD_CTX
);
3476 struct xscale_common
*xscale
= target_to_xscale(target
);
3479 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3480 if (retval
!= ERROR_OK
)
3483 xscale_analyze_trace(target
, CMD_CTX
);
3488 COMMAND_HANDLER(xscale_handle_cp15
)
3490 struct target
*target
= get_current_target(CMD_CTX
);
3491 struct xscale_common
*xscale
= target_to_xscale(target
);
3494 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3495 if (retval
!= ERROR_OK
)
3498 if (target
->state
!= TARGET_HALTED
) {
3499 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3502 uint32_t reg_no
= 0;
3503 struct reg
*reg
= NULL
;
3505 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg_no
);
3506 /*translate from xscale cp15 register no to openocd register*/
3509 reg_no
= XSCALE_MAINID
;
3512 reg_no
= XSCALE_CTRL
;
3515 reg_no
= XSCALE_TTB
;
3518 reg_no
= XSCALE_DAC
;
3521 reg_no
= XSCALE_FSR
;
3524 reg_no
= XSCALE_FAR
;
3527 reg_no
= XSCALE_PID
;
3530 reg_no
= XSCALE_CPACCESS
;
3533 command_print(CMD_CTX
, "invalid register number");
3534 return ERROR_COMMAND_SYNTAX_ERROR
;
3536 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3539 if (CMD_ARGC
== 1) {
3542 /* read cp15 control register */
3543 xscale_get_reg(reg
);
3544 value
= buf_get_u32(reg
->value
, 0, 32);
3545 command_print(CMD_CTX
, "%s (/%i): 0x%" PRIx32
"", reg
->name
, (int)(reg
->size
),
3547 } else if (CMD_ARGC
== 2) {
3549 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
3551 /* send CP write request (command 0x41) */
3552 xscale_send_u32(target
, 0x41);
3554 /* send CP register number */
3555 xscale_send_u32(target
, reg_no
);
3557 /* send CP register value */
3558 xscale_send_u32(target
, value
);
3560 /* execute cpwait to ensure outstanding operations complete */
3561 xscale_send_u32(target
, 0x53);
3563 return ERROR_COMMAND_SYNTAX_ERROR
;
3568 static const struct command_registration xscale_exec_command_handlers
[] = {
3570 .name
= "cache_info",
3571 .handler
= xscale_handle_cache_info_command
,
3572 .mode
= COMMAND_EXEC
,
3573 .help
= "display information about CPU caches",
3577 .handler
= xscale_handle_mmu_command
,
3578 .mode
= COMMAND_EXEC
,
3579 .help
= "enable or disable the MMU",
3580 .usage
= "['enable'|'disable']",
3584 .handler
= xscale_handle_idcache_command
,
3585 .mode
= COMMAND_EXEC
,
3586 .help
= "display ICache state, optionally enabling or "
3588 .usage
= "['enable'|'disable']",
3592 .handler
= xscale_handle_idcache_command
,
3593 .mode
= COMMAND_EXEC
,
3594 .help
= "display DCache state, optionally enabling or "
3596 .usage
= "['enable'|'disable']",
3599 .name
= "vector_catch",
3600 .handler
= xscale_handle_vector_catch_command
,
3601 .mode
= COMMAND_EXEC
,
3602 .help
= "set or display mask of vectors "
3603 "that should trigger debug entry",
3604 .usage
= "['all'|'none'|'fiq'|'irq'|'dabt'|'pabt'|'swi'|'undef'|'reset']",
3607 .name
= "vector_table",
3608 .handler
= xscale_handle_vector_table_command
,
3609 .mode
= COMMAND_EXEC
,
3610 .help
= "set vector table entry in mini-ICache, "
3611 "or display current tables",
3612 .usage
= "[('high'|'low') index code]",
3615 .name
= "trace_buffer",
3616 .handler
= xscale_handle_trace_buffer_command
,
3617 .mode
= COMMAND_EXEC
,
3618 .help
= "display trace buffer status, enable or disable "
3619 "tracing, and optionally reconfigure trace mode",
3620 .usage
= "['enable'|'disable' ['fill' [number]|'wrap']]",
3623 .name
= "dump_trace",
3624 .handler
= xscale_handle_dump_trace_command
,
3625 .mode
= COMMAND_EXEC
,
3626 .help
= "dump content of trace buffer to file",
3627 .usage
= "filename",
3630 .name
= "analyze_trace",
3631 .handler
= xscale_handle_analyze_trace_buffer_command
,
3632 .mode
= COMMAND_EXEC
,
3633 .help
= "analyze content of trace buffer",
3637 .name
= "trace_image",
3638 .handler
= xscale_handle_trace_image_command
,
3639 .mode
= COMMAND_EXEC
,
3640 .help
= "load image from file to address (default 0)",
3641 .usage
= "filename [offset [filetype]]",
3645 .handler
= xscale_handle_cp15
,
3646 .mode
= COMMAND_EXEC
,
3647 .help
= "Read or write coprocessor 15 register.",
3648 .usage
= "register [value]",
3650 COMMAND_REGISTRATION_DONE
3652 static const struct command_registration xscale_any_command_handlers
[] = {
3654 .name
= "debug_handler",
3655 .handler
= xscale_handle_debug_handler_command
,
3656 .mode
= COMMAND_ANY
,
3657 .help
= "Change address used for debug handler.",
3658 .usage
= "<target> <address>",
3661 .name
= "cache_clean_address",
3662 .handler
= xscale_handle_cache_clean_address_command
,
3663 .mode
= COMMAND_ANY
,
3664 .help
= "Change address used for cleaning data cache.",
3668 .chain
= xscale_exec_command_handlers
,
3670 COMMAND_REGISTRATION_DONE
3672 static const struct command_registration xscale_command_handlers
[] = {
3674 .chain
= arm_command_handlers
,
3678 .mode
= COMMAND_ANY
,
3679 .help
= "xscale command group",
3681 .chain
= xscale_any_command_handlers
,
3683 COMMAND_REGISTRATION_DONE
3686 struct target_type xscale_target
= {
3689 .poll
= xscale_poll
,
3690 .arch_state
= xscale_arch_state
,
3692 .halt
= xscale_halt
,
3693 .resume
= xscale_resume
,
3694 .step
= xscale_step
,
3696 .assert_reset
= xscale_assert_reset
,
3697 .deassert_reset
= xscale_deassert_reset
,
3699 /* REVISIT on some cores, allow exporting iwmmxt registers ... */
3700 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3702 .read_memory
= xscale_read_memory
,
3703 .read_phys_memory
= xscale_read_phys_memory
,
3704 .write_memory
= xscale_write_memory
,
3705 .write_phys_memory
= xscale_write_phys_memory
,
3707 .checksum_memory
= arm_checksum_memory
,
3708 .blank_check_memory
= arm_blank_check_memory
,
3710 .run_algorithm
= armv4_5_run_algorithm
,
3712 .add_breakpoint
= xscale_add_breakpoint
,
3713 .remove_breakpoint
= xscale_remove_breakpoint
,
3714 .add_watchpoint
= xscale_add_watchpoint
,
3715 .remove_watchpoint
= xscale_remove_watchpoint
,
3717 .commands
= xscale_command_handlers
,
3718 .target_create
= xscale_target_create
,
3719 .init_target
= xscale_init_target
,
3721 .virt2phys
= xscale_virt2phys
,