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- explicitly disable monitor mode on ARM7/9 targets
[openocd.git] / src / target / xscale.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #include "config.h"
21
22 #include "xscale.h"
23
24 #include "register.h"
25 #include "target.h"
26 #include "armv4_5.h"
27 #include "arm_simulator.h"
28 #include "log.h"
29 #include "jtag.h"
30 #include "binarybuffer.h"
31 #include "time_support.h"
32 #include "breakpoints.h"
33
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include <sys/types.h>
38 #include <sys/stat.h>
39 #include <unistd.h>
40 #include <errno.h>
41
42 /* cli handling */
43 int xscale_register_commands(struct command_context_s *cmd_ctx);
44
45 /* forward declarations */
46 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
47 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
48 int xscale_quit();
49
50 int xscale_arch_state(struct target_s *target, char *buf, int buf_size);
51 enum target_state xscale_poll(target_t *target);
52 int xscale_halt(target_t *target);
53 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
54 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
55 int xscale_debug_entry(target_t *target);
56 int xscale_restore_context(target_t *target);
57
58 int xscale_assert_reset(target_t *target);
59 int xscale_deassert_reset(target_t *target);
60 int xscale_soft_reset_halt(struct target_s *target);
61 int xscale_prepare_reset_halt(struct target_s *target);
62
63 int xscale_set_reg_u32(reg_t *reg, u32 value);
64
65 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
66 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
67
68 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
69 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
70 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
71
72 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
73 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
74 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
75 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
76 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
77 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
78 void xscale_enable_watchpoints(struct target_s *target);
79 void xscale_enable_breakpoints(struct target_s *target);
80
81 target_type_t xscale_target =
82 {
83 .name = "xscale",
84
85 .poll = xscale_poll,
86 .arch_state = xscale_arch_state,
87
88 .halt = xscale_halt,
89 .resume = xscale_resume,
90 .step = xscale_step,
91
92 .assert_reset = xscale_assert_reset,
93 .deassert_reset = xscale_deassert_reset,
94 .soft_reset_halt = xscale_soft_reset_halt,
95 .prepare_reset_halt = xscale_prepare_reset_halt,
96
97 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
98
99 .read_memory = xscale_read_memory,
100 .write_memory = xscale_write_memory,
101 .bulk_write_memory = xscale_bulk_write_memory,
102
103 .run_algorithm = armv4_5_run_algorithm,
104
105 .add_breakpoint = xscale_add_breakpoint,
106 .remove_breakpoint = xscale_remove_breakpoint,
107 .add_watchpoint = xscale_add_watchpoint,
108 .remove_watchpoint = xscale_remove_watchpoint,
109
110 .register_commands = xscale_register_commands,
111 .target_command = xscale_target_command,
112 .init_target = xscale_init_target,
113 .quit = xscale_quit
114 };
115
116 char* xscale_reg_list[] =
117 {
118 "XSCALE_MAINID", /* 0 */
119 "XSCALE_CACHETYPE",
120 "XSCALE_CTRL",
121 "XSCALE_AUXCTRL",
122 "XSCALE_TTB",
123 "XSCALE_DAC",
124 "XSCALE_FSR",
125 "XSCALE_FAR",
126 "XSCALE_PID",
127 "XSCALE_CPACCESS",
128 "XSCALE_IBCR0", /* 10 */
129 "XSCALE_IBCR1",
130 "XSCALE_DBR0",
131 "XSCALE_DBR1",
132 "XSCALE_DBCON",
133 "XSCALE_TBREG",
134 "XSCALE_CHKPT0",
135 "XSCALE_CHKPT1",
136 "XSCALE_DCSR",
137 "XSCALE_TX",
138 "XSCALE_RX", /* 20 */
139 "XSCALE_TXRXCTRL",
140 };
141
142 xscale_reg_t xscale_reg_arch_info[] =
143 {
144 {XSCALE_MAINID, NULL},
145 {XSCALE_CACHETYPE, NULL},
146 {XSCALE_CTRL, NULL},
147 {XSCALE_AUXCTRL, NULL},
148 {XSCALE_TTB, NULL},
149 {XSCALE_DAC, NULL},
150 {XSCALE_FSR, NULL},
151 {XSCALE_FAR, NULL},
152 {XSCALE_PID, NULL},
153 {XSCALE_CPACCESS, NULL},
154 {XSCALE_IBCR0, NULL},
155 {XSCALE_IBCR1, NULL},
156 {XSCALE_DBR0, NULL},
157 {XSCALE_DBR1, NULL},
158 {XSCALE_DBCON, NULL},
159 {XSCALE_TBREG, NULL},
160 {XSCALE_CHKPT0, NULL},
161 {XSCALE_CHKPT1, NULL},
162 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
163 {-1, NULL}, /* TX accessed via JTAG */
164 {-1, NULL}, /* RX accessed via JTAG */
165 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
166 };
167
168 int xscale_reg_arch_type = -1;
169
170 int xscale_get_reg(reg_t *reg);
171 int xscale_set_reg(reg_t *reg, u8 *buf);
172
173 int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
174 {
175 armv4_5_common_t *armv4_5 = target->arch_info;
176 xscale_common_t *xscale = armv4_5->arch_info;
177
178 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
179 {
180 return -1;
181 }
182
183 if (xscale->common_magic != XSCALE_COMMON_MAGIC)
184 {
185 return -1;
186 }
187
188 *armv4_5_p = armv4_5;
189 *xscale_p = xscale;
190
191 return ERROR_OK;
192 }
193
194 int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
195 {
196 jtag_device_t *device = jtag_get_device(chain_pos);
197
198 if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
199 {
200 scan_field_t field;
201
202 field.device = chain_pos;
203 field.num_bits = device->ir_length;
204 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
205 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
206 field.out_mask = NULL;
207 field.in_value = NULL;
208 field.in_check_value = device->expected;
209 field.in_check_mask = device->expected_mask;
210 field.in_handler = NULL;
211 field.in_handler_priv = NULL;
212
213 jtag_add_ir_scan(1, &field, -1);
214
215 free(field.out_value);
216 }
217
218 return ERROR_OK;
219 }
220
221 int xscale_jtag_callback(enum jtag_event event, void *priv)
222 {
223 switch (event)
224 {
225 case JTAG_TRST_ASSERTED:
226 break;
227 case JTAG_TRST_RELEASED:
228 break;
229 case JTAG_SRST_ASSERTED:
230 break;
231 case JTAG_SRST_RELEASED:
232 break;
233 default:
234 WARNING("unhandled JTAG event");
235 }
236
237 return ERROR_OK;
238 }
239
240 int xscale_read_dcsr(target_t *target)
241 {
242 armv4_5_common_t *armv4_5 = target->arch_info;
243 xscale_common_t *xscale = armv4_5->arch_info;
244
245 int retval;
246
247 scan_field_t fields[3];
248 u8 field0 = 0x0;
249 u8 field0_check_value = 0x2;
250 u8 field0_check_mask = 0x7;
251 u8 field2 = 0x0;
252 u8 field2_check_value = 0x0;
253 u8 field2_check_mask = 0x1;
254
255 jtag_add_end_state(TAP_PD);
256 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
257
258 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
259 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
260
261 fields[0].device = xscale->jtag_info.chain_pos;
262 fields[0].num_bits = 3;
263 fields[0].out_value = &field0;
264 fields[0].out_mask = NULL;
265 fields[0].in_value = NULL;
266 fields[0].in_check_value = &field0_check_value;
267 fields[0].in_check_mask = &field0_check_mask;
268 fields[0].in_handler = NULL;
269 fields[0].in_handler_priv = NULL;
270
271 fields[1].device = xscale->jtag_info.chain_pos;
272 fields[1].num_bits = 32;
273 fields[1].out_value = NULL;
274 fields[1].out_mask = NULL;
275 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
276 fields[1].in_handler = NULL;
277 fields[1].in_handler_priv = NULL;
278 fields[1].in_check_value = NULL;
279 fields[1].in_check_mask = NULL;
280
281 fields[2].device = xscale->jtag_info.chain_pos;
282 fields[2].num_bits = 1;
283 fields[2].out_value = &field2;
284 fields[2].out_mask = NULL;
285 fields[2].in_value = NULL;
286 fields[2].in_check_value = &field2_check_value;
287 fields[2].in_check_mask = &field2_check_mask;
288 fields[2].in_handler = NULL;
289 fields[2].in_handler_priv = NULL;
290
291 jtag_add_dr_scan(3, fields, -1);
292
293 if ((retval = jtag_execute_queue()) != ERROR_OK)
294 {
295 ERROR("JTAG error while reading DCSR");
296 exit(-1);
297 }
298
299 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
300 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
301
302 /* write the register with the value we just read
303 * on this second pass, only the first bit of field0 is guaranteed to be 0)
304 */
305 field0_check_mask = 0x1;
306 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
307 fields[1].in_value = NULL;
308
309 jtag_add_end_state(TAP_RTI);
310
311 jtag_add_dr_scan(3, fields, -1);
312
313 return ERROR_OK;
314 }
315
316 int xscale_receive(target_t *target, u32 *buffer, int num_words)
317 {
318 armv4_5_common_t *armv4_5 = target->arch_info;
319 xscale_common_t *xscale = armv4_5->arch_info;
320
321 enum tap_state path[3];
322 scan_field_t fields[3];
323
324 u8 *field0 = malloc(num_words * 1);
325 u8 field0_check_value = 0x2;
326 u8 field0_check_mask = 0x6;
327 u32 *field1 = malloc(num_words * 4);
328 u8 field2_check_value = 0x0;
329 u8 field2_check_mask = 0x1;
330 int words_done = 0;
331 int words_scheduled = 0;
332
333 int i;
334 int retval;
335
336 path[0] = TAP_SDS;
337 path[1] = TAP_CD;
338 path[2] = TAP_SD;
339
340 fields[0].device = xscale->jtag_info.chain_pos;
341 fields[0].num_bits = 3;
342 fields[0].out_value = NULL;
343 fields[0].out_mask = NULL;
344 /* fields[0].in_value = field0; */
345 fields[0].in_check_value = &field0_check_value;
346 fields[0].in_check_mask = &field0_check_mask;
347 fields[0].in_handler = NULL;
348 fields[0].in_handler_priv = NULL;
349
350 fields[1].device = xscale->jtag_info.chain_pos;
351 fields[1].num_bits = 32;
352 fields[1].out_value = NULL;
353 fields[1].out_mask = NULL;
354 fields[1].in_value = NULL;
355 fields[1].in_handler = NULL;
356 fields[1].in_handler_priv = NULL;
357 fields[1].in_check_value = NULL;
358 fields[1].in_check_mask = NULL;
359
360 fields[2].device = xscale->jtag_info.chain_pos;
361 fields[2].num_bits = 1;
362 fields[2].out_value = NULL;
363 fields[2].out_mask = NULL;
364 fields[2].in_value = NULL;
365 fields[2].in_check_value = &field2_check_value;
366 fields[2].in_check_mask = &field2_check_mask;
367 fields[2].in_handler = NULL;
368 fields[2].in_handler_priv = NULL;
369
370 jtag_add_end_state(TAP_RTI);
371 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
372 jtag_add_runtest(1, -1);
373
374 /* repeat until all words have been collected */
375 while (words_done < num_words)
376 {
377 /* schedule reads */
378 words_scheduled = 0;
379 for (i = words_done; i < num_words; i++)
380 {
381 fields[0].in_value = &field0[i];
382 fields[1].in_handler = buf_to_u32_handler;
383 fields[1].in_handler_priv = (u8*)&field1[i];
384
385 jtag_add_pathmove(3, path);
386 jtag_add_dr_scan(3, fields, TAP_RTI);
387 words_scheduled++;
388 }
389
390 if ((retval = jtag_execute_queue()) != ERROR_OK)
391 {
392 ERROR("JTAG error while receiving data from debug handler");
393 exit(-1);
394 }
395
396 /* examine results */
397 for (i = words_done; i < num_words; i++)
398 {
399 if (!(field0[0] & 1))
400 {
401 /* move backwards if necessary */
402 int j;
403 for (j = i; j < num_words - 1; j++)
404 {
405 field0[j] = field0[j+1];
406 field1[j] = field1[j+1];
407 }
408 words_scheduled--;
409 }
410 }
411 words_done += words_scheduled;
412 }
413
414 for (i = 0; i < num_words; i++)
415 *(buffer++) = buf_get_u32((u8*)&field1[i], 0, 32);
416
417 free(field1);
418
419 return ERROR_OK;
420 }
421
422 int xscale_read_tx(target_t *target, int consume)
423 {
424 armv4_5_common_t *armv4_5 = target->arch_info;
425 xscale_common_t *xscale = armv4_5->arch_info;
426 enum tap_state path[3];
427
428 int retval;
429 struct timeval timeout, now;
430
431 scan_field_t fields[3];
432 u8 field0_in = 0x0;
433 u8 field0_check_value = 0x2;
434 u8 field0_check_mask = 0x6;
435 u8 field2_check_value = 0x0;
436 u8 field2_check_mask = 0x1;
437
438 jtag_add_end_state(TAP_RTI);
439
440 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
441
442 path[0] = TAP_SDS;
443 path[1] = TAP_CD;
444 path[2] = TAP_SD;
445
446 fields[0].device = xscale->jtag_info.chain_pos;
447 fields[0].num_bits = 3;
448 fields[0].out_value = NULL;
449 fields[0].out_mask = NULL;
450 fields[0].in_value = &field0_in;
451 fields[0].in_check_value = &field0_check_value;
452 fields[0].in_check_mask = &field0_check_mask;
453 fields[0].in_handler = NULL;
454 fields[0].in_handler_priv = NULL;
455
456 fields[1].device = xscale->jtag_info.chain_pos;
457 fields[1].num_bits = 32;
458 fields[1].out_value = NULL;
459 fields[1].out_mask = NULL;
460 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
461 fields[1].in_handler = NULL;
462 fields[1].in_handler_priv = NULL;
463 fields[1].in_check_value = NULL;
464 fields[1].in_check_mask = NULL;
465
466 fields[2].device = xscale->jtag_info.chain_pos;
467 fields[2].num_bits = 1;
468 fields[2].out_value = NULL;
469 fields[2].out_mask = NULL;
470 fields[2].in_value = NULL;
471 fields[2].in_check_value = &field2_check_value;
472 fields[2].in_check_mask = &field2_check_mask;
473 fields[2].in_handler = NULL;
474 fields[2].in_handler_priv = NULL;
475
476 gettimeofday(&timeout, NULL);
477 timeval_add_time(&timeout, 5, 0);
478
479 do
480 {
481 /* if we want to consume the register content (i.e. clear TX_READY),
482 * we have to go straight from Capture-DR to Shift-DR
483 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
484 */
485 if (consume)
486 jtag_add_pathmove(3, path);
487 else
488 jtag_add_statemove(TAP_PD);
489
490 jtag_add_dr_scan(3, fields, TAP_RTI);
491
492 if ((retval = jtag_execute_queue()) != ERROR_OK)
493 {
494 ERROR("JTAG error while reading TX");
495 exit(-1);
496 }
497
498 gettimeofday(&now, NULL);
499 if ((now.tv_sec > timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))
500 {
501 ERROR("time out reading TX register");
502 return ERROR_TARGET_TIMEOUT;
503 }
504 } while ((!(field0_in & 1)) && consume);
505
506 if (!(field0_in & 1))
507 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
508
509 return ERROR_OK;
510 }
511
512 int xscale_write_rx(target_t *target)
513 {
514 armv4_5_common_t *armv4_5 = target->arch_info;
515 xscale_common_t *xscale = armv4_5->arch_info;
516
517 int retval;
518 struct timeval timeout, now;
519
520 scan_field_t fields[3];
521 u8 field0_out = 0x0;
522 u8 field0_in = 0x0;
523 u8 field0_check_value = 0x2;
524 u8 field0_check_mask = 0x6;
525 u8 field2 = 0x0;
526 u8 field2_check_value = 0x0;
527 u8 field2_check_mask = 0x1;
528
529 jtag_add_end_state(TAP_RTI);
530
531 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
532
533 fields[0].device = xscale->jtag_info.chain_pos;
534 fields[0].num_bits = 3;
535 fields[0].out_value = &field0_out;
536 fields[0].out_mask = NULL;
537 fields[0].in_value = &field0_in;
538 fields[0].in_check_value = &field0_check_value;
539 fields[0].in_check_mask = &field0_check_mask;
540 fields[0].in_handler = NULL;
541 fields[0].in_handler_priv = NULL;
542
543 fields[1].device = xscale->jtag_info.chain_pos;
544 fields[1].num_bits = 32;
545 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
546 fields[1].out_mask = NULL;
547 fields[1].in_value = NULL;
548 fields[1].in_handler = NULL;
549 fields[1].in_handler_priv = NULL;
550 fields[1].in_check_value = NULL;
551 fields[1].in_check_mask = NULL;
552
553 fields[2].device = xscale->jtag_info.chain_pos;
554 fields[2].num_bits = 1;
555 fields[2].out_value = &field2;
556 fields[2].out_mask = NULL;
557 fields[2].in_value = NULL;
558 fields[2].in_check_value = &field2_check_value;
559 fields[2].in_check_mask = &field2_check_mask;
560 fields[2].in_handler = NULL;
561 fields[2].in_handler_priv = NULL;
562
563 gettimeofday(&timeout, NULL);
564 timeval_add_time(&timeout, 5, 0);
565
566 /* poll until rx_read is low */
567 do
568 {
569 DEBUG("polling RX");
570 jtag_add_dr_scan(3, fields, TAP_RTI);
571
572 if ((retval = jtag_execute_queue()) != ERROR_OK)
573 {
574 ERROR("JTAG error while writing RX");
575 exit(-1);
576 }
577
578 gettimeofday(&now, NULL);
579 if ((now.tv_sec > timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))
580 {
581 ERROR("time out writing RX register");
582 return ERROR_TARGET_TIMEOUT;
583 }
584 } while (field0_in & 1);
585
586 /* set rx_valid */
587 field2 = 0x1;
588 jtag_add_dr_scan(3, fields, TAP_RTI);
589
590 if ((retval = jtag_execute_queue()) != ERROR_OK)
591 {
592 ERROR("JTAG error while writing RX");
593 exit(-1);
594 }
595
596 return ERROR_OK;
597 }
598
599 /* send count elements of size byte to the debug handler */
600 int xscale_send(target_t *target, u8 *buffer, int count, int size)
601 {
602 armv4_5_common_t *armv4_5 = target->arch_info;
603 xscale_common_t *xscale = armv4_5->arch_info;
604
605 int retval;
606
607 int done_count = 0;
608 u8 output[4] = {0, 0, 0, 0};
609
610 scan_field_t fields[3];
611 u8 field0_out = 0x0;
612 u8 field0_in = 0x0;
613 u8 field0_check_value = 0x2;
614 u8 field0_check_mask = 0x6;
615 u8 field2 = 0x1;
616 u8 field2_check_value = 0x0;
617 u8 field2_check_mask = 0x1;
618
619 jtag_add_end_state(TAP_RTI);
620
621 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
622
623 fields[0].device = xscale->jtag_info.chain_pos;
624 fields[0].num_bits = 3;
625 fields[0].out_value = &field0_out;
626 fields[0].out_mask = NULL;
627 fields[0].in_value = &field0_in;
628 fields[0].in_check_value = &field0_check_value;
629 fields[0].in_check_mask = &field0_check_mask;
630 fields[0].in_handler = NULL;
631 fields[0].in_handler_priv = NULL;
632
633 fields[1].device = xscale->jtag_info.chain_pos;
634 fields[1].num_bits = 32;
635 fields[1].out_value = output;
636 fields[1].out_mask = NULL;
637 fields[1].in_value = NULL;
638 fields[1].in_handler = NULL;
639 fields[1].in_handler_priv = NULL;
640 fields[1].in_check_value = NULL;
641 fields[1].in_check_mask = NULL;
642
643 fields[2].device = xscale->jtag_info.chain_pos;
644 fields[2].num_bits = 1;
645 fields[2].out_value = &field2;
646 fields[2].out_mask = NULL;
647 fields[2].in_value = NULL;
648 fields[2].in_check_value = &field2_check_value;
649 fields[2].in_check_mask = &field2_check_mask;
650 fields[2].in_handler = NULL;
651 fields[2].in_handler_priv = NULL;
652
653 while (done_count++ < count)
654 {
655 /* extract sized element from target-endian buffer, and put it
656 * into little-endian output buffer
657 */
658 switch (size)
659 {
660 case 4:
661 buf_set_u32(output, 0, 32, target_buffer_get_u32(target, buffer));
662 break;
663 case 2:
664 buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer));
665 break;
666 case 1:
667 output[0] = *buffer;
668 break;
669 default:
670 ERROR("BUG: size neither 4, 2 nor 1");
671 exit(-1);
672 }
673
674 jtag_add_dr_scan(3, fields, TAP_RTI);
675 buffer += size;
676 }
677
678 if ((retval = jtag_execute_queue()) != ERROR_OK)
679 {
680 ERROR("JTAG error while sending data to debug handler");
681 exit(-1);
682 }
683
684 return ERROR_OK;
685 }
686
687 int xscale_send_u32(target_t *target, u32 value)
688 {
689 armv4_5_common_t *armv4_5 = target->arch_info;
690 xscale_common_t *xscale = armv4_5->arch_info;
691
692 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
693 return xscale_write_rx(target);
694 }
695
696 int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
697 {
698 armv4_5_common_t *armv4_5 = target->arch_info;
699 xscale_common_t *xscale = armv4_5->arch_info;
700
701 int retval;
702
703 scan_field_t fields[3];
704 u8 field0 = 0x0;
705 u8 field0_check_value = 0x2;
706 u8 field0_check_mask = 0x7;
707 u8 field2 = 0x0;
708 u8 field2_check_value = 0x0;
709 u8 field2_check_mask = 0x1;
710
711 if (hold_rst != -1)
712 xscale->hold_rst = hold_rst;
713
714 if (ext_dbg_brk != -1)
715 xscale->external_debug_break = ext_dbg_brk;
716
717 jtag_add_end_state(TAP_RTI);
718 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
719
720 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
721 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
722
723 fields[0].device = xscale->jtag_info.chain_pos;
724 fields[0].num_bits = 3;
725 fields[0].out_value = &field0;
726 fields[0].out_mask = NULL;
727 fields[0].in_value = NULL;
728 fields[0].in_check_value = &field0_check_value;
729 fields[0].in_check_mask = &field0_check_mask;
730 fields[0].in_handler = NULL;
731 fields[0].in_handler_priv = NULL;
732
733 fields[1].device = xscale->jtag_info.chain_pos;
734 fields[1].num_bits = 32;
735 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
736 fields[1].out_mask = NULL;
737 fields[1].in_value = NULL;
738 fields[1].in_handler = NULL;
739 fields[1].in_handler_priv = NULL;
740 fields[1].in_check_value = NULL;
741 fields[1].in_check_mask = NULL;
742
743 fields[2].device = xscale->jtag_info.chain_pos;
744 fields[2].num_bits = 1;
745 fields[2].out_value = &field2;
746 fields[2].out_mask = NULL;
747 fields[2].in_value = NULL;
748 fields[2].in_check_value = &field2_check_value;
749 fields[2].in_check_mask = &field2_check_mask;
750 fields[2].in_handler = NULL;
751 fields[2].in_handler_priv = NULL;
752
753 jtag_add_dr_scan(3, fields, -1);
754
755 if ((retval = jtag_execute_queue()) != ERROR_OK)
756 {
757 ERROR("JTAG error while writing DCSR");
758 exit(-1);
759 }
760
761 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
762 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
763
764 return ERROR_OK;
765 }
766
767 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
768 unsigned int parity (unsigned int v)
769 {
770 unsigned int ov = v;
771 v ^= v >> 16;
772 v ^= v >> 8;
773 v ^= v >> 4;
774 v &= 0xf;
775 DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
776 return (0x6996 >> v) & 1;
777 }
778
779 int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
780 {
781 armv4_5_common_t *armv4_5 = target->arch_info;
782 xscale_common_t *xscale = armv4_5->arch_info;
783 u8 packet[4];
784 u8 cmd;
785 int word;
786
787 scan_field_t fields[2];
788
789 DEBUG("loading miniIC at 0x%8.8x", va);
790
791 jtag_add_end_state(TAP_RTI);
792 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
793
794 /* CMD is b010 for Main IC and b011 for Mini IC */
795 if (mini)
796 buf_set_u32(&cmd, 0, 3, 0x3);
797 else
798 buf_set_u32(&cmd, 0, 3, 0x2);
799
800 buf_set_u32(&cmd, 3, 3, 0x0);
801
802 /* virtual address of desired cache line */
803 buf_set_u32(packet, 0, 27, va >> 5);
804
805 fields[0].device = xscale->jtag_info.chain_pos;
806 fields[0].num_bits = 6;
807 fields[0].out_value = &cmd;
808 fields[0].out_mask = NULL;
809 fields[0].in_value = NULL;
810 fields[0].in_check_value = NULL;
811 fields[0].in_check_mask = NULL;
812 fields[0].in_handler = NULL;
813 fields[0].in_handler_priv = NULL;
814
815 fields[1].device = xscale->jtag_info.chain_pos;
816 fields[1].num_bits = 27;
817 fields[1].out_value = packet;
818 fields[1].out_mask = NULL;
819 fields[1].in_value = NULL;
820 fields[1].in_check_value = NULL;
821 fields[1].in_check_mask = NULL;
822 fields[1].in_handler = NULL;
823 fields[1].in_handler_priv = NULL;
824
825 jtag_add_dr_scan(2, fields, -1);
826
827 fields[0].num_bits = 32;
828 fields[0].out_value = packet;
829
830 fields[1].num_bits = 1;
831 fields[1].out_value = &cmd;
832
833 for (word = 0; word < 8; word++)
834 {
835 buf_set_u32(packet, 0, 32, buffer[word]);
836 cmd = parity(*((u32*)packet));
837 jtag_add_dr_scan(2, fields, -1);
838 }
839
840 jtag_execute_queue();
841
842 return ERROR_OK;
843 }
844
845 int xscale_invalidate_ic_line(target_t *target, u32 va)
846 {
847 armv4_5_common_t *armv4_5 = target->arch_info;
848 xscale_common_t *xscale = armv4_5->arch_info;
849 u8 packet[4];
850 u8 cmd;
851
852 scan_field_t fields[2];
853
854 jtag_add_end_state(TAP_RTI);
855 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
856
857 /* CMD for invalidate IC line b000, bits [6:4] b000 */
858 buf_set_u32(&cmd, 0, 6, 0x0);
859
860 /* virtual address of desired cache line */
861 buf_set_u32(packet, 0, 27, va >> 5);
862
863 fields[0].device = xscale->jtag_info.chain_pos;
864 fields[0].num_bits = 6;
865 fields[0].out_value = &cmd;
866 fields[0].out_mask = NULL;
867 fields[0].in_value = NULL;
868 fields[0].in_check_value = NULL;
869 fields[0].in_check_mask = NULL;
870 fields[0].in_handler = NULL;
871 fields[0].in_handler_priv = NULL;
872
873 fields[1].device = xscale->jtag_info.chain_pos;
874 fields[1].num_bits = 27;
875 fields[1].out_value = packet;
876 fields[1].out_mask = NULL;
877 fields[1].in_value = NULL;
878 fields[1].in_check_value = NULL;
879 fields[1].in_check_mask = NULL;
880 fields[1].in_handler = NULL;
881 fields[1].in_handler_priv = NULL;
882
883 jtag_add_dr_scan(2, fields, -1);
884
885 return ERROR_OK;
886 }
887
888 int xscale_update_vectors(target_t *target)
889 {
890 armv4_5_common_t *armv4_5 = target->arch_info;
891 xscale_common_t *xscale = armv4_5->arch_info;
892 int i;
893
894 u32 low_reset_branch, high_reset_branch;
895
896 for (i = 1; i < 8; i++)
897 {
898 /* if there's a static vector specified for this exception, override */
899 if (xscale->static_high_vectors_set & (1 << i))
900 {
901 xscale->high_vectors[i] = xscale->static_high_vectors[i];
902 }
903 else
904 {
905 if (target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]) != ERROR_OK)
906 {
907 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
908 }
909 }
910 }
911
912 for (i = 1; i < 8; i++)
913 {
914 if (xscale->static_low_vectors_set & (1 << i))
915 {
916 xscale->low_vectors[i] = xscale->static_low_vectors[i];
917 }
918 else
919 {
920 if (target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]) != ERROR_OK)
921 {
922 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
923 }
924 }
925 }
926
927 /* calculate branches to debug handler */
928 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
929 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
930
931 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
932 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
933
934 /* invalidate and load exception vectors in mini i-cache */
935 xscale_invalidate_ic_line(target, 0x0);
936 xscale_invalidate_ic_line(target, 0xffff0000);
937
938 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
939 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
940
941 return ERROR_OK;
942 }
943
944 int xscale_arch_state(struct target_s *target, char *buf, int buf_size)
945 {
946 armv4_5_common_t *armv4_5 = target->arch_info;
947 xscale_common_t *xscale = armv4_5->arch_info;
948
949 char *state[] =
950 {
951 "disabled", "enabled"
952 };
953
954 char *arch_dbg_reason[] =
955 {
956 "", "\n(processor reset)", "\n(trace buffer full)"
957 };
958
959 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
960 {
961 ERROR("BUG: called for a non-ARMv4/5 target");
962 exit(-1);
963 }
964
965 snprintf(buf, buf_size,
966 "target halted in %s state due to %s, current mode: %s\n"
967 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
968 "MMU: %s, D-Cache: %s, I-Cache: %s"
969 "%s",
970 armv4_5_state_strings[armv4_5->core_state],
971 target_debug_reason_strings[target->debug_reason],
972 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
973 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
974 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
975 state[xscale->armv4_5_mmu.mmu_enabled],
976 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
977 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
978 arch_dbg_reason[xscale->arch_debug_reason]);
979
980 return ERROR_OK;
981 }
982
983 enum target_state xscale_poll(target_t *target)
984 {
985 int retval;
986 armv4_5_common_t *armv4_5 = target->arch_info;
987 xscale_common_t *xscale = armv4_5->arch_info;
988
989 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
990 {
991 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
992 {
993 /* there's data to read from the tx register, we entered debug state */
994 xscale->handler_running = 1;
995
996 /* process debug entry, fetching current mode regs */
997 if ((retval = xscale_debug_entry(target)) != ERROR_OK)
998 return retval;
999
1000 /* if target was running, signal that we halted
1001 * otherwise we reentered from debug execution */
1002 if (target->state == TARGET_RUNNING)
1003 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1004 else
1005 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
1006
1007 target->state = TARGET_HALTED;
1008 }
1009 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1010 {
1011 ERROR("error while polling TX register");
1012 exit(-1);
1013 }
1014 }
1015
1016 return target->state;
1017 }
1018
1019 int xscale_debug_entry(target_t *target)
1020 {
1021 armv4_5_common_t *armv4_5 = target->arch_info;
1022 xscale_common_t *xscale = armv4_5->arch_info;
1023 u32 pc;
1024 u32 *buffer = malloc(4 * 10);
1025 int i;
1026
1027 u32 moe;
1028
1029 /* clear external dbg break (will be written on next DCSR read) */
1030 xscale->external_debug_break = 0;
1031 xscale_read_dcsr(target);
1032
1033 /* get r0, pc, r1 to r7 and cpsr */
1034 xscale_receive(target, buffer, 10);
1035
1036 /* move r0 from buffer to register cache */
1037 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
1038 armv4_5->core_cache->reg_list[15].dirty = 1;
1039 armv4_5->core_cache->reg_list[15].valid = 1;
1040 DEBUG("r0: 0x%8.8x", buffer[0]);
1041
1042 /* move pc from buffer to register cache */
1043 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
1044 armv4_5->core_cache->reg_list[15].dirty = 1;
1045 armv4_5->core_cache->reg_list[15].valid = 1;
1046 DEBUG("pc: 0x%8.8x", buffer[1]);
1047
1048 /* move data from buffer to register cache */
1049 for (i = 1; i <= 7; i++)
1050 {
1051 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
1052 armv4_5->core_cache->reg_list[i].dirty = 1;
1053 armv4_5->core_cache->reg_list[i].valid = 1;
1054 DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]);
1055 }
1056
1057 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
1058 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1059 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1060 DEBUG("cpsr: 0x%8.8x", buffer[9]);
1061
1062 armv4_5->core_mode = buffer[9] & 0x1f;
1063 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1064 {
1065 target->state = TARGET_UNKNOWN;
1066 ERROR("cpsr contains invalid mode value - communication failure");
1067 return ERROR_TARGET_FAILURE;
1068 }
1069 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1070
1071 if (buffer[9] & 0x20)
1072 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1073 else
1074 armv4_5->core_state = ARMV4_5_STATE_ARM;
1075
1076 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1077 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1078 {
1079 xscale_receive(target, buffer, 8);
1080 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1081 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1082 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1083 }
1084 else
1085 {
1086 /* r8 to r14, but no spsr */
1087 xscale_receive(target, buffer, 7);
1088 }
1089
1090 /* move data from buffer to register cache */
1091 for (i = 8; i <= 14; i++)
1092 {
1093 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
1094 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1095 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1096 }
1097
1098 /* examine debug reason */
1099 xscale_read_dcsr(target);
1100 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
1101
1102 /* stored PC (for calculating fixup) */
1103 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1104
1105 switch (moe)
1106 {
1107 case 0x0: /* Processor reset */
1108 target->debug_reason = DBG_REASON_DBGRQ;
1109 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
1110 pc -= 4;
1111 break;
1112 case 0x1: /* Instruction breakpoint hit */
1113 target->debug_reason = DBG_REASON_BREAKPOINT;
1114 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1115 pc -= 4;
1116 break;
1117 case 0x2: /* Data breakpoint hit */
1118 target->debug_reason = DBG_REASON_WATCHPOINT;
1119 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1120 pc -= 4;
1121 break;
1122 case 0x3: /* BKPT instruction executed */
1123 target->debug_reason = DBG_REASON_BREAKPOINT;
1124 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1125 pc -= 4;
1126 break;
1127 case 0x4: /* Ext. debug event */
1128 target->debug_reason = DBG_REASON_DBGRQ;
1129 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1130 pc -= 4;
1131 break;
1132 case 0x5: /* Vector trap occured */
1133 target->debug_reason = DBG_REASON_BREAKPOINT;
1134 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1135 pc -= 4;
1136 break;
1137 case 0x6: /* Trace buffer full break */
1138 target->debug_reason = DBG_REASON_DBGRQ;
1139 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1140 pc -= 4;
1141 break;
1142 case 0x7: /* Reserved */
1143 default:
1144 ERROR("Method of Entry is 'Reserved'");
1145 exit(-1);
1146 break;
1147 }
1148
1149 /* apply PC fixup */
1150 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1151
1152 /* on the first debug entry, identify cache type */
1153 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1154 {
1155 u32 cache_type_reg;
1156
1157 /* read cp15 cache type register */
1158 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1159 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1160
1161 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1162 }
1163
1164 /* examine MMU and Cache settings */
1165 /* read cp15 control register */
1166 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1167 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1168 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1169 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1170 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1171
1172 return ERROR_OK;
1173 }
1174
1175 int xscale_halt(target_t *target)
1176 {
1177 armv4_5_common_t *armv4_5 = target->arch_info;
1178 xscale_common_t *xscale = armv4_5->arch_info;
1179
1180 DEBUG("target->state: %s", target_state_strings[target->state]);
1181
1182 if (target->state == TARGET_HALTED)
1183 {
1184 WARNING("target was already halted");
1185 return ERROR_TARGET_ALREADY_HALTED;
1186 }
1187 else if (target->state == TARGET_UNKNOWN)
1188 {
1189 /* this must not happen for a xscale target */
1190 ERROR("target was in unknown state when halt was requested");
1191 exit(-1);
1192 }
1193 else if (target->state == TARGET_RESET)
1194 {
1195 DEBUG("target->state == TARGET_RESET");
1196
1197 /* clear TRST */
1198 jtag_add_reset(0, -1);
1199 }
1200 else
1201 {
1202 /* assert external dbg break */
1203 xscale->external_debug_break = 1;
1204 xscale_read_dcsr(target);
1205
1206 target->debug_reason = DBG_REASON_DBGRQ;
1207 }
1208
1209 return ERROR_OK;
1210 }
1211
1212 int xscale_enable_single_step(struct target_s *target, u32 next_pc)
1213 {
1214 armv4_5_common_t *armv4_5 = target->arch_info;
1215 xscale_common_t *xscale= armv4_5->arch_info;
1216 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1217
1218 if (xscale->ibcr0_used)
1219 {
1220 breakpoint_t *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1221
1222 if (ibcr0_bp)
1223 {
1224 xscale_unset_breakpoint(target, ibcr0_bp);
1225 }
1226 else
1227 {
1228 ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1229 exit(-1);
1230 }
1231 }
1232
1233 xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1234
1235 return ERROR_OK;
1236 }
1237
1238 int xscale_disable_single_step(struct target_s *target)
1239 {
1240 armv4_5_common_t *armv4_5 = target->arch_info;
1241 xscale_common_t *xscale= armv4_5->arch_info;
1242 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1243
1244 xscale_set_reg_u32(ibcr0, 0x0);
1245
1246 return ERROR_OK;
1247 }
1248
1249 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1250 {
1251 armv4_5_common_t *armv4_5 = target->arch_info;
1252 xscale_common_t *xscale= armv4_5->arch_info;
1253 breakpoint_t *breakpoint = target->breakpoints;
1254
1255 u32 current_pc;
1256
1257 int retval;
1258 int i;
1259
1260 DEBUG("-");
1261
1262 if (target->state != TARGET_HALTED)
1263 {
1264 WARNING("target not halted");
1265 return ERROR_TARGET_NOT_HALTED;
1266 }
1267
1268 if (!debug_execution)
1269 {
1270 target_free_all_working_areas(target);
1271 }
1272
1273 /* update vector tables */
1274 xscale_update_vectors(target);
1275
1276 /* current = 1: continue on current pc, otherwise continue at <address> */
1277 if (!current)
1278 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1279
1280 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1281
1282 /* if we're at the reset vector, we have to simulate the branch */
1283 if (current_pc == 0x0)
1284 {
1285 arm_simulate_step(target, NULL);
1286 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1287 }
1288
1289 /* the front-end may request us not to handle breakpoints */
1290 if (handle_breakpoints)
1291 {
1292 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1293 {
1294 u32 next_pc;
1295
1296 /* there's a breakpoint at the current PC, we have to step over it */
1297 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1298 xscale_unset_breakpoint(target, breakpoint);
1299
1300 /* calculate PC of next instruction */
1301 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1302 {
1303 u32 current_opcode;
1304 target_read_u32(target, current_pc, &current_opcode);
1305 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1306 }
1307
1308 DEBUG("enable single-step");
1309 xscale_enable_single_step(target, next_pc);
1310
1311 /* restore banked registers */
1312 xscale_restore_context(target);
1313
1314 /* send resume request (command 0x30 or 0x31)
1315 * clean the trace buffer if it is to be enabled (0x62) */
1316 if (xscale->trace_buffer_enabled)
1317 {
1318 xscale_send_u32(target, 0x62);
1319 xscale_send_u32(target, 0x31);
1320 }
1321 else
1322 xscale_send_u32(target, 0x30);
1323
1324 /* send CPSR */
1325 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1326 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1327
1328 for (i = 7; i >= 0; i--)
1329 {
1330 /* send register */
1331 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1332 DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1333 }
1334
1335 /* send PC */
1336 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1337 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1338
1339 /* wait for and process debug entry */
1340 xscale_debug_entry(target);
1341
1342 DEBUG("disable single-step");
1343 xscale_disable_single_step(target);
1344
1345 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1346 xscale_set_breakpoint(target, breakpoint);
1347 }
1348 }
1349
1350 /* enable any pending breakpoints and watchpoints */
1351 xscale_enable_breakpoints(target);
1352 xscale_enable_watchpoints(target);
1353
1354 /* restore banked registers */
1355 xscale_restore_context(target);
1356
1357 /* send resume request (command 0x30 or 0x31)
1358 * clean the trace buffer if it is to be enabled (0x62) */
1359 if (xscale->trace_buffer_enabled)
1360 {
1361 xscale_send_u32(target, 0x62);
1362 xscale_send_u32(target, 0x31);
1363 }
1364 else
1365 xscale_send_u32(target, 0x30);
1366
1367 /* send CPSR */
1368 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1369 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1370
1371 for (i = 7; i >= 0; i--)
1372 {
1373 /* send register */
1374 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1375 DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1376 }
1377
1378 /* send PC */
1379 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1380 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1381
1382 target->debug_reason = DBG_REASON_NOTHALTED;
1383
1384 if (!debug_execution)
1385 {
1386 /* registers are now invalid */
1387 armv4_5_invalidate_core_regs(target);
1388 target->state = TARGET_RUNNING;
1389 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1390 }
1391 else
1392 {
1393 target->state = TARGET_DEBUG_RUNNING;
1394 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1395 }
1396
1397 DEBUG("target resumed");
1398
1399 xscale->handler_running = 1;
1400
1401 return ERROR_OK;
1402 }
1403
1404 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1405 {
1406 armv4_5_common_t *armv4_5 = target->arch_info;
1407 xscale_common_t *xscale = armv4_5->arch_info;
1408 breakpoint_t *breakpoint = target->breakpoints;
1409
1410 u32 current_pc, next_pc;
1411 int i;
1412 int retval;
1413
1414 if (target->state != TARGET_HALTED)
1415 {
1416 WARNING("target not halted");
1417 return ERROR_TARGET_NOT_HALTED;
1418 }
1419
1420 /* current = 1: continue on current pc, otherwise continue at <address> */
1421 if (!current)
1422 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1423
1424 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1425
1426 /* if we're at the reset vector, we have to simulate the step */
1427 if (current_pc == 0x0)
1428 {
1429 arm_simulate_step(target, NULL);
1430 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1431
1432 target->debug_reason = DBG_REASON_SINGLESTEP;
1433 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1434
1435 return ERROR_OK;
1436 }
1437
1438 /* the front-end may request us not to handle breakpoints */
1439 if (handle_breakpoints)
1440 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1441 {
1442 xscale_unset_breakpoint(target, breakpoint);
1443 }
1444
1445 target->debug_reason = DBG_REASON_SINGLESTEP;
1446
1447 /* calculate PC of next instruction */
1448 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1449 {
1450 u32 current_opcode;
1451 target_read_u32(target, current_pc, &current_opcode);
1452 ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1453 }
1454
1455 DEBUG("enable single-step");
1456 xscale_enable_single_step(target, next_pc);
1457
1458 /* restore banked registers */
1459 xscale_restore_context(target);
1460
1461 /* send resume request (command 0x30 or 0x31)
1462 * clean the trace buffer if it is to be enabled (0x62) */
1463 if (xscale->trace_buffer_enabled)
1464 {
1465 xscale_send_u32(target, 0x62);
1466 xscale_send_u32(target, 0x31);
1467 }
1468 else
1469 xscale_send_u32(target, 0x30);
1470
1471 /* send CPSR */
1472 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1473 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1474
1475 for (i = 7; i >= 0; i--)
1476 {
1477 /* send register */
1478 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1479 DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1480 }
1481
1482 /* send PC */
1483 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1484 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1485
1486 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1487
1488 /* registers are now invalid */
1489 armv4_5_invalidate_core_regs(target);
1490
1491 /* wait for and process debug entry */
1492 xscale_debug_entry(target);
1493
1494 DEBUG("disable single-step");
1495 xscale_disable_single_step(target);
1496
1497 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1498
1499 if (breakpoint)
1500 {
1501 xscale_set_breakpoint(target, breakpoint);
1502 }
1503
1504 DEBUG("target stepped");
1505
1506 return ERROR_OK;
1507
1508 }
1509
1510 int xscale_assert_reset(target_t *target)
1511 {
1512 armv4_5_common_t *armv4_5 = target->arch_info;
1513 xscale_common_t *xscale = armv4_5->arch_info;
1514
1515 DEBUG("target->state: %s", target_state_strings[target->state]);
1516
1517 /* if the handler isn't installed yet, we have to assert TRST, too */
1518 if (!xscale->handler_installed)
1519 {
1520 jtag_add_reset(1, 1);
1521 }
1522 else
1523 jtag_add_reset(-1, 1);
1524
1525 /* sleep 1ms, to be sure we fulfill any requirements */
1526 jtag_add_sleep(1000);
1527
1528 target->state = TARGET_RESET;
1529
1530 return ERROR_OK;
1531
1532 }
1533
1534 int xscale_deassert_reset(target_t *target)
1535 {
1536 armv4_5_common_t *armv4_5 = target->arch_info;
1537 xscale_common_t *xscale = armv4_5->arch_info;
1538
1539 FILE *binary;
1540 u32 address;
1541 struct stat binary_stat;
1542 u32 binary_size;
1543
1544 u32 buffer[8];
1545 u32 buf_cnt;
1546 int i;
1547
1548 breakpoint_t *breakpoint = target->breakpoints;
1549
1550 xscale->ibcr_available = 2;
1551 xscale->ibcr0_used = 0;
1552 xscale->ibcr1_used = 0;
1553
1554 xscale->dbr_available = 2;
1555 xscale->dbr0_used = 0;
1556 xscale->dbr1_used = 0;
1557
1558 /* mark all hardware breakpoints as unset */
1559 while (breakpoint)
1560 {
1561 if (breakpoint->type == BKPT_HARD)
1562 {
1563 breakpoint->set = 0;
1564 }
1565 breakpoint = breakpoint->next;
1566 }
1567
1568 if (!xscale->handler_installed)
1569 {
1570 /* release TRST */
1571 jtag_add_reset(0, -1);
1572 jtag_add_sleep(100000);
1573
1574 /* set Hold reset, Halt mode and Trap Reset */
1575 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1576 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1577 xscale_write_dcsr(target, 1, 0);
1578 jtag_add_runtest(100, TAP_RTI);
1579 jtag_execute_queue();
1580
1581 /* release SRST */
1582 jtag_add_reset(0, 0);
1583 /* wait 150ms; 100ms were not enough */
1584 jtag_add_sleep(150000);
1585
1586 jtag_add_runtest(2030, TAP_RTI);
1587 jtag_execute_queue();
1588
1589 xscale_write_dcsr(target, 1, 0);
1590 jtag_execute_queue();
1591
1592 /* TODO: load debug handler */
1593 if (stat("target/xscale/debug_handler.bin", &binary_stat) == -1)
1594 {
1595 ERROR("couldn't stat() target/xscale/debug_handler.bin: %s", strerror(errno));
1596 return ERROR_OK;
1597 }
1598
1599 if (!(binary = fopen("target/xscale/debug_handler.bin", "r")))
1600 {
1601 ERROR("couldn't open target/xscale/debug_handler.bin: %s", strerror(errno));
1602 return ERROR_OK;
1603 }
1604
1605 if ((binary_size = binary_stat.st_size) % 4)
1606 {
1607 ERROR("debug_handler.bin: size not a multiple of 4");
1608 exit(-1);
1609 }
1610
1611 if (binary_size > 0x800)
1612 {
1613 ERROR("debug_handler.bin: larger than 2kb");
1614 exit(-1);
1615 }
1616
1617 binary_size = CEIL(binary_size, 32) * 32;
1618
1619 address = xscale->handler_address;
1620 while (binary_size > 0)
1621 {
1622 buf_cnt = fread(buffer, 4, 8, binary);
1623
1624 for (i = 0; i < buf_cnt; i++)
1625 {
1626 /* convert LE buffer to host-endian u32 */
1627 buffer[i] = buf_get_u32((u8*)(&buffer[i]), 0, 32);
1628 }
1629
1630 if (buf_cnt < 8)
1631 {
1632 for (; buf_cnt < 8; buf_cnt++)
1633 {
1634 buffer[buf_cnt] = 0xe1a08008;
1635 }
1636 }
1637
1638 /* only load addresses other than the reset vectors */
1639 if ((address % 0x400) != 0x0)
1640 {
1641 xscale_load_ic(target, 1, address, buffer);
1642 }
1643
1644 address += buf_cnt * 4;
1645 binary_size -= buf_cnt * 4;
1646 };
1647
1648 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
1649 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
1650
1651 jtag_add_runtest(30, TAP_RTI);
1652
1653 /* let the target run (should enter debug handler) */
1654 xscale_write_dcsr(target, 0, 0);
1655 target->state = TARGET_RUNNING;
1656
1657 if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT))
1658 {
1659 jtag_add_sleep(10000);
1660
1661 /* we should have entered debug now */
1662 xscale_debug_entry(target);
1663 target->state = TARGET_HALTED;
1664
1665 /* the PC is now at 0x0 */
1666 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1667 }
1668 }
1669 else
1670 {
1671 jtag_add_reset(0, 0);
1672 }
1673
1674
1675 return ERROR_OK;
1676 }
1677
1678 int xscale_soft_reset_halt(struct target_s *target)
1679 {
1680
1681 return ERROR_OK;
1682 }
1683
1684 int xscale_prepare_reset_halt(struct target_s *target)
1685 {
1686 /* nothing to be done for reset_halt on XScale targets */
1687 return ERROR_OK;
1688 }
1689
1690 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1691 {
1692
1693 return ERROR_OK;
1694 }
1695
1696 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1697 {
1698
1699 return ERROR_OK;
1700 }
1701
1702 int xscale_full_context(target_t *target)
1703 {
1704 armv4_5_common_t *armv4_5 = target->arch_info;
1705
1706 u32 *buffer;
1707
1708 int i, j;
1709
1710 DEBUG("-");
1711
1712 if (target->state != TARGET_HALTED)
1713 {
1714 WARNING("target not halted");
1715 return ERROR_TARGET_NOT_HALTED;
1716 }
1717
1718 buffer = malloc(4 * 8);
1719
1720 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1721 * we can't enter User mode on an XScale (unpredictable),
1722 * but User shares registers with SYS
1723 */
1724 for(i = 1; i < 7; i++)
1725 {
1726 int valid = 1;
1727
1728 /* check if there are invalid registers in the current mode
1729 */
1730 for (j = 0; j <= 16; j++)
1731 {
1732 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1733 valid = 0;
1734 }
1735
1736 if (!valid)
1737 {
1738 u32 tmp_cpsr;
1739
1740 /* request banked registers */
1741 xscale_send_u32(target, 0x0);
1742
1743 tmp_cpsr = 0x0;
1744 tmp_cpsr |= armv4_5_number_to_mode(i);
1745 tmp_cpsr |= 0xc0; /* I/F bits */
1746
1747 /* send CPSR for desired mode */
1748 xscale_send_u32(target, tmp_cpsr);
1749
1750 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1751 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1752 {
1753 xscale_receive(target, buffer, 8);
1754 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1755 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1756 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1757 }
1758 else
1759 {
1760 xscale_receive(target, buffer, 7);
1761 }
1762
1763 /* move data from buffer to register cache */
1764 for (j = 8; j <= 14; j++)
1765 {
1766 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
1767 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1768 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1769 }
1770 }
1771 }
1772
1773 free(buffer);
1774
1775 return ERROR_OK;
1776 }
1777
1778 int xscale_restore_context(target_t *target)
1779 {
1780 armv4_5_common_t *armv4_5 = target->arch_info;
1781
1782 int i, j;
1783
1784 DEBUG("-");
1785
1786 if (target->state != TARGET_HALTED)
1787 {
1788 WARNING("target not halted");
1789 return ERROR_TARGET_NOT_HALTED;
1790 }
1791
1792 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1793 * we can't enter User mode on an XScale (unpredictable),
1794 * but User shares registers with SYS
1795 */
1796 for(i = 1; i < 7; i++)
1797 {
1798 int dirty = 0;
1799
1800 /* check if there are invalid registers in the current mode
1801 */
1802 for (j = 8; j <= 14; j++)
1803 {
1804 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
1805 dirty = 1;
1806 }
1807
1808 /* if not USR/SYS, check if the SPSR needs to be written */
1809 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1810 {
1811 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
1812 dirty = 1;
1813 }
1814
1815 if (dirty)
1816 {
1817 u32 tmp_cpsr;
1818
1819 /* send banked registers */
1820 xscale_send_u32(target, 0x1);
1821
1822 tmp_cpsr = 0x0;
1823 tmp_cpsr |= armv4_5_number_to_mode(i);
1824 tmp_cpsr |= 0xc0; /* I/F bits */
1825
1826 /* send CPSR for desired mode */
1827 xscale_send_u32(target, tmp_cpsr);
1828
1829 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1830 for (j = 8; j <= 14; j++)
1831 {
1832 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
1833 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1834 }
1835
1836 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1837 {
1838 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
1839 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1840 }
1841 }
1842 }
1843
1844 return ERROR_OK;
1845 }
1846
1847 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1848 {
1849 armv4_5_common_t *armv4_5 = target->arch_info;
1850 xscale_common_t *xscale = armv4_5->arch_info;
1851 u32 *buf32;
1852 int i;
1853
1854 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1855
1856 if (target->state != TARGET_HALTED)
1857 {
1858 WARNING("target not halted");
1859 return ERROR_TARGET_NOT_HALTED;
1860 }
1861
1862 /* sanitize arguments */
1863 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1864 return ERROR_INVALID_ARGUMENTS;
1865
1866 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1867 return ERROR_TARGET_UNALIGNED_ACCESS;
1868
1869 /* send memory read request (command 0x1n, n: access size) */
1870 xscale_send_u32(target, 0x10 | size);
1871
1872 /* send base address for read request */
1873 xscale_send_u32(target, address);
1874
1875 /* send number of requested data words */
1876 xscale_send_u32(target, count);
1877
1878 /* receive data from target (count times 32-bit words in host endianness) */
1879 buf32 = malloc(4 * count);
1880 xscale_receive(target, buf32, count);
1881
1882 /* extract data from host-endian buffer into byte stream */
1883 for (i = 0; i < count; i++)
1884 {
1885 switch (size)
1886 {
1887 case 4:
1888 target_buffer_set_u32(target, buffer, buf32[i]);
1889 buffer += 4;
1890 break;
1891 case 2:
1892 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1893 buffer += 2;
1894 break;
1895 case 1:
1896 *buffer++ = buf32[i] & 0xff;
1897 break;
1898 default:
1899 ERROR("should never get here");
1900 exit(-1);
1901 }
1902 }
1903
1904 free(buf32);
1905
1906 /* examine DCSR, to see if Sticky Abort (SA) got set */
1907 xscale_read_dcsr(target);
1908 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1909 {
1910 /* clear SA bit */
1911 xscale_send_u32(target, 0x60);
1912
1913 return ERROR_TARGET_DATA_ABORT;
1914 }
1915
1916 return ERROR_OK;
1917 }
1918
1919 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1920 {
1921 armv4_5_common_t *armv4_5 = target->arch_info;
1922 xscale_common_t *xscale = armv4_5->arch_info;
1923
1924 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1925
1926 if (target->state != TARGET_HALTED)
1927 {
1928 WARNING("target not halted");
1929 return ERROR_TARGET_NOT_HALTED;
1930 }
1931
1932 /* sanitize arguments */
1933 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1934 return ERROR_INVALID_ARGUMENTS;
1935
1936 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1937 return ERROR_TARGET_UNALIGNED_ACCESS;
1938
1939 /* send memory write request (command 0x2n, n: access size) */
1940 xscale_send_u32(target, 0x20 | size);
1941
1942 /* send base address for read request */
1943 xscale_send_u32(target, address);
1944
1945 /* send number of requested data words to be written*/
1946 xscale_send_u32(target, count);
1947
1948 /* extract data from host-endian buffer into byte stream */
1949 #if 0
1950 for (i = 0; i < count; i++)
1951 {
1952 switch (size)
1953 {
1954 case 4:
1955 value = target_buffer_get_u32(target, buffer);
1956 xscale_send_u32(target, value);
1957 buffer += 4;
1958 break;
1959 case 2:
1960 value = target_buffer_get_u16(target, buffer);
1961 xscale_send_u32(target, value);
1962 buffer += 2;
1963 break;
1964 case 1:
1965 value = *buffer;
1966 xscale_send_u32(target, value);
1967 buffer += 1;
1968 break;
1969 default:
1970 ERROR("should never get here");
1971 exit(-1);
1972 }
1973 }
1974 #endif
1975 xscale_send(target, buffer, count, size);
1976
1977 /* examine DCSR, to see if Sticky Abort (SA) got set */
1978 xscale_read_dcsr(target);
1979 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1980 {
1981 /* clear SA bit */
1982 xscale_send_u32(target, 0x60);
1983
1984 return ERROR_TARGET_DATA_ABORT;
1985 }
1986
1987 return ERROR_OK;
1988 }
1989
1990 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1991 {
1992 xscale_write_memory(target, address, 4, count, buffer);
1993
1994 return ERROR_OK;
1995 }
1996
1997 u32 xscale_get_ttb(target_t *target)
1998 {
1999 armv4_5_common_t *armv4_5 = target->arch_info;
2000 xscale_common_t *xscale = armv4_5->arch_info;
2001 u32 ttb;
2002
2003 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2004 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2005
2006 return ttb;
2007 }
2008
2009 void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2010 {
2011 armv4_5_common_t *armv4_5 = target->arch_info;
2012 xscale_common_t *xscale = armv4_5->arch_info;
2013 u32 cp15_control;
2014
2015 /* read cp15 control register */
2016 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2017 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2018
2019 if (mmu)
2020 cp15_control &= ~0x1U;
2021
2022 if (d_u_cache)
2023 {
2024 /* clean DCache */
2025 xscale_send_u32(target, 0x50);
2026 xscale_send_u32(target, xscale->cache_clean_address);
2027
2028 /* invalidate DCache */
2029 xscale_send_u32(target, 0x51);
2030
2031 cp15_control &= ~0x4U;
2032 }
2033
2034 if (i_cache)
2035 {
2036 /* invalidate ICache */
2037 xscale_send_u32(target, 0x52);
2038 cp15_control &= ~0x1000U;
2039 }
2040
2041 /* write new cp15 control register */
2042 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2043
2044 /* execute cpwait to ensure outstanding operations complete */
2045 xscale_send_u32(target, 0x53);
2046 }
2047
2048 void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2049 {
2050 armv4_5_common_t *armv4_5 = target->arch_info;
2051 xscale_common_t *xscale = armv4_5->arch_info;
2052 u32 cp15_control;
2053
2054 /* read cp15 control register */
2055 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2056 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2057
2058 if (mmu)
2059 cp15_control |= 0x1U;
2060
2061 if (d_u_cache)
2062 cp15_control |= 0x4U;
2063
2064 if (i_cache)
2065 cp15_control |= 0x1000U;
2066
2067 /* write new cp15 control register */
2068 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2069
2070 /* execute cpwait to ensure outstanding operations complete */
2071 xscale_send_u32(target, 0x53);
2072 }
2073
2074 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2075 {
2076 armv4_5_common_t *armv4_5 = target->arch_info;
2077 xscale_common_t *xscale = armv4_5->arch_info;
2078
2079 if (target->state != TARGET_HALTED)
2080 {
2081 WARNING("target not halted");
2082 return ERROR_TARGET_NOT_HALTED;
2083 }
2084
2085 if (xscale->force_hw_bkpts)
2086 breakpoint->type = BKPT_HARD;
2087
2088 if (breakpoint->set)
2089 {
2090 WARNING("breakpoint already set");
2091 return ERROR_OK;
2092 }
2093
2094 if (breakpoint->type == BKPT_HARD)
2095 {
2096 u32 value = breakpoint->address | 1;
2097 if (!xscale->ibcr0_used)
2098 {
2099 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2100 xscale->ibcr0_used = 1;
2101 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2102 }
2103 else if (!xscale->ibcr1_used)
2104 {
2105 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2106 xscale->ibcr1_used = 1;
2107 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2108 }
2109 else
2110 {
2111 ERROR("BUG: no hardware comparator available");
2112 return ERROR_OK;
2113 }
2114 }
2115 else if (breakpoint->type == BKPT_SOFT)
2116 {
2117 if (breakpoint->length == 4)
2118 {
2119 /* keep the original instruction in target endianness */
2120 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2121 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2122 target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
2123 }
2124 else
2125 {
2126 /* keep the original instruction in target endianness */
2127 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2128 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2129 target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
2130 }
2131 breakpoint->set = 1;
2132 }
2133
2134 return ERROR_OK;
2135
2136 }
2137
2138 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2139 {
2140 armv4_5_common_t *armv4_5 = target->arch_info;
2141 xscale_common_t *xscale = armv4_5->arch_info;
2142
2143 if (target->state != TARGET_HALTED)
2144 {
2145 WARNING("target not halted");
2146 return ERROR_TARGET_NOT_HALTED;
2147 }
2148
2149 if (xscale->force_hw_bkpts)
2150 {
2151 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
2152 breakpoint->type = BKPT_HARD;
2153 }
2154
2155 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2156 {
2157 INFO("no breakpoint unit available for hardware breakpoint");
2158 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2159 }
2160 else
2161 {
2162 xscale->ibcr_available--;
2163 }
2164
2165 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2166 {
2167 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2168 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2169 }
2170
2171 return ERROR_OK;
2172 }
2173
2174 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2175 {
2176 armv4_5_common_t *armv4_5 = target->arch_info;
2177 xscale_common_t *xscale = armv4_5->arch_info;
2178
2179 if (target->state != TARGET_HALTED)
2180 {
2181 WARNING("target not halted");
2182 return ERROR_TARGET_NOT_HALTED;
2183 }
2184
2185 if (!breakpoint->set)
2186 {
2187 WARNING("breakpoint not set");
2188 return ERROR_OK;
2189 }
2190
2191 if (breakpoint->type == BKPT_HARD)
2192 {
2193 if (breakpoint->set == 1)
2194 {
2195 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2196 xscale->ibcr0_used = 0;
2197 }
2198 else if (breakpoint->set == 2)
2199 {
2200 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2201 xscale->ibcr1_used = 0;
2202 }
2203 breakpoint->set = 0;
2204 }
2205 else
2206 {
2207 /* restore original instruction (kept in target endianness) */
2208 if (breakpoint->length == 4)
2209 {
2210 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2211 }
2212 else
2213 {
2214 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2215 }
2216 breakpoint->set = 0;
2217 }
2218
2219 return ERROR_OK;
2220 }
2221
2222 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2223 {
2224 armv4_5_common_t *armv4_5 = target->arch_info;
2225 xscale_common_t *xscale = armv4_5->arch_info;
2226
2227 if (target->state != TARGET_HALTED)
2228 {
2229 WARNING("target not halted");
2230 return ERROR_TARGET_NOT_HALTED;
2231 }
2232
2233 if (breakpoint->set)
2234 {
2235 xscale_unset_breakpoint(target, breakpoint);
2236 }
2237
2238 if (breakpoint->type == BKPT_HARD)
2239 xscale->ibcr_available++;
2240
2241 return ERROR_OK;
2242 }
2243
2244 int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2245 {
2246 armv4_5_common_t *armv4_5 = target->arch_info;
2247 xscale_common_t *xscale = armv4_5->arch_info;
2248 u8 enable;
2249 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2250 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2251
2252 if (target->state != TARGET_HALTED)
2253 {
2254 WARNING("target not halted");
2255 return ERROR_TARGET_NOT_HALTED;
2256 }
2257
2258 xscale_get_reg(dbcon);
2259
2260 switch (watchpoint->rw)
2261 {
2262 case WPT_READ:
2263 enable = 0x3;
2264 break;
2265 case WPT_ACCESS:
2266 enable = 0x2;
2267 break;
2268 case WPT_WRITE:
2269 enable = 0x1;
2270 break;
2271 default:
2272 ERROR("BUG: watchpoint->rw neither read, write nor access");
2273 }
2274
2275 if (!xscale->dbr0_used)
2276 {
2277 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2278 dbcon_value |= enable;
2279 xscale_set_reg_u32(dbcon, dbcon_value);
2280 watchpoint->set = 1;
2281 xscale->dbr0_used = 1;
2282 }
2283 else if (!xscale->dbr1_used)
2284 {
2285 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2286 dbcon_value |= enable << 2;
2287 xscale_set_reg_u32(dbcon, dbcon_value);
2288 watchpoint->set = 2;
2289 xscale->dbr1_used = 1;
2290 }
2291 else
2292 {
2293 ERROR("BUG: no hardware comparator available");
2294 return ERROR_OK;
2295 }
2296
2297 return ERROR_OK;
2298 }
2299
2300 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2301 {
2302 armv4_5_common_t *armv4_5 = target->arch_info;
2303 xscale_common_t *xscale = armv4_5->arch_info;
2304
2305 if (target->state != TARGET_HALTED)
2306 {
2307 WARNING("target not halted");
2308 return ERROR_TARGET_NOT_HALTED;
2309 }
2310
2311 if (xscale->dbr_available < 1)
2312 {
2313 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2314 }
2315
2316 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
2317 {
2318 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2319 }
2320
2321 xscale->dbr_available--;
2322
2323 return ERROR_OK;
2324 }
2325
2326 int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2327 {
2328 armv4_5_common_t *armv4_5 = target->arch_info;
2329 xscale_common_t *xscale = armv4_5->arch_info;
2330 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2331 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2332
2333 if (target->state != TARGET_HALTED)
2334 {
2335 WARNING("target not halted");
2336 return ERROR_TARGET_NOT_HALTED;
2337 }
2338
2339 if (!watchpoint->set)
2340 {
2341 WARNING("breakpoint not set");
2342 return ERROR_OK;
2343 }
2344
2345 if (watchpoint->set == 1)
2346 {
2347 dbcon_value &= ~0x3;
2348 xscale_set_reg_u32(dbcon, dbcon_value);
2349 xscale->dbr0_used = 0;
2350 }
2351 else if (watchpoint->set == 2)
2352 {
2353 dbcon_value &= ~0xc;
2354 xscale_set_reg_u32(dbcon, dbcon_value);
2355 xscale->dbr1_used = 0;
2356 }
2357 watchpoint->set = 0;
2358
2359 return ERROR_OK;
2360 }
2361
2362 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2363 {
2364 armv4_5_common_t *armv4_5 = target->arch_info;
2365 xscale_common_t *xscale = armv4_5->arch_info;
2366
2367 if (target->state != TARGET_HALTED)
2368 {
2369 WARNING("target not halted");
2370 return ERROR_TARGET_NOT_HALTED;
2371 }
2372
2373 if (watchpoint->set)
2374 {
2375 xscale_unset_watchpoint(target, watchpoint);
2376 }
2377
2378 xscale->dbr_available++;
2379
2380 return ERROR_OK;
2381 }
2382
2383 void xscale_enable_watchpoints(struct target_s *target)
2384 {
2385 watchpoint_t *watchpoint = target->watchpoints;
2386
2387 while (watchpoint)
2388 {
2389 if (watchpoint->set == 0)
2390 xscale_set_watchpoint(target, watchpoint);
2391 watchpoint = watchpoint->next;
2392 }
2393 }
2394
2395 void xscale_enable_breakpoints(struct target_s *target)
2396 {
2397 breakpoint_t *breakpoint = target->breakpoints;
2398
2399 /* set any pending breakpoints */
2400 while (breakpoint)
2401 {
2402 if (breakpoint->set == 0)
2403 xscale_set_breakpoint(target, breakpoint);
2404 breakpoint = breakpoint->next;
2405 }
2406 }
2407
2408 int xscale_get_reg(reg_t *reg)
2409 {
2410 xscale_reg_t *arch_info = reg->arch_info;
2411 target_t *target = arch_info->target;
2412 armv4_5_common_t *armv4_5 = target->arch_info;
2413 xscale_common_t *xscale = armv4_5->arch_info;
2414
2415 /* DCSR, TX and RX are accessible via JTAG */
2416 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2417 {
2418 return xscale_read_dcsr(arch_info->target);
2419 }
2420 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2421 {
2422 /* 1 = consume register content */
2423 return xscale_read_tx(arch_info->target, 1);
2424 }
2425 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2426 {
2427 /* can't read from RX register (host -> debug handler) */
2428 return ERROR_OK;
2429 }
2430 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2431 {
2432 /* can't (explicitly) read from TXRXCTRL register */
2433 return ERROR_OK;
2434 }
2435 else /* Other DBG registers have to be transfered by the debug handler */
2436 {
2437 /* send CP read request (command 0x40) */
2438 xscale_send_u32(target, 0x40);
2439
2440 /* send CP register number */
2441 xscale_send_u32(target, arch_info->dbg_handler_number);
2442
2443 /* read register value */
2444 xscale_read_tx(target, 1);
2445 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2446
2447 reg->dirty = 0;
2448 reg->valid = 1;
2449 }
2450
2451 return ERROR_OK;
2452 }
2453
2454 int xscale_set_reg(reg_t *reg, u8* buf)
2455 {
2456 xscale_reg_t *arch_info = reg->arch_info;
2457 target_t *target = arch_info->target;
2458 armv4_5_common_t *armv4_5 = target->arch_info;
2459 xscale_common_t *xscale = armv4_5->arch_info;
2460 u32 value = buf_get_u32(buf, 0, 32);
2461
2462 /* DCSR, TX and RX are accessible via JTAG */
2463 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2464 {
2465 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2466 return xscale_write_dcsr(arch_info->target, -1, -1);
2467 }
2468 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2469 {
2470 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2471 return xscale_write_rx(arch_info->target);
2472 }
2473 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2474 {
2475 /* can't write to TX register (debug-handler -> host) */
2476 return ERROR_OK;
2477 }
2478 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2479 {
2480 /* can't (explicitly) write to TXRXCTRL register */
2481 return ERROR_OK;
2482 }
2483 else /* Other DBG registers have to be transfered by the debug handler */
2484 {
2485 /* send CP write request (command 0x41) */
2486 xscale_send_u32(target, 0x41);
2487
2488 /* send CP register number */
2489 xscale_send_u32(target, arch_info->dbg_handler_number);
2490
2491 /* send CP register value */
2492 xscale_send_u32(target, value);
2493 buf_set_u32(reg->value, 0, 32, value);
2494 }
2495
2496 return ERROR_OK;
2497 }
2498
2499 /* convenience wrapper to access XScale specific registers */
2500 int xscale_set_reg_u32(reg_t *reg, u32 value)
2501 {
2502 u8 buf[4];
2503
2504 buf_set_u32(buf, 0, 32, value);
2505
2506 return xscale_set_reg(reg, buf);
2507 }
2508
2509 int xscale_write_dcsr_sw(target_t *target, u32 value)
2510 {
2511 /* get pointers to arch-specific information */
2512 armv4_5_common_t *armv4_5 = target->arch_info;
2513 xscale_common_t *xscale = armv4_5->arch_info;
2514 reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2515 xscale_reg_t *dcsr_arch_info = dcsr->arch_info;
2516
2517 /* send CP write request (command 0x41) */
2518 xscale_send_u32(target, 0x41);
2519
2520 /* send CP register number */
2521 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2522
2523 /* send CP register value */
2524 xscale_send_u32(target, value);
2525 buf_set_u32(dcsr->value, 0, 32, value);
2526
2527 return ERROR_OK;
2528 }
2529
2530 void xscale_build_reg_cache(target_t *target)
2531 {
2532 /* get pointers to arch-specific information */
2533 armv4_5_common_t *armv4_5 = target->arch_info;
2534 xscale_common_t *xscale = armv4_5->arch_info;
2535
2536 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
2537 xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info));
2538 int i;
2539 int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t);
2540
2541 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
2542 armv4_5->core_cache = (*cache_p);
2543
2544 /* register a register arch-type for XScale dbg registers only once */
2545 if (xscale_reg_arch_type == -1)
2546 xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
2547
2548 (*cache_p)->next = malloc(sizeof(reg_cache_t));
2549 cache_p = &(*cache_p)->next;
2550
2551 /* fill in values for the xscale reg cache */
2552 (*cache_p)->name = "XScale registers";
2553 (*cache_p)->next = NULL;
2554 (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
2555 (*cache_p)->num_regs = num_regs;
2556
2557 for (i = 0; i < num_regs; i++)
2558 {
2559 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2560 (*cache_p)->reg_list[i].value = calloc(4, 1);
2561 (*cache_p)->reg_list[i].dirty = 0;
2562 (*cache_p)->reg_list[i].valid = 0;
2563 (*cache_p)->reg_list[i].size = 32;
2564 (*cache_p)->reg_list[i].bitfield_desc = NULL;
2565 (*cache_p)->reg_list[i].num_bitfields = 0;
2566 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2567 (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
2568 arch_info[i] = xscale_reg_arch_info[i];
2569 arch_info[i].target = target;
2570 }
2571
2572 xscale->reg_cache = (*cache_p);
2573 }
2574
2575 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
2576 {
2577 if (startup_mode != DAEMON_RESET)
2578 {
2579 ERROR("XScale target requires a reset");
2580 ERROR("Reset target to enable debug");
2581 }
2582
2583 return ERROR_OK;
2584 }
2585
2586 int xscale_quit()
2587 {
2588
2589 return ERROR_OK;
2590 }
2591
2592 int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, char *variant)
2593 {
2594 armv4_5_common_t *armv4_5;
2595 u32 high_reset_branch, low_reset_branch;
2596 int i;
2597
2598 armv4_5 = &xscale->armv4_5_common;
2599
2600 /* store architecture specfic data (none so far) */
2601 xscale->arch_info = NULL;
2602 xscale->common_magic = XSCALE_COMMON_MAGIC;
2603
2604 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
2605 xscale->variant = strdup(variant);
2606
2607 /* prepare JTAG information for the new target */
2608 xscale->jtag_info.chain_pos = chain_pos;
2609 jtag_register_event_callback(xscale_jtag_callback, target);
2610
2611 xscale->jtag_info.dbgrx = 0x02;
2612 xscale->jtag_info.dbgtx = 0x10;
2613 xscale->jtag_info.dcsr = 0x09;
2614 xscale->jtag_info.ldic = 0x07;
2615
2616 if ((strcmp(xscale->variant, "pxa250") == 0) ||
2617 (strcmp(xscale->variant, "pxa255") == 0) ||
2618 (strcmp(xscale->variant, "pxa26x") == 0))
2619 {
2620 xscale->jtag_info.ir_length = 5;
2621 }
2622 else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
2623 (strcmp(xscale->variant, "ixp42x") == 0) ||
2624 (strcmp(xscale->variant, "ixp45x") == 0) ||
2625 (strcmp(xscale->variant, "ixp46x") == 0))
2626 {
2627 xscale->jtag_info.ir_length = 7;
2628 }
2629
2630 /* the debug handler isn't installed (and thus not running) at this time */
2631 xscale->handler_installed = 0;
2632 xscale->handler_running = 0;
2633 xscale->handler_address = 0xfe000800;
2634
2635 /* clear the vectors we keep locally for reference */
2636 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
2637 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
2638
2639 /* no user-specified vectors have been configured yet */
2640 xscale->static_low_vectors_set = 0x0;
2641 xscale->static_high_vectors_set = 0x0;
2642
2643 /* calculate branches to debug handler */
2644 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
2645 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
2646
2647 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
2648 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
2649
2650 for (i = 1; i <= 7; i++)
2651 {
2652 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2653 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2654 }
2655
2656 /* 64kB aligned region used for DCache cleaning */
2657 xscale->cache_clean_address = 0xfffe0000;
2658
2659 xscale->hold_rst = 0;
2660 xscale->external_debug_break = 0;
2661
2662 xscale->force_hw_bkpts = 1;
2663
2664 xscale->ibcr_available = 2;
2665 xscale->ibcr0_used = 0;
2666 xscale->ibcr1_used = 0;
2667
2668 xscale->dbr_available = 2;
2669 xscale->dbr0_used = 0;
2670 xscale->dbr1_used = 0;
2671
2672 xscale->arm_bkpt = ARMV5_BKPT(0x0);
2673 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
2674
2675 xscale->vector_catch = 0x1;
2676
2677 xscale->trace_buffer_enabled = 0;
2678 xscale->trace_buffer_fill = 0;
2679
2680 /* prepare ARMv4/5 specific information */
2681 armv4_5->arch_info = xscale;
2682 armv4_5->read_core_reg = xscale_read_core_reg;
2683 armv4_5->write_core_reg = xscale_write_core_reg;
2684 armv4_5->full_context = xscale_full_context;
2685
2686 armv4_5_init_arch_info(target, armv4_5);
2687
2688 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
2689 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
2690 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
2691 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
2692 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
2693 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
2694 xscale->armv4_5_mmu.has_tiny_pages = 1;
2695 xscale->armv4_5_mmu.mmu_enabled = 0;
2696
2697 return ERROR_OK;
2698 }
2699
2700 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
2701 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
2702 {
2703 int chain_pos;
2704 char *variant = NULL;
2705 xscale_common_t *xscale = malloc(sizeof(xscale_common_t));
2706
2707 if (argc < 5)
2708 {
2709 ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
2710 exit(-1);
2711 }
2712
2713 chain_pos = strtoul(args[3], NULL, 0);
2714
2715 variant = args[4];
2716
2717 xscale_init_arch_info(target, xscale, chain_pos, variant);
2718 xscale_build_reg_cache(target);
2719
2720 return ERROR_OK;
2721 }
2722
2723 int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2724 {
2725 target_t *target = NULL;
2726 armv4_5_common_t *armv4_5;
2727 xscale_common_t *xscale;
2728
2729 u32 handler_address;
2730
2731 if (argc < 2)
2732 {
2733 ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
2734 return ERROR_OK;
2735 }
2736
2737 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
2738 {
2739 ERROR("no target '%s' configured", args[0]);
2740 return ERROR_OK;
2741 }
2742
2743 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2744 {
2745 command_print(cmd_ctx, "target isn't an ARM920t target");
2746 return ERROR_OK;
2747 }
2748
2749 handler_address = strtoul(args[1], NULL, 0);
2750
2751 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
2752 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
2753 {
2754 xscale->handler_address = handler_address;
2755 }
2756 else
2757 {
2758 ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
2759 }
2760
2761 return ERROR_OK;
2762 }
2763
2764 int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2765 {
2766 target_t *target = NULL;
2767 armv4_5_common_t *armv4_5;
2768 xscale_common_t *xscale;
2769
2770 u32 cache_clean_address;
2771
2772 if (argc < 2)
2773 {
2774 ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
2775 return ERROR_OK;
2776 }
2777
2778 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
2779 {
2780 ERROR("no target '%s' configured", args[0]);
2781 return ERROR_OK;
2782 }
2783
2784 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2785 {
2786 command_print(cmd_ctx, "target isn't an XScale target");
2787 return ERROR_OK;
2788 }
2789
2790 cache_clean_address = strtoul(args[1], NULL, 0);
2791
2792 if (cache_clean_address & 0xffff)
2793 {
2794 ERROR("xscale cache_clean_address <address> must be 64kb aligned");
2795 }
2796 else
2797 {
2798 xscale->cache_clean_address = cache_clean_address;
2799 }
2800
2801 return ERROR_OK;
2802 }
2803
2804 int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2805 {
2806 target_t *target = get_current_target(cmd_ctx);
2807 armv4_5_common_t *armv4_5;
2808 xscale_common_t *xscale;
2809
2810 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2811 {
2812 command_print(cmd_ctx, "target isn't an XScale target");
2813 return ERROR_OK;
2814 }
2815
2816 return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
2817 }
2818
2819 int xscale_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
2820 {
2821 target_t *target = get_current_target(cmd_ctx);
2822 armv4_5_common_t *armv4_5;
2823 xscale_common_t *xscale;
2824
2825 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2826 {
2827 command_print(cmd_ctx, "target isn't an XScale target");
2828 return ERROR_OK;
2829 }
2830
2831 if (target->state != TARGET_HALTED)
2832 {
2833 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
2834 return ERROR_OK;
2835 }
2836
2837 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &xscale->armv4_5_mmu);
2838 }
2839
2840 int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
2841 {
2842 target_t *target = get_current_target(cmd_ctx);
2843 armv4_5_common_t *armv4_5;
2844 xscale_common_t *xscale;
2845
2846 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2847 {
2848 command_print(cmd_ctx, "target isn't an XScale target");
2849 return ERROR_OK;
2850 }
2851
2852 if (target->state != TARGET_HALTED)
2853 {
2854 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
2855 return ERROR_OK;
2856 }
2857
2858 if (argc >= 1)
2859 {
2860 if (strcmp("enable", args[0]) == 0)
2861 {
2862 xscale_enable_mmu_caches(target, 1, 0, 0);
2863 xscale->armv4_5_mmu.mmu_enabled = 1;
2864 }
2865 else if (strcmp("disable", args[0]) == 0)
2866 {
2867 xscale_disable_mmu_caches(target, 1, 0, 0);
2868 xscale->armv4_5_mmu.mmu_enabled = 0;
2869 }
2870 }
2871
2872 command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
2873
2874 return ERROR_OK;
2875 }
2876
2877 int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
2878 {
2879 target_t *target = get_current_target(cmd_ctx);
2880 armv4_5_common_t *armv4_5;
2881 xscale_common_t *xscale;
2882 int icache = 0, dcache = 0;
2883
2884 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2885 {
2886 command_print(cmd_ctx, "target isn't an XScale target");
2887 return ERROR_OK;
2888 }
2889
2890 if (target->state != TARGET_HALTED)
2891 {
2892 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
2893 return ERROR_OK;
2894 }
2895
2896 if (strcmp(cmd, "icache") == 0)
2897 icache = 1;
2898 else if (strcmp(cmd, "dcache") == 0)
2899 dcache = 1;
2900
2901 if (argc >= 1)
2902 {
2903 if (strcmp("enable", args[0]) == 0)
2904 {
2905 xscale_enable_mmu_caches(target, 0, dcache, icache);
2906
2907 if (icache)
2908 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
2909 else if (dcache)
2910 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
2911 }
2912 else if (strcmp("disable", args[0]) == 0)
2913 {
2914 xscale_disable_mmu_caches(target, 0, dcache, icache);
2915
2916 if (icache)
2917 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
2918 else if (dcache)
2919 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
2920 }
2921 }
2922
2923 if (icache)
2924 command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
2925
2926 if (dcache)
2927 command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
2928
2929 return ERROR_OK;
2930 }
2931
2932 int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
2933 {
2934 target_t *target = get_current_target(cmd_ctx);
2935 armv4_5_common_t *armv4_5;
2936 xscale_common_t *xscale;
2937
2938 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2939 {
2940 command_print(cmd_ctx, "target isn't an XScale target");
2941 return ERROR_OK;
2942 }
2943
2944 if (argc < 1)
2945 {
2946 command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
2947 }
2948 else
2949 {
2950 xscale->vector_catch = strtoul(args[0], NULL, 0);
2951 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
2952 xscale_write_dcsr(target, -1, -1);
2953 }
2954
2955 command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
2956
2957 return ERROR_OK;
2958 }
2959
2960 int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2961 {
2962 target_t *target = get_current_target(cmd_ctx);
2963 armv4_5_common_t *armv4_5;
2964 xscale_common_t *xscale;
2965
2966 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2967 {
2968 command_print(cmd_ctx, "target isn't an XScale target");
2969 return ERROR_OK;
2970 }
2971
2972 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2973 {
2974 xscale->force_hw_bkpts = 1;
2975 }
2976 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2977 {
2978 xscale->force_hw_bkpts = 0;
2979 }
2980 else
2981 {
2982 command_print(cmd_ctx, "usage: xscale force_hw_bkpts <enable|disable>");
2983 }
2984
2985 command_print(cmd_ctx, "force hardware breakpoints %s", (xscale->force_hw_bkpts) ? "enabled" : "disabled");
2986
2987 return ERROR_OK;
2988 }
2989
2990 int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2991 {
2992 target_t *target = get_current_target(cmd_ctx);
2993 armv4_5_common_t *armv4_5;
2994 xscale_common_t *xscale;
2995 u32 dcsr_value;
2996
2997 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
2998 {
2999 command_print(cmd_ctx, "target isn't an XScale target");
3000 return ERROR_OK;
3001 }
3002
3003 if (target->state != TARGET_HALTED)
3004 {
3005 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3006 return ERROR_OK;
3007 }
3008
3009 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3010 {
3011 xscale->trace_buffer_enabled = 1;
3012 }
3013 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3014 {
3015 xscale->trace_buffer_enabled = 0;
3016 }
3017
3018 if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
3019 {
3020 xscale->trace_buffer_fill = 1;
3021 }
3022 else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
3023 {
3024 xscale->trace_buffer_fill = 0;
3025 }
3026
3027 command_print(cmd_ctx, "trace buffer %s (%s)",
3028 (xscale->trace_buffer_enabled) ? "enabled" : "disabled",
3029 (xscale->trace_buffer_fill) ? "fill" : "wrap");
3030
3031 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3032 if (xscale->trace_buffer_fill)
3033 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3034 else
3035 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3036
3037 return ERROR_OK;
3038 }
3039
3040 int xscale_handle_dump_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3041 {
3042 target_t *target = get_current_target(cmd_ctx);
3043 armv4_5_common_t *armv4_5;
3044 xscale_common_t *xscale;
3045 u32 trace_buffer[258];
3046 int is_address[256];
3047 int i;
3048
3049 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3050 {
3051 command_print(cmd_ctx, "target isn't an XScale target");
3052 return ERROR_OK;
3053 }
3054
3055 if (target->state != TARGET_HALTED)
3056 {
3057 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3058 return ERROR_OK;
3059 }
3060
3061 /* send read trace buffer command (command 0x61) */
3062 xscale_send_u32(target, 0x61);
3063
3064 /* receive trace buffer content */
3065 xscale_receive(target, trace_buffer, 258);
3066
3067 for (i = 255; i >= 0; i--)
3068 {
3069 is_address[i] = 0;
3070 if (((trace_buffer[i] & 0xf0) == 0x90) ||
3071 ((trace_buffer[i] & 0xf0) == 0xd0))
3072 {
3073 if (i >= 4)
3074 is_address[--i] = 1;
3075 if (i >= 3)
3076 is_address[--i] = 1;
3077 if (i >= 2)
3078 is_address[--i] = 1;
3079 if (i >= 1)
3080 is_address[--i] = 1;
3081 }
3082 }
3083
3084 for (i = 0; i < 256; i++)
3085 {
3086 #if 0
3087 command_print(cmd_ctx, "0x%2.2x 0x%2.2x 0x%2.2x 0x%2.2x 0x%2.2x 0x%2.2x 0x%2.2x 0x%2.2x",
3088 trace_buffer[i + 0], trace_buffer[i + 1], trace_buffer[i + 2], trace_buffer[i + 3],
3089 trace_buffer[i + 4], trace_buffer[i + 5], trace_buffer[i + 6], trace_buffer[i + 6]
3090 );
3091 i += 8;
3092 #endif
3093 if (is_address[i])
3094 {
3095 command_print(cmd_ctx, "address: 0x%2.2x%2.2x%2.2x%2.2x", trace_buffer[i], trace_buffer[i+1], trace_buffer[i+2], trace_buffer[i+3]);
3096 i += 3;
3097 }
3098 else
3099 {
3100 switch ((trace_buffer[i] & 0xf0) >> 4)
3101 {
3102 case 0:
3103 command_print(cmd_ctx, "0x%2.2x: reset exception", trace_buffer[i]);
3104 break;
3105 case 1:
3106 command_print(cmd_ctx, "0x%2.2x: undef exception", trace_buffer[i]);
3107 break;
3108 case 2:
3109 command_print(cmd_ctx, "0x%2.2x: swi exception", trace_buffer[i]);
3110 break;
3111 case 3:
3112 command_print(cmd_ctx, "0x%2.2x: pabort exception", trace_buffer[i]);
3113 break;
3114 case 4:
3115 command_print(cmd_ctx, "0x%2.2x: dabort exception", trace_buffer[i]);
3116 break;
3117 case 5:
3118 command_print(cmd_ctx, "0x%2.2x: invalid", trace_buffer[i]);
3119 break;
3120 case 6:
3121 command_print(cmd_ctx, "0x%2.2x: irq exception", trace_buffer[i]);
3122 break;
3123 case 7:
3124 command_print(cmd_ctx, "0x%2.2x: fiq exception", trace_buffer[i]);
3125 break;
3126 case 0x8:
3127 command_print(cmd_ctx, "0x%2.2x: direct branch", trace_buffer[i]);
3128 break;
3129 case 0x9:
3130 command_print(cmd_ctx, "0x%2.2x: indirect branch", trace_buffer[i]);
3131 break;
3132 case 0xa:
3133 command_print(cmd_ctx, "0x%2.2x: invalid", trace_buffer[i]);
3134 break;
3135 case 0xb:
3136 command_print(cmd_ctx, "0x%2.2x: invalid", trace_buffer[i]);
3137 break;
3138 case 0xc:
3139 command_print(cmd_ctx, "0x%2.2x: checkpointed direct branch", trace_buffer[i]);
3140 break;
3141 case 0xd:
3142 command_print(cmd_ctx, "0x%2.2x: checkpointed indirect branch", trace_buffer[i]);
3143 break;
3144 case 0xe:
3145 command_print(cmd_ctx, "0x%2.2x: invalid", trace_buffer[i]);
3146 break;
3147 case 0xf:
3148 command_print(cmd_ctx, "0x%2.2x: rollover", trace_buffer[i]);
3149 break;
3150 }
3151 }
3152 }
3153
3154 command_print(cmd_ctx, "chkpt0: 0x%8.8x, chkpt1: 0x%8.8x", trace_buffer[256], trace_buffer[257]);
3155
3156 return ERROR_OK;
3157 }
3158
3159 int xscale_register_commands(struct command_context_s *cmd_ctx)
3160 {
3161 command_t *xscale_cmd;
3162
3163 xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
3164
3165 register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_CONFIG, NULL);
3166 register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
3167
3168 register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
3169 register_command(cmd_ctx, xscale_cmd, "virt2phys", xscale_handle_virt2phys_command, COMMAND_EXEC, NULL);
3170 register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
3171 register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
3172 register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
3173
3174 register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_idcache_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
3175
3176 register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill'|'wrap']");
3177
3178 register_command(cmd_ctx, xscale_cmd, "dump_trace_buffer", xscale_handle_dump_trace_buffer_command, COMMAND_EXEC, "dump content of trace buffer");
3179
3180 armv4_5_register_commands(cmd_ctx);
3181
3182 return ERROR_OK;
3183 }
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