src/target/xtensa/xtensa.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Generic Xtensa target                                                 *
   5  *   Copyright (C) 2020-2022 Cadence Design Systems, Inc.                  *
   6  *   Copyright (C) 2019 Espressif Systems Ltd.                             *
   7  ***************************************************************************/
   8
   9 #ifndef OPENOCD_TARGET_XTENSA_H
  10 #define OPENOCD_TARGET_XTENSA_H
  11
  12 #include "assert.h"
  13 #include <target/target.h>
  14 #include <target/breakpoints.h>
  15 #include "xtensa_regs.h"
  16 #include "xtensa_debug_module.h"
  17
  18 /**
  19  * @file
  20  * Holds the interface to Xtensa cores.
  21  */
  22
  23 /* Big-endian vs. little-endian detection */
  24 #define XT_ISBE(X)                              ((X)->target->endianness == TARGET_BIG_ENDIAN)
  25
  26 /* 24-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
  27 #define XT_INS_BREAK_LE(S, T)                   (0x004000 | (((S) & 0xF) << 8) | (((T) & 0xF) << 4))
  28 #define XT_INS_BREAK_BE(S, T)                   (0x000400 | (((S) & 0xF) << 12) | ((T) & 0xF))
  29 #define XT_INS_BREAK(X, S, T)                   (XT_ISBE(X) ? XT_INS_BREAK_BE(S, T) : XT_INS_BREAK_LE(S, T))
  30
  31 /* 16-bit break; BE version field-swapped then byte-swapped for use in memory R/W fns */
  32 #define XT_INS_BREAKN_LE(IMM4)                  (0xF02D | (((IMM4) & 0xF) << 8))
  33 #define XT_INS_BREAKN_BE(IMM4)                  (0x0FD2 | (((IMM4) & 0xF) << 12))
  34 #define XT_INS_BREAKN(X, IMM4)                  (XT_ISBE(X) ? XT_INS_BREAKN_BE(IMM4) : XT_INS_BREAKN_LE(IMM4))
  35
  36 #define XT_ISNS_SZ_MAX                          3
  37
  38 /* PS register bits (LX) */
  39 #define XT_PS_RING(_v_)                         ((uint32_t)((_v_) & 0x3) << 6)
  40 #define XT_PS_RING_MSK                          (0x3 << 6)
  41 #define XT_PS_RING_GET(_v_)                     (((_v_) >> 6) & 0x3)
  42 #define XT_PS_CALLINC_MSK                       (0x3 << 16)
  43 #define XT_PS_OWB_MSK                           (0xF << 8)
  44 #define XT_PS_WOE_MSK                           BIT(18)
  45
  46 /* PS register bits (NX) */
  47 #define XT_PS_DIEXC_MSK                         BIT(2)
  48
  49 /* MS register bits (NX) */
  50 #define XT_MS_DE_MSK                            BIT(5)
  51 #define XT_MS_DISPST_MSK                        (0x1f)
  52 #define XT_MS_DISPST_DBG                        (0x10)
  53
  54 /* WB register bits (NX) */
  55 #define XT_WB_P_SHIFT                           (0)
  56 #define XT_WB_P_MSK                             (0x7U << XT_WB_P_SHIFT)
  57 #define XT_WB_C_SHIFT                           (4)
  58 #define XT_WB_C_MSK                             (0x7U << XT_WB_C_SHIFT)
  59 #define XT_WB_N_SHIFT                           (8)
  60 #define XT_WB_N_MSK                             (0x7U << XT_WB_N_SHIFT)
  61 #define XT_WB_S_SHIFT                           (30)
  62 #define XT_WB_S_MSK                             (0x3U << XT_WB_S_SHIFT)
  63
  64 /* IBREAKC register bits (NX) */
  65 #define XT_IBREAKC_FB                           (0x80000000)
  66
  67 /* Definitions for imprecise exception registers (NX) */
  68 #define XT_IMPR_EXC_MSK                         (0x00000013)
  69 #define XT_MESRCLR_IMPR_EXC_MSK                 (0x00000090)
  70
  71 #define XT_LOCAL_MEM_REGIONS_NUM_MAX            8
  72
  73 #define XT_AREGS_NUM_MAX                        64
  74 #define XT_USER_REGS_NUM_MAX                    256
  75
  76 #define XT_MEM_ACCESS_NONE                      0x0
  77 #define XT_MEM_ACCESS_READ                      0x1
  78 #define XT_MEM_ACCESS_WRITE                     0x2
  79
  80 #define XT_MAX_TIE_REG_WIDTH                    (512)   /* TIE register file max 4096 bits */
  81 #define XT_QUERYPKT_RESP_MAX                    (XT_MAX_TIE_REG_WIDTH * 2 + 1)
  82
  83 enum xtensa_qerr_e {
  84         XT_QERR_INTERNAL = 0,
  85         XT_QERR_FAIL,
  86         XT_QERR_INVAL,
  87         XT_QERR_MEM,
  88         XT_QERR_NUM,
  89 };
  90
  91 /* An and ARn registers potentially used as scratch regs */
  92 enum xtensa_ar_scratch_set_e {
  93         XT_AR_SCRATCH_A3 = 0,
  94         XT_AR_SCRATCH_AR3,
  95         XT_AR_SCRATCH_A4,
  96         XT_AR_SCRATCH_AR4,
  97         XT_AR_SCRATCH_NUM
  98 };
  99
 100 struct xtensa_keyval_info_s {
 101         char *chrval;
 102         int intval;
 103 };
 104
 105 enum xtensa_type {
 106         XT_UNDEF = 0,
 107         XT_LX,
 108         XT_NX,
 109 };
 110
 111 struct xtensa_cache_config {
 112         uint8_t way_count;
 113         uint32_t line_size;
 114         uint32_t size;
 115         int writeback;
 116 };
 117
 118 struct xtensa_local_mem_region_config {
 119         target_addr_t base;
 120         uint32_t size;
 121         int access;
 122 };
 123
 124 struct xtensa_local_mem_config {
 125         uint16_t count;
 126         struct xtensa_local_mem_region_config regions[XT_LOCAL_MEM_REGIONS_NUM_MAX];
 127 };
 128
 129 struct xtensa_mmu_config {
 130         bool enabled;
 131         uint8_t itlb_entries_count;
 132         uint8_t dtlb_entries_count;
 133 };
 134
 135 struct xtensa_mpu_config {
 136         bool enabled;
 137         uint8_t nfgseg;
 138         uint32_t minsegsize;
 139         bool lockable;
 140         bool execonly;
 141 };
 142
 143 struct xtensa_irq_config {
 144         bool enabled;
 145         uint8_t irq_num;
 146 };
 147
 148 struct xtensa_high_prio_irq_config {
 149         bool enabled;
 150         uint8_t level_num;
 151         uint8_t excm_level;
 152 };
 153
 154 struct xtensa_debug_config {
 155         bool enabled;
 156         uint8_t irq_level;
 157         uint8_t ibreaks_num;
 158         uint8_t dbreaks_num;
 159         uint8_t perfcount_num;
 160 };
 161
 162 struct xtensa_tracing_config {
 163         bool enabled;
 164         uint32_t mem_sz;
 165         bool reversed_mem_access;
 166 };
 167
 168 struct xtensa_config {
 169         enum xtensa_type core_type;
 170         uint8_t aregs_num;
 171         bool windowed;
 172         bool coproc;
 173         bool exceptions;
 174         struct xtensa_irq_config irq;
 175         struct xtensa_high_prio_irq_config high_irq;
 176         struct xtensa_mmu_config mmu;
 177         struct xtensa_mpu_config mpu;
 178         struct xtensa_debug_config debug;
 179         struct xtensa_tracing_config trace;
 180         struct xtensa_cache_config icache;
 181         struct xtensa_cache_config dcache;
 182         struct xtensa_local_mem_config irom;
 183         struct xtensa_local_mem_config iram;
 184         struct xtensa_local_mem_config drom;
 185         struct xtensa_local_mem_config dram;
 186         struct xtensa_local_mem_config sram;
 187         struct xtensa_local_mem_config srom;
 188 };
 189
 190 typedef uint32_t xtensa_insn_t;
 191
 192 enum xtensa_stepping_isr_mode {
 193         XT_STEPPING_ISR_OFF,    /* interrupts are disabled during stepping */
 194         XT_STEPPING_ISR_ON,             /* interrupts are enabled during stepping */
 195 };
 196
 197 enum xtensa_nx_reg_idx {
 198         XT_NX_REG_IDX_IBREAKC0 = 0,
 199         XT_NX_REG_IDX_WB,
 200         XT_NX_REG_IDX_MS,
 201         XT_NX_REG_IDX_IEVEC,            /* IEVEC, IEEXTERN, and MESR must be contiguous */
 202         XT_NX_REG_IDX_IEEXTERN,
 203         XT_NX_REG_IDX_MESR,
 204         XT_NX_REG_IDX_MESRCLR,
 205         XT_NX_REG_IDX_NUM
 206 };
 207
 208 /* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */
 209 enum xtensa_mode {
 210         XT_MODE_RING0,
 211         XT_MODE_RING1,
 212         XT_MODE_RING2,
 213         XT_MODE_RING3,
 214         XT_MODE_ANY     /* special value to run algorithm in current core mode */
 215 };
 216
 217 struct xtensa_sw_breakpoint {
 218         struct breakpoint *oocd_bp;
 219         /* original insn */
 220         uint8_t insn[XT_ISNS_SZ_MAX];
 221         /* original insn size */
 222         uint8_t insn_sz;        /* 2 or 3 bytes */
 223 };
 224
 225 #define XTENSA_COMMON_MAGIC 0x54E4E555U
 226
 227 /**
 228  * Represents a generic Xtensa core.
 229  */
 230 struct xtensa {
 231         unsigned int common_magic;
 232         struct xtensa_chip_common *xtensa_chip;
 233         struct xtensa_config *core_config;
 234         struct xtensa_debug_module dbg_mod;
 235         struct reg_cache *core_cache;
 236         unsigned int total_regs_num;
 237         unsigned int core_regs_num;
 238         bool regmap_contiguous;
 239         unsigned int genpkt_regs_num;
 240         struct xtensa_reg_desc **contiguous_regs_desc;
 241         struct reg **contiguous_regs_list;
 242         /* Per-config Xtensa registers as specified via "xtreg" in xtensa-core*.cfg */
 243         struct xtensa_reg_desc *optregs;
 244         unsigned int num_optregs;
 245         struct reg *empty_regs;
 246         char qpkt_resp[XT_QUERYPKT_RESP_MAX];
 247         /* An array of pointers to buffers to backup registers' values while algo is run on target.
 248          * Size is 'regs_num'. */
 249         void **algo_context_backup;
 250         unsigned int eps_dbglevel_idx;
 251         unsigned int dbregs_num;
 252         struct target *target;
 253         bool reset_asserted;
 254         enum xtensa_stepping_isr_mode stepping_isr_mode;
 255         struct breakpoint **hw_brps;
 256         struct watchpoint **hw_wps;
 257         struct xtensa_sw_breakpoint *sw_brps;
 258         bool trace_active;
 259         bool permissive_mode;   /* bypass memory checks */
 260         bool suppress_dsr_errors;
 261         uint32_t smp_break;
 262         uint32_t spill_loc;
 263         unsigned int spill_bytes;
 264         uint8_t *spill_buf;
 265         int8_t probe_lsddr32p;
 266         /* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some
 267          * time.This is the number of polling periods after which core is considered to be powered
 268          * off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by
 269          * SW running on target).*/
 270         uint8_t come_online_probes_num;
 271         bool proc_syscall;
 272         bool halt_request;
 273         uint32_t nx_stop_cause;
 274         uint32_t nx_reg_idx[XT_NX_REG_IDX_NUM];
 275         struct xtensa_keyval_info_s scratch_ars[XT_AR_SCRATCH_NUM];
 276         bool regs_fetched;      /* true after first register fetch completed successfully */
 277 };
 278
 279 static inline struct xtensa *target_to_xtensa(struct target *target)
 280 {
 281         assert(target);
 282         struct xtensa *xtensa = target->arch_info;
 283         assert(xtensa->common_magic == XTENSA_COMMON_MAGIC);
 284         return xtensa;
 285 }
 286
 287 int xtensa_init_arch_info(struct target *target,
 288         struct xtensa *xtensa,
 289         const struct xtensa_debug_module_config *dm_cfg);
 290 int xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
 291 void xtensa_target_deinit(struct target *target);
 292
 293 static inline bool xtensa_addr_in_mem(const struct xtensa_local_mem_config *mem, uint32_t addr)
 294 {
 295         for (unsigned int i = 0; i < mem->count; i++) {
 296                 if (addr >= mem->regions[i].base &&
 297                         addr < mem->regions[i].base + mem->regions[i].size)
 298                         return true;
 299         }
 300         return false;
 301 }
 302
 303 static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
 304 {
 305         struct xtensa *xtensa = target_to_xtensa(target);
 306
 307         if (xtensa_addr_in_mem(&xtensa->core_config->drom, addr))
 308                 return true;
 309         if (xtensa_addr_in_mem(&xtensa->core_config->dram, addr))
 310                 return true;
 311         if (xtensa_addr_in_mem(&xtensa->core_config->sram, addr))
 312                 return true;
 313         return false;
 314 }
 315
 316 static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data)
 317 {
 318         struct xtensa_debug_module *dm = &xtensa->dbg_mod;
 319
 320         if (!xtensa->core_config->trace.enabled &&
 321                 (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
 322                 LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
 323                 return ERROR_FAIL;
 324         }
 325         return dm->dbg_ops->queue_reg_read(dm, reg, data);
 326 }
 327
 328 static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data)
 329 {
 330         struct xtensa_debug_module *dm = &xtensa->dbg_mod;
 331
 332         if (!xtensa->core_config->trace.enabled &&
 333                 (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
 334                 LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
 335                 return ERROR_FAIL;
 336         }
 337         return dm->dbg_ops->queue_reg_write(dm, reg, data);
 338 }
 339
 340 static inline int xtensa_core_status_clear(struct target *target, uint32_t bits)
 341 {
 342         struct xtensa *xtensa = target_to_xtensa(target);
 343         return xtensa_dm_core_status_clear(&xtensa->dbg_mod, bits);
 344 }
 345
 346 int xtensa_core_status_check(struct target *target);
 347
 348 int xtensa_examine(struct target *target);
 349 int xtensa_wakeup(struct target *target);
 350 int xtensa_smpbreak_set(struct target *target, uint32_t set);
 351 int xtensa_smpbreak_get(struct target *target, uint32_t *val);
 352 int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set);
 353 int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val);
 354 xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id);
 355 void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value);
 356 void xtensa_reg_set_deep_relgen(struct target *target, enum xtensa_reg_id a_idx, xtensa_reg_val_t value);
 357 int xtensa_fetch_all_regs(struct target *target);
 358 int xtensa_get_gdb_reg_list(struct target *target,
 359         struct reg **reg_list[],
 360         int *reg_list_size,
 361         enum target_register_class reg_class);
 362 uint32_t xtensa_cause_get(struct target *target);
 363 void xtensa_cause_clear(struct target *target);
 364 void xtensa_cause_reset(struct target *target);
 365 int xtensa_poll(struct target *target);
 366 void xtensa_on_poll(struct target *target);
 367 int xtensa_halt(struct target *target);
 368 int xtensa_resume(struct target *target,
 369         int current,
 370         target_addr_t address,
 371         int handle_breakpoints,
 372         int debug_execution);
 373 int xtensa_prepare_resume(struct target *target,
 374         int current,
 375         target_addr_t address,
 376         int handle_breakpoints,
 377         int debug_execution);
 378 int xtensa_do_resume(struct target *target);
 379 int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
 380 int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
 381 int xtensa_mmu_is_enabled(struct target *target, int *enabled);
 382 int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 383 int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);
 384 int xtensa_write_memory(struct target *target,
 385         target_addr_t address,
 386         uint32_t size,
 387         uint32_t count,
 388         const uint8_t *buffer);
 389 int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer);
 390 int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum);
 391 int xtensa_assert_reset(struct target *target);
 392 int xtensa_deassert_reset(struct target *target);
 393 int xtensa_soft_reset_halt(struct target *target);
 394 int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
 395 int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
 396 int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
 397 int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
 398 void xtensa_set_permissive_mode(struct target *target, bool state);
 399 const char *xtensa_get_gdb_arch(struct target *target);
 400 int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p);
 401
 402 COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa);
 403 COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa);
 404 COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa);
 405 COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa);
 406 COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa);
 407 COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa);
 408 COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa);
 409 COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa);
 410 COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa);
 411 COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target);
 412 COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa);
 413 COMMAND_HELPER(xtensa_cmd_perfmon_enable_do, struct xtensa *xtensa);
 414 COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa);
 415 COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa);
 416 COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname);
 417
 418 extern const struct command_registration xtensa_command_handlers[];
 419
 420 #endif  /* OPENOCD_TARGET_XTENSA_H */