src/target/xtensa/xtensa.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Generic Xtensa target                                                 *
   5  *   Copyright (C) 2019 Espressif Systems Ltd.                             *
   6  *   Author: Alexey Gerenkov <alexey@espressif.com>                        *
   7  ***************************************************************************/
   8
   9 #ifndef OPENOCD_TARGET_XTENSA_H
  10 #define OPENOCD_TARGET_XTENSA_H
  11
  12 #include "assert.h"
  13 #include <target/target.h>
  14 #include <target/breakpoints.h>
  15 #include "xtensa_regs.h"
  16 #include "xtensa_debug_module.h"
  17
  18 /**
  19  * @file
  20  * Holds the interface to Xtensa cores.
  21  */
  22
  23 #define XT_ISNS_SZ_MAX                  3
  24
  25 #define XT_PS_RING(_v_)                 ((uint32_t)((_v_) & 0x3) << 6)
  26 #define XT_PS_RING_MSK                  (0x3 << 6)
  27 #define XT_PS_RING_GET(_v_)             (((_v_) >> 6) & 0x3)
  28 #define XT_PS_CALLINC_MSK               (0x3 << 16)
  29 #define XT_PS_OWB_MSK                   (0xF << 8)
  30
  31 #define XT_LOCAL_MEM_REGIONS_NUM_MAX    8
  32
  33 #define XT_AREGS_NUM_MAX                64
  34 #define XT_USER_REGS_NUM_MAX            256
  35
  36 #define XT_MEM_ACCESS_NONE              0x0
  37 #define XT_MEM_ACCESS_READ              0x1
  38 #define XT_MEM_ACCESS_WRITE             0x2
  39
  40 enum xtensa_mem_err_detect {
  41         XT_MEM_ERR_DETECT_NONE,
  42         XT_MEM_ERR_DETECT_PARITY,
  43         XT_MEM_ERR_DETECT_ECC,
  44 };
  45
  46 struct xtensa_cache_config {
  47         uint8_t way_count;
  48         uint8_t line_size;
  49         uint16_t size;
  50         bool writeback;
  51         enum xtensa_mem_err_detect mem_err_check;
  52 };
  53
  54 struct xtensa_local_mem_region_config {
  55         target_addr_t base;
  56         uint32_t size;
  57         enum xtensa_mem_err_detect mem_err_check;
  58         int access;
  59 };
  60
  61 struct xtensa_local_mem_config {
  62         uint16_t count;
  63         struct xtensa_local_mem_region_config regions[XT_LOCAL_MEM_REGIONS_NUM_MAX];
  64 };
  65
  66 struct xtensa_mmu_config {
  67         bool enabled;
  68         uint8_t itlb_entries_count;
  69         uint8_t dtlb_entries_count;
  70         bool ivarway56;
  71         bool dvarway56;
  72 };
  73
  74 struct xtensa_exception_config {
  75         bool enabled;
  76         uint8_t depc_num;
  77 };
  78
  79 struct xtensa_irq_config {
  80         bool enabled;
  81         uint8_t irq_num;
  82 };
  83
  84 struct xtensa_high_prio_irq_config {
  85         bool enabled;
  86         uint8_t excm_level;
  87         uint8_t nmi_num;
  88 };
  89
  90 struct xtensa_debug_config {
  91         bool enabled;
  92         uint8_t irq_level;
  93         uint8_t ibreaks_num;
  94         uint8_t dbreaks_num;
  95         uint8_t icount_sz;
  96 };
  97
  98 struct xtensa_tracing_config {
  99         bool enabled;
 100         uint32_t mem_sz;
 101         bool reversed_mem_access;
 102 };
 103
 104 struct xtensa_timer_irq_config {
 105         bool enabled;
 106         uint8_t comp_num;
 107 };
 108
 109 struct xtensa_config {
 110         bool density;
 111         uint8_t aregs_num;
 112         bool windowed;
 113         bool coproc;
 114         bool fp_coproc;
 115         bool loop;
 116         uint8_t miscregs_num;
 117         bool threadptr;
 118         bool boolean;
 119         bool cond_store;
 120         bool ext_l32r;
 121         bool mac16;
 122         bool reloc_vec;
 123         bool proc_id;
 124         bool mem_err_check;
 125         uint16_t user_regs_num;
 126         const struct xtensa_user_reg_desc *user_regs;
 127         int (*fetch_user_regs)(struct target *target);
 128         int (*queue_write_dirty_user_regs)(struct target *target);
 129         struct xtensa_cache_config icache;
 130         struct xtensa_cache_config dcache;
 131         struct xtensa_local_mem_config irom;
 132         struct xtensa_local_mem_config iram;
 133         struct xtensa_local_mem_config drom;
 134         struct xtensa_local_mem_config dram;
 135         struct xtensa_local_mem_config uram;
 136         struct xtensa_local_mem_config xlmi;
 137         struct xtensa_mmu_config mmu;
 138         struct xtensa_exception_config exc;
 139         struct xtensa_irq_config irq;
 140         struct xtensa_high_prio_irq_config high_irq;
 141         struct xtensa_timer_irq_config tim_irq;
 142         struct xtensa_debug_config debug;
 143         struct xtensa_tracing_config trace;
 144         unsigned int gdb_general_regs_num;
 145         const unsigned int *gdb_regs_mapping;
 146 };
 147
 148 typedef uint32_t xtensa_insn_t;
 149
 150 enum xtensa_stepping_isr_mode {
 151         XT_STEPPING_ISR_OFF,    /* interrupts are disabled during stepping */
 152         XT_STEPPING_ISR_ON,             /* interrupts are enabled during stepping */
 153 };
 154
 155 /* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */
 156 enum xtensa_mode {
 157         XT_MODE_RING0,
 158         XT_MODE_RING1,
 159         XT_MODE_RING2,
 160         XT_MODE_RING3,
 161         XT_MODE_ANY     /* special value to run algorithm in current core mode */
 162 };
 163
 164 struct xtensa_sw_breakpoint {
 165         struct breakpoint *oocd_bp;
 166         /* original insn */
 167         uint8_t insn[XT_ISNS_SZ_MAX];
 168         /* original insn size */
 169         uint8_t insn_sz;        /* 2 or 3 bytes */
 170 };
 171
 172 #define XTENSA_COMMON_MAGIC 0x54E4E555U
 173
 174 /**
 175  * Represents a generic Xtensa core.
 176  */
 177 struct xtensa {
 178         unsigned int common_magic;
 179         const struct xtensa_config *core_config;
 180         struct xtensa_debug_module dbg_mod;
 181         struct reg_cache *core_cache;
 182         unsigned int regs_num;
 183         /* An array of pointers to buffers to backup registers' values while algo is run on target.
 184          * Size is 'regs_num'. */
 185         void **algo_context_backup;
 186         struct target *target;
 187         bool reset_asserted;
 188         enum xtensa_stepping_isr_mode stepping_isr_mode;
 189         struct breakpoint **hw_brps;
 190         struct watchpoint **hw_wps;
 191         struct xtensa_sw_breakpoint *sw_brps;
 192         bool trace_active;
 193         bool permissive_mode;   /* bypass memory checks */
 194         bool suppress_dsr_errors;
 195         uint32_t smp_break;
 196         /* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some
 197          * time.This is the number of polling periods after which core is considered to be powered
 198          * off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by
 199          * SW running on target).*/
 200         uint8_t come_online_probes_num;
 201         bool regs_fetched;      /* true after first register fetch completed successfully */
 202 };
 203
 204 static inline struct xtensa *target_to_xtensa(struct target *target)
 205 {
 206         assert(target);
 207         struct xtensa *xtensa = target->arch_info;
 208         assert(xtensa->common_magic == XTENSA_COMMON_MAGIC);
 209         return xtensa;
 210 }
 211
 212 int xtensa_init_arch_info(struct target *target,
 213         struct xtensa *xtensa,
 214         const struct xtensa_config *cfg,
 215         const struct xtensa_debug_module_config *dm_cfg);
 216 int xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
 217 void xtensa_target_deinit(struct target *target);
 218
 219 static inline bool xtensa_addr_in_mem(const struct xtensa_local_mem_config *mem, uint32_t addr)
 220 {
 221         for (unsigned int i = 0; i < mem->count; i++) {
 222                 if (addr >= mem->regions[i].base &&
 223                         addr < mem->regions[i].base + mem->regions[i].size)
 224                         return true;
 225         }
 226         return false;
 227 }
 228
 229 static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
 230 {
 231         struct xtensa *xtensa = target_to_xtensa(target);
 232
 233         if (xtensa_addr_in_mem(&xtensa->core_config->drom, addr))
 234                 return true;
 235         if (xtensa_addr_in_mem(&xtensa->core_config->dram, addr))
 236                 return true;
 237         if (xtensa_addr_in_mem(&xtensa->core_config->uram, addr))
 238                 return true;
 239         return false;
 240 }
 241
 242 int xtensa_core_status_check(struct target *target);
 243
 244 int xtensa_examine(struct target *target);
 245 int xtensa_wakeup(struct target *target);
 246 int xtensa_smpbreak_set(struct target *target, uint32_t set);
 247 int xtensa_smpbreak_get(struct target *target, uint32_t *val);
 248 int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set);
 249 int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val);
 250 xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id);
 251 void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value);
 252 int xtensa_fetch_all_regs(struct target *target);
 253 int xtensa_get_gdb_reg_list(struct target *target,
 254         struct reg **reg_list[],
 255         int *reg_list_size,
 256         enum target_register_class reg_class);
 257 int xtensa_poll(struct target *target);
 258 void xtensa_on_poll(struct target *target);
 259 int xtensa_halt(struct target *target);
 260 int xtensa_resume(struct target *target,
 261         int current,
 262         target_addr_t address,
 263         int handle_breakpoints,
 264         int debug_execution);
 265 int xtensa_prepare_resume(struct target *target,
 266         int current,
 267         target_addr_t address,
 268         int handle_breakpoints,
 269         int debug_execution);
 270 int xtensa_do_resume(struct target *target);
 271 int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
 272 int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
 273 int xtensa_mmu_is_enabled(struct target *target, int *enabled);
 274 int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 275 int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);
 276 int xtensa_write_memory(struct target *target,
 277         target_addr_t address,
 278         uint32_t size,
 279         uint32_t count,
 280         const uint8_t *buffer);
 281 int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer);
 282 int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum);
 283 int xtensa_assert_reset(struct target *target);
 284 int xtensa_deassert_reset(struct target *target);
 285 int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
 286 int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
 287 int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
 288 int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
 289 void xtensa_set_permissive_mode(struct target *target, bool state);
 290 int xtensa_fetch_user_regs_u32(struct target *target);
 291 int xtensa_queue_write_dirty_user_regs_u32(struct target *target);
 292 const char *xtensa_get_gdb_arch(struct target *target);
 293
 294
 295 COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa);
 296 COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa);
 297 COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target);
 298 COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa);
 299 COMMAND_HELPER(xtensa_cmd_perfmon_enable_do, struct xtensa *xtensa);
 300 COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa);
 301 COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa);
 302 COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname);
 303
 304 extern const struct reg_arch_type xtensa_user_reg_u32_type;
 305 extern const struct reg_arch_type xtensa_user_reg_u128_type;
 306 extern const struct command_registration xtensa_command_handlers[];
 307
 308 #endif  /* OPENOCD_TARGET_XTENSA_H */