src/target/xtensa/xtensa.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Generic Xtensa target                                                 *
   5  *   Copyright (C) 2019 Espressif Systems Ltd.                             *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_TARGET_XTENSA_H
   9 #define OPENOCD_TARGET_XTENSA_H
  10
  11 #include "assert.h"
  12 #include <target/target.h>
  13 #include <target/breakpoints.h>
  14 #include "xtensa_regs.h"
  15 #include "xtensa_debug_module.h"
  16
  17 /**
  18  * @file
  19  * Holds the interface to Xtensa cores.
  20  */
  21
  22 #define XT_ISNS_SZ_MAX                  3
  23
  24 #define XT_PS_RING(_v_)                 ((uint32_t)((_v_) & 0x3) << 6)
  25 #define XT_PS_RING_MSK                  (0x3 << 6)
  26 #define XT_PS_RING_GET(_v_)             (((_v_) >> 6) & 0x3)
  27 #define XT_PS_CALLINC_MSK               (0x3 << 16)
  28 #define XT_PS_OWB_MSK                   (0xF << 8)
  29
  30 #define XT_LOCAL_MEM_REGIONS_NUM_MAX    8
  31
  32 #define XT_AREGS_NUM_MAX                64
  33 #define XT_USER_REGS_NUM_MAX            256
  34
  35 #define XT_MEM_ACCESS_NONE              0x0
  36 #define XT_MEM_ACCESS_READ              0x1
  37 #define XT_MEM_ACCESS_WRITE             0x2
  38
  39 enum xtensa_mem_err_detect {
  40         XT_MEM_ERR_DETECT_NONE,
  41         XT_MEM_ERR_DETECT_PARITY,
  42         XT_MEM_ERR_DETECT_ECC,
  43 };
  44
  45 struct xtensa_cache_config {
  46         uint8_t way_count;
  47         uint8_t line_size;
  48         uint16_t size;
  49         bool writeback;
  50         enum xtensa_mem_err_detect mem_err_check;
  51 };
  52
  53 struct xtensa_local_mem_region_config {
  54         target_addr_t base;
  55         uint32_t size;
  56         enum xtensa_mem_err_detect mem_err_check;
  57         int access;
  58 };
  59
  60 struct xtensa_local_mem_config {
  61         uint16_t count;
  62         struct xtensa_local_mem_region_config regions[XT_LOCAL_MEM_REGIONS_NUM_MAX];
  63 };
  64
  65 struct xtensa_mmu_config {
  66         bool enabled;
  67         uint8_t itlb_entries_count;
  68         uint8_t dtlb_entries_count;
  69         bool ivarway56;
  70         bool dvarway56;
  71 };
  72
  73 struct xtensa_exception_config {
  74         bool enabled;
  75         uint8_t depc_num;
  76 };
  77
  78 struct xtensa_irq_config {
  79         bool enabled;
  80         uint8_t irq_num;
  81 };
  82
  83 struct xtensa_high_prio_irq_config {
  84         bool enabled;
  85         uint8_t excm_level;
  86         uint8_t nmi_num;
  87 };
  88
  89 struct xtensa_debug_config {
  90         bool enabled;
  91         uint8_t irq_level;
  92         uint8_t ibreaks_num;
  93         uint8_t dbreaks_num;
  94         uint8_t icount_sz;
  95 };
  96
  97 struct xtensa_tracing_config {
  98         bool enabled;
  99         uint32_t mem_sz;
 100         bool reversed_mem_access;
 101 };
 102
 103 struct xtensa_timer_irq_config {
 104         bool enabled;
 105         uint8_t comp_num;
 106 };
 107
 108 struct xtensa_config {
 109         bool density;
 110         uint8_t aregs_num;
 111         bool windowed;
 112         bool coproc;
 113         bool fp_coproc;
 114         bool loop;
 115         uint8_t miscregs_num;
 116         bool threadptr;
 117         bool boolean;
 118         bool cond_store;
 119         bool ext_l32r;
 120         bool mac16;
 121         bool reloc_vec;
 122         bool proc_id;
 123         bool mem_err_check;
 124         uint16_t user_regs_num;
 125         const struct xtensa_user_reg_desc *user_regs;
 126         int (*fetch_user_regs)(struct target *target);
 127         int (*queue_write_dirty_user_regs)(struct target *target);
 128         struct xtensa_cache_config icache;
 129         struct xtensa_cache_config dcache;
 130         struct xtensa_local_mem_config irom;
 131         struct xtensa_local_mem_config iram;
 132         struct xtensa_local_mem_config drom;
 133         struct xtensa_local_mem_config dram;
 134         struct xtensa_local_mem_config uram;
 135         struct xtensa_local_mem_config xlmi;
 136         struct xtensa_mmu_config mmu;
 137         struct xtensa_exception_config exc;
 138         struct xtensa_irq_config irq;
 139         struct xtensa_high_prio_irq_config high_irq;
 140         struct xtensa_timer_irq_config tim_irq;
 141         struct xtensa_debug_config debug;
 142         struct xtensa_tracing_config trace;
 143         unsigned int gdb_general_regs_num;
 144         const unsigned int *gdb_regs_mapping;
 145 };
 146
 147 typedef uint32_t xtensa_insn_t;
 148
 149 enum xtensa_stepping_isr_mode {
 150         XT_STEPPING_ISR_OFF,    /* interrupts are disabled during stepping */
 151         XT_STEPPING_ISR_ON,             /* interrupts are enabled during stepping */
 152 };
 153
 154 /* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */
 155 enum xtensa_mode {
 156         XT_MODE_RING0,
 157         XT_MODE_RING1,
 158         XT_MODE_RING2,
 159         XT_MODE_RING3,
 160         XT_MODE_ANY     /* special value to run algorithm in current core mode */
 161 };
 162
 163 struct xtensa_sw_breakpoint {
 164         struct breakpoint *oocd_bp;
 165         /* original insn */
 166         uint8_t insn[XT_ISNS_SZ_MAX];
 167         /* original insn size */
 168         uint8_t insn_sz;        /* 2 or 3 bytes */
 169 };
 170
 171 #define XTENSA_COMMON_MAGIC 0x54E4E555U
 172
 173 /**
 174  * Represents a generic Xtensa core.
 175  */
 176 struct xtensa {
 177         unsigned int common_magic;
 178         const struct xtensa_config *core_config;
 179         struct xtensa_debug_module dbg_mod;
 180         struct reg_cache *core_cache;
 181         unsigned int regs_num;
 182         /* An array of pointers to buffers to backup registers' values while algo is run on target.
 183          * Size is 'regs_num'. */
 184         void **algo_context_backup;
 185         struct target *target;
 186         bool reset_asserted;
 187         enum xtensa_stepping_isr_mode stepping_isr_mode;
 188         struct breakpoint **hw_brps;
 189         struct watchpoint **hw_wps;
 190         struct xtensa_sw_breakpoint *sw_brps;
 191         bool trace_active;
 192         bool permissive_mode;   /* bypass memory checks */
 193         bool suppress_dsr_errors;
 194         uint32_t smp_break;
 195         /* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some
 196          * time.This is the number of polling periods after which core is considered to be powered
 197          * off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by
 198          * SW running on target).*/
 199         uint8_t come_online_probes_num;
 200         bool regs_fetched;      /* true after first register fetch completed successfully */
 201 };
 202
 203 static inline struct xtensa *target_to_xtensa(struct target *target)
 204 {
 205         assert(target);
 206         struct xtensa *xtensa = target->arch_info;
 207         assert(xtensa->common_magic == XTENSA_COMMON_MAGIC);
 208         return xtensa;
 209 }
 210
 211 int xtensa_init_arch_info(struct target *target,
 212         struct xtensa *xtensa,
 213         const struct xtensa_config *cfg,
 214         const struct xtensa_debug_module_config *dm_cfg);
 215 int xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
 216 void xtensa_target_deinit(struct target *target);
 217
 218 static inline bool xtensa_addr_in_mem(const struct xtensa_local_mem_config *mem, uint32_t addr)
 219 {
 220         for (unsigned int i = 0; i < mem->count; i++) {
 221                 if (addr >= mem->regions[i].base &&
 222                         addr < mem->regions[i].base + mem->regions[i].size)
 223                         return true;
 224         }
 225         return false;
 226 }
 227
 228 static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
 229 {
 230         struct xtensa *xtensa = target_to_xtensa(target);
 231
 232         if (xtensa_addr_in_mem(&xtensa->core_config->drom, addr))
 233                 return true;
 234         if (xtensa_addr_in_mem(&xtensa->core_config->dram, addr))
 235                 return true;
 236         if (xtensa_addr_in_mem(&xtensa->core_config->uram, addr))
 237                 return true;
 238         return false;
 239 }
 240
 241 int xtensa_core_status_check(struct target *target);
 242
 243 int xtensa_examine(struct target *target);
 244 int xtensa_wakeup(struct target *target);
 245 int xtensa_smpbreak_set(struct target *target, uint32_t set);
 246 int xtensa_smpbreak_get(struct target *target, uint32_t *val);
 247 int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set);
 248 int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val);
 249 xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id);
 250 void xtensa_reg_set(struct target *target, enum xtensa_reg_id reg_id, xtensa_reg_val_t value);
 251 int xtensa_fetch_all_regs(struct target *target);
 252 int xtensa_get_gdb_reg_list(struct target *target,
 253         struct reg **reg_list[],
 254         int *reg_list_size,
 255         enum target_register_class reg_class);
 256 int xtensa_poll(struct target *target);
 257 void xtensa_on_poll(struct target *target);
 258 int xtensa_halt(struct target *target);
 259 int xtensa_resume(struct target *target,
 260         int current,
 261         target_addr_t address,
 262         int handle_breakpoints,
 263         int debug_execution);
 264 int xtensa_prepare_resume(struct target *target,
 265         int current,
 266         target_addr_t address,
 267         int handle_breakpoints,
 268         int debug_execution);
 269 int xtensa_do_resume(struct target *target);
 270 int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
 271 int xtensa_do_step(struct target *target, int current, target_addr_t address, int handle_breakpoints);
 272 int xtensa_mmu_is_enabled(struct target *target, int *enabled);
 273 int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 274 int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);
 275 int xtensa_write_memory(struct target *target,
 276         target_addr_t address,
 277         uint32_t size,
 278         uint32_t count,
 279         const uint8_t *buffer);
 280 int xtensa_write_buffer(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer);
 281 int xtensa_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum);
 282 int xtensa_assert_reset(struct target *target);
 283 int xtensa_deassert_reset(struct target *target);
 284 int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
 285 int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
 286 int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
 287 int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
 288 void xtensa_set_permissive_mode(struct target *target, bool state);
 289 int xtensa_fetch_user_regs_u32(struct target *target);
 290 int xtensa_queue_write_dirty_user_regs_u32(struct target *target);
 291 const char *xtensa_get_gdb_arch(struct target *target);
 292
 293
 294 COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa);
 295 COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa);
 296 COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target);
 297 COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa);
 298 COMMAND_HELPER(xtensa_cmd_perfmon_enable_do, struct xtensa *xtensa);
 299 COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa);
 300 COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa);
 301 COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname);
 302
 303 extern const struct reg_arch_type xtensa_user_reg_u32_type;
 304 extern const struct reg_arch_type xtensa_user_reg_u128_type;
 305 extern const struct command_registration xtensa_command_handlers[];
 306
 307 #endif  /* OPENOCD_TARGET_XTENSA_H */