src/target/xtensa/xtensa_debug_module.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Xtensa Debug Module (XDM) Support for OpenOCD                         *
   5  *   Copyright (C) 2020-2022 Cadence Design Systems, Inc.                  *
   6  *   Copyright (C) 2019 Espressif Systems Ltd.                             *
   7  *   Derived from original ESP8266 target.                                 *
   8  *   Author: Angus Gratton gus@projectgus.com                              *
   9  ***************************************************************************/
  10
  11 #ifndef OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
  12 #define OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H
  13
  14 #include <jtag/jtag.h>
  15 #include <target/arm_adi_v5.h>
  16 #include <helper/bits.h>
  17 #include <target/target.h>
  18
  19 /* Virtual IDs for using with xtensa_power_ops API */
  20 enum xtensa_dm_pwr_reg {
  21         XDMREG_PWRCTL = 0x00,
  22         XDMREG_PWRSTAT,
  23         XDMREG_PWRNUM
  24 };
  25
  26 /* Debug Module Power Register offsets within APB */
  27 struct xtensa_dm_pwr_reg_offsets {
  28         uint16_t apb;
  29 };
  30
  31 /* Debug Module Power Register offset structure; must include XDMREG_PWRNUM entries */
  32 #define XTENSA_DM_PWR_REG_OFFSETS       {                               \
  33         /* Power/Reset Registers */                                             \
  34         { .apb = 0x3020 },              /* XDMREG_PWRCTL */             \
  35         { .apb = 0x3024 },              /* XDMREG_PWRSTAT */    \
  36 }
  37
  38 /*
  39  From the manual:
  40  To properly use Debug registers through JTAG, software must ensure that:
  41  - Tap is out of reset
  42  - Xtensa Debug Module is out of reset
  43  - Other bits of PWRCTL are set to their desired values, and finally
  44  - JtagDebugUse transitions from 0 to 1
  45  The bit must continue to be 1 in order for JTAG accesses to the Debug
  46  Module to happen correctly. When it is set, any write to this bit clears it.
  47  Either don't access it, or re-write it to 1 so JTAG accesses continue.
  48 */
  49 #define PWRCTL_JTAGDEBUGUSE(x)          (((x)->dbg_mod.dap) ? (0)     : BIT(7))
  50 #define PWRCTL_DEBUGRESET(x)            (((x)->dbg_mod.dap) ? BIT(28) : BIT(6))
  51 #define PWRCTL_CORERESET(x)                     (((x)->dbg_mod.dap) ? BIT(16) : BIT(4))
  52 #define PWRCTL_DEBUGWAKEUP(x)           (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
  53 #define PWRCTL_MEMWAKEUP(x)                     (((x)->dbg_mod.dap) ? BIT(8)  : BIT(1))
  54 #define PWRCTL_COREWAKEUP(x)            (((x)->dbg_mod.dap) ? BIT(0)  : BIT(0))
  55
  56 #define PWRSTAT_DEBUGWASRESET_DM(d)     (((d)->dap) ? BIT(28) : BIT(6))
  57 #define PWRSTAT_COREWASRESET_DM(d)      (((d)->dap) ? BIT(16) : BIT(4))
  58 #define PWRSTAT_DEBUGWASRESET(x)        (PWRSTAT_DEBUGWASRESET_DM(&((x)->dbg_mod)))
  59 #define PWRSTAT_COREWASRESET(x)         (PWRSTAT_COREWASRESET_DM(&((x)->dbg_mod)))
  60 #define PWRSTAT_CORESTILLNEEDED(x)      (((x)->dbg_mod.dap) ? BIT(4)  : BIT(3))
  61 #define PWRSTAT_DEBUGDOMAINON(x)        (((x)->dbg_mod.dap) ? BIT(12) : BIT(2))
  62 #define PWRSTAT_MEMDOMAINON(x)          (((x)->dbg_mod.dap) ? BIT(8)  : BIT(1))
  63 #define PWRSTAT_COREDOMAINON(x)         (((x)->dbg_mod.dap) ? BIT(0)  : BIT(0))
  64
  65 /* Virtual IDs for using with xtensa_debug_ops API */
  66 enum xtensa_dm_reg {
  67         /* TRAX Registers */
  68         XDMREG_TRAXID = 0x00,
  69         XDMREG_TRAXCTRL,
  70         XDMREG_TRAXSTAT,
  71         XDMREG_TRAXDATA,
  72         XDMREG_TRAXADDR,
  73         XDMREG_TRIGGERPC,
  74         XDMREG_PCMATCHCTRL,
  75         XDMREG_DELAYCNT,
  76         XDMREG_MEMADDRSTART,
  77         XDMREG_MEMADDREND,
  78         XDMREG_EXTTIMELO,
  79         XDMREG_EXTTIMEHI,
  80         XDMREG_TRAXRSVD48,
  81         XDMREG_TRAXRSVD4C,
  82         XDMREG_TRAXRSVD50,
  83         XDMREG_TRAXRSVD54,
  84         XDMREG_TRAXRSVD58,
  85         XDMREG_TRAXRSVD5C,
  86         XDMREG_TRAXRSVD60,
  87         XDMREG_TRAXRSVD64,
  88         XDMREG_TRAXRSVD68,
  89         XDMREG_TRAXRSVD6C,
  90         XDMREG_TRAXRSVD70,
  91         XDMREG_TRAXRSVD74,
  92         XDMREG_CONFIGID0,
  93         XDMREG_CONFIGID1,
  94
  95         /* Performance Monitor Registers */
  96         XDMREG_PMG,
  97         XDMREG_INTPC,
  98         XDMREG_PM0,
  99         XDMREG_PM1,
 100         XDMREG_PM2,
 101         XDMREG_PM3,
 102         XDMREG_PM4,
 103         XDMREG_PM5,
 104         XDMREG_PM6,
 105         XDMREG_PM7,
 106         XDMREG_PMCTRL0,
 107         XDMREG_PMCTRL1,
 108         XDMREG_PMCTRL2,
 109         XDMREG_PMCTRL3,
 110         XDMREG_PMCTRL4,
 111         XDMREG_PMCTRL5,
 112         XDMREG_PMCTRL6,
 113         XDMREG_PMCTRL7,
 114         XDMREG_PMSTAT0,
 115         XDMREG_PMSTAT1,
 116         XDMREG_PMSTAT2,
 117         XDMREG_PMSTAT3,
 118         XDMREG_PMSTAT4,
 119         XDMREG_PMSTAT5,
 120         XDMREG_PMSTAT6,
 121         XDMREG_PMSTAT7,
 122
 123         /* OCD Registers */
 124         XDMREG_OCDID,
 125         XDMREG_DCRCLR,
 126         XDMREG_DCRSET,
 127         XDMREG_DSR,
 128         XDMREG_DDR,
 129         XDMREG_DDREXEC,
 130         XDMREG_DIR0EXEC,
 131         XDMREG_DIR0,
 132         XDMREG_DIR1,
 133         XDMREG_DIR2,
 134         XDMREG_DIR3,
 135         XDMREG_DIR4,
 136         XDMREG_DIR5,
 137         XDMREG_DIR6,
 138         XDMREG_DIR7,
 139
 140         /* Misc Registers */
 141         XDMREG_ERISTAT,
 142
 143         /* CoreSight Registers */
 144         XDMREG_ITCTRL,
 145         XDMREG_CLAIMSET,
 146         XDMREG_CLAIMCLR,
 147         XDMREG_LOCKACCESS,
 148         XDMREG_LOCKSTATUS,
 149         XDMREG_AUTHSTATUS,
 150         XDMREG_DEVID,
 151         XDMREG_DEVTYPE,
 152         XDMREG_PERID4,
 153         XDMREG_PERID5,
 154         XDMREG_PERID6,
 155         XDMREG_PERID7,
 156         XDMREG_PERID0,
 157         XDMREG_PERID1,
 158         XDMREG_PERID2,
 159         XDMREG_PERID3,
 160         XDMREG_COMPID0,
 161         XDMREG_COMPID1,
 162         XDMREG_COMPID2,
 163         XDMREG_COMPID3,
 164
 165         XDMREG_NUM
 166 };
 167
 168 /* Debug Module Register offsets within Nexus (NAR) or APB */
 169 struct xtensa_dm_reg_offsets {
 170         uint8_t  nar;
 171         uint16_t apb;
 172 };
 173
 174 /* Debug Module Register offset structure; must include XDMREG_NUM entries */
 175 #define XTENSA_DM_REG_OFFSETS   {                                                               \
 176         /* TRAX Registers */                                                                            \
 177         { .nar = 0x00, .apb = 0x0000 }, /* XDMREG_TRAXID */                     \
 178         { .nar = 0x01, .apb = 0x0004 }, /* XDMREG_TRAXCTRL */           \
 179         { .nar = 0x02, .apb = 0x0008 }, /* XDMREG_TRAXSTAT */           \
 180         { .nar = 0x03, .apb = 0x000c }, /* XDMREG_TRAXDATA */           \
 181         { .nar = 0x04, .apb = 0x0010 }, /* XDMREG_TRAXADDR */           \
 182         { .nar = 0x05, .apb = 0x0014 }, /* XDMREG_TRIGGERPC */          \
 183         { .nar = 0x06, .apb = 0x0018 }, /* XDMREG_PCMATCHCTRL */        \
 184         { .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */           \
 185         { .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */       \
 186         { .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */         \
 187         { .nar = 0x10, .apb = 0x0040 }, /* XDMREG_EXTTIMELO */          \
 188         { .nar = 0x11, .apb = 0x0044 }, /* XDMREG_EXTTIMEHI */          \
 189         { .nar = 0x12, .apb = 0x0048 }, /* XDMREG_TRAXRSVD48 */         \
 190         { .nar = 0x13, .apb = 0x004c }, /* XDMREG_TRAXRSVD4C */         \
 191         { .nar = 0x14, .apb = 0x0050 }, /* XDMREG_TRAXRSVD50 */         \
 192         { .nar = 0x15, .apb = 0x0054 }, /* XDMREG_TRAXRSVD54 */         \
 193         { .nar = 0x16, .apb = 0x0058 }, /* XDMREG_TRAXRSVD58 */         \
 194         { .nar = 0x17, .apb = 0x005c }, /* XDMREG_TRAXRSVD5C */         \
 195         { .nar = 0x18, .apb = 0x0060 }, /* XDMREG_TRAXRSVD60 */         \
 196         { .nar = 0x19, .apb = 0x0064 }, /* XDMREG_TRAXRSVD64 */         \
 197         { .nar = 0x1a, .apb = 0x0068 }, /* XDMREG_TRAXRSVD68 */         \
 198         { .nar = 0x1b, .apb = 0x006c }, /* XDMREG_TRAXRSVD6C */         \
 199         { .nar = 0x1c, .apb = 0x0070 }, /* XDMREG_TRAXRSVD70 */         \
 200         { .nar = 0x1d, .apb = 0x0074 }, /* XDMREG_TRAXRSVD74 */         \
 201         { .nar = 0x1e, .apb = 0x0078 }, /* XDMREG_CONFIGID0 */          \
 202         { .nar = 0x1f, .apb = 0x007c }, /* XDMREG_CONFIGID1 */          \
 203                                                                                                                                 \
 204         /* Performance Monitor Registers */                                                     \
 205         { .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */                        \
 206         { .nar = 0x24, .apb = 0x1010 }, /* XDMREG_INTPC */                      \
 207         { .nar = 0x28, .apb = 0x1080 }, /* XDMREG_PM0 */                        \
 208         { .nar = 0x29, .apb = 0x1084 }, /* XDMREG_PM1 */                        \
 209         { .nar = 0x2a, .apb = 0x1088 }, /* XDMREG_PM2 */                        \
 210         { .nar = 0x2b, .apb = 0x108c }, /* XDMREG_PM3 */                        \
 211         { .nar = 0x2c, .apb = 0x1090 }, /* XDMREG_PM4 */                        \
 212         { .nar = 0x2d, .apb = 0x1094 }, /* XDMREG_PM5 */                        \
 213         { .nar = 0x2e, .apb = 0x1098 }, /* XDMREG_PM6 */                        \
 214         { .nar = 0x2f, .apb = 0x109c }, /* XDMREG_PM7 */                        \
 215         { .nar = 0x30, .apb = 0x1100 }, /* XDMREG_PMCTRL0 */            \
 216         { .nar = 0x31, .apb = 0x1104 }, /* XDMREG_PMCTRL1 */            \
 217         { .nar = 0x32, .apb = 0x1108 }, /* XDMREG_PMCTRL2 */            \
 218         { .nar = 0x33, .apb = 0x110c }, /* XDMREG_PMCTRL3 */            \
 219         { .nar = 0x34, .apb = 0x1110 }, /* XDMREG_PMCTRL4 */            \
 220         { .nar = 0x35, .apb = 0x1114 }, /* XDMREG_PMCTRL5 */            \
 221         { .nar = 0x36, .apb = 0x1118 }, /* XDMREG_PMCTRL6 */            \
 222         { .nar = 0x37, .apb = 0x111c }, /* XDMREG_PMCTRL7 */            \
 223         { .nar = 0x38, .apb = 0x1180 }, /* XDMREG_PMSTAT0 */            \
 224         { .nar = 0x39, .apb = 0x1184 }, /* XDMREG_PMSTAT1 */            \
 225         { .nar = 0x3a, .apb = 0x1188 }, /* XDMREG_PMSTAT2 */            \
 226         { .nar = 0x3b, .apb = 0x118c }, /* XDMREG_PMSTAT3 */            \
 227         { .nar = 0x3c, .apb = 0x1190 }, /* XDMREG_PMSTAT4 */            \
 228         { .nar = 0x3d, .apb = 0x1194 }, /* XDMREG_PMSTAT5 */            \
 229         { .nar = 0x3e, .apb = 0x1198 }, /* XDMREG_PMSTAT6 */            \
 230         { .nar = 0x3f, .apb = 0x119c }, /* XDMREG_PMSTAT7 */            \
 231                                                                                                                                 \
 232         /* OCD Registers */                                                                                     \
 233         { .nar = 0x40, .apb = 0x2000 }, /* XDMREG_OCDID */                      \
 234         { .nar = 0x42, .apb = 0x2008 }, /* XDMREG_DCRCLR */                     \
 235         { .nar = 0x43, .apb = 0x200c }, /* XDMREG_DCRSET */                     \
 236         { .nar = 0x44, .apb = 0x2010 }, /* XDMREG_DSR */                        \
 237         { .nar = 0x45, .apb = 0x2014 }, /* XDMREG_DDR */                        \
 238         { .nar = 0x46, .apb = 0x2018 }, /* XDMREG_DDREXEC */            \
 239         { .nar = 0x47, .apb = 0x201c }, /* XDMREG_DIR0EXEC */           \
 240         { .nar = 0x48, .apb = 0x2020 }, /* XDMREG_DIR0 */                       \
 241         { .nar = 0x49, .apb = 0x2024 }, /* XDMREG_DIR1 */                       \
 242         { .nar = 0x4a, .apb = 0x2028 }, /* XDMREG_DIR2 */                       \
 243         { .nar = 0x4b, .apb = 0x202c }, /* XDMREG_DIR3 */                       \
 244         { .nar = 0x4c, .apb = 0x2030 }, /* XDMREG_DIR4 */                       \
 245         { .nar = 0x4d, .apb = 0x2034 }, /* XDMREG_DIR5 */                       \
 246         { .nar = 0x4e, .apb = 0x2038 }, /* XDMREG_DIR6 */                       \
 247         { .nar = 0x4f, .apb = 0x203c }, /* XDMREG_DIR7 */                       \
 248                                                                                                                                 \
 249         /* Misc Registers */                                                                            \
 250         { .nar = 0x5a, .apb = 0x3028 }, /* XDMREG_ERISTAT */            \
 251                                                                                                                                 \
 252         /* CoreSight Registers */                                                                       \
 253         { .nar = 0x60, .apb = 0x3f00 }, /* XDMREG_ITCTRL */                     \
 254         { .nar = 0x68, .apb = 0x3fa0 }, /* XDMREG_CLAIMSET */           \
 255         { .nar = 0x69, .apb = 0x3fa4 }, /* XDMREG_CLAIMCLR */           \
 256         { .nar = 0x6c, .apb = 0x3fb0 }, /* XDMREG_LOCKACCESS */         \
 257         { .nar = 0x6d, .apb = 0x3fb4 }, /* XDMREG_LOCKSTATUS */         \
 258         { .nar = 0x6e, .apb = 0x3fb8 }, /* XDMREG_AUTHSTATUS */         \
 259         { .nar = 0x72, .apb = 0x3fc8 }, /* XDMREG_DEVID */                      \
 260         { .nar = 0x73, .apb = 0x3fcc }, /* XDMREG_DEVTYPE */            \
 261         { .nar = 0x74, .apb = 0x3fd0 }, /* XDMREG_PERID4 */                     \
 262         { .nar = 0x75, .apb = 0x3fd4 }, /* XDMREG_PERID5 */                     \
 263         { .nar = 0x76, .apb = 0x3fd8 }, /* XDMREG_PERID6 */                     \
 264         { .nar = 0x77, .apb = 0x3fdc }, /* XDMREG_PERID7 */                     \
 265         { .nar = 0x78, .apb = 0x3fe0 }, /* XDMREG_PERID0 */                     \
 266         { .nar = 0x79, .apb = 0x3fe4 }, /* XDMREG_PERID1 */                     \
 267         { .nar = 0x7a, .apb = 0x3fe8 }, /* XDMREG_PERID2 */                     \
 268         { .nar = 0x7b, .apb = 0x3fec }, /* XDMREG_PERID3 */                     \
 269         { .nar = 0x7c, .apb = 0x3ff0 }, /* XDMREG_COMPID0 */            \
 270         { .nar = 0x7d, .apb = 0x3ff4 }, /* XDMREG_COMPID1 */            \
 271         { .nar = 0x7e, .apb = 0x3ff8 }, /* XDMREG_COMPID2 */            \
 272         { .nar = 0x7f, .apb = 0x3ffc }, /* XDMREG_COMPID3 */            \
 273 }
 274
 275 #define XTENSA_DM_APB_ALIGN         0x4000
 276
 277 /* OCD registers, bit definitions */
 278 #define OCDDCR_ENABLEOCD            BIT(0)
 279 #define OCDDCR_DEBUGINTERRUPT       BIT(1)
 280 #define OCDDCR_INTERRUPTALLCONDS    BIT(2)
 281 #define OCDDCR_STEPREQUEST          BIT(3)              /* NX only */
 282 #define OCDDCR_BREAKINEN            BIT(16)
 283 #define OCDDCR_BREAKOUTEN           BIT(17)
 284 #define OCDDCR_DEBUGSWACTIVE        BIT(20)
 285 #define OCDDCR_RUNSTALLINEN         BIT(21)
 286 #define OCDDCR_DEBUGMODEOUTEN       BIT(22)
 287 #define OCDDCR_BREAKOUTITO          BIT(24)
 288 #define OCDDCR_BREAKACKITO          BIT(25)
 289
 290 #define OCDDSR_EXECDONE             BIT(0)
 291 #define OCDDSR_EXECEXCEPTION        BIT(1)
 292 #define OCDDSR_EXECBUSY             BIT(2)
 293 #define OCDDSR_EXECOVERRUN          BIT(3)
 294 #define OCDDSR_STOPPED              BIT(4)
 295 #define OCDDSR_STOPCAUSE            (0xF << 5)  /* NX only */
 296 #define OCDDSR_STOPCAUSE_SHIFT      (5)                 /* NX only */
 297 #define OCDDSR_COREWROTEDDR         BIT(10)
 298 #define OCDDSR_COREREADDDR          BIT(11)
 299 #define OCDDSR_HOSTWROTEDDR         BIT(14)
 300 #define OCDDSR_HOSTREADDDR          BIT(15)
 301 #define OCDDSR_DEBUGPENDBREAK       BIT(16)
 302 #define OCDDSR_DEBUGPENDHOST        BIT(17)
 303 #define OCDDSR_DEBUGPENDTRAX        BIT(18)
 304 #define OCDDSR_DEBUGINTBREAK        BIT(20)
 305 #define OCDDSR_DEBUGINTHOST         BIT(21)
 306 #define OCDDSR_DEBUGINTTRAX         BIT(22)
 307 #define OCDDSR_RUNSTALLTOGGLE       BIT(23)
 308 #define OCDDSR_RUNSTALLSAMPLE       BIT(24)
 309 #define OCDDSR_BREACKOUTACKITI      BIT(25)
 310 #define OCDDSR_BREAKINITI           BIT(26)
 311 #define OCDDSR_DBGMODPOWERON        BIT(31)
 312
 313 /* NX stop cause */
 314 #define OCDDSR_STOPCAUSE_DI         (0)         /* Debug Interrupt */
 315 #define OCDDSR_STOPCAUSE_SS         (1)         /* Single-step completed */
 316 #define OCDDSR_STOPCAUSE_IB         (2)         /* HW breakpoint (IBREAKn match) */
 317 #define OCDDSR_STOPCAUSE_B1         (4)         /* SW breakpoint (BREAK.1 instruction) */
 318 #define OCDDSR_STOPCAUSE_BN         (5)         /* SW breakpoint (BREAK.N instruction) */
 319 #define OCDDSR_STOPCAUSE_B          (6)         /* SW breakpoint (BREAK instruction) */
 320 #define OCDDSR_STOPCAUSE_DB0        (8)         /* HW watchpoint (DBREAK0 match) */
 321 #define OCDDSR_STOPCAUSE_DB1        (9)         /* HW watchpoint (DBREAK0 match) */
 322
 323 /* LX stop cause */
 324 #define DEBUGCAUSE_IC               BIT(0)      /* ICOUNT exception */
 325 #define DEBUGCAUSE_IB               BIT(1)      /* IBREAK exception */
 326 #define DEBUGCAUSE_DB               BIT(2)      /* DBREAK exception */
 327 #define DEBUGCAUSE_BI               BIT(3)      /* BREAK instruction encountered */
 328 #define DEBUGCAUSE_BN               BIT(4)      /* BREAK.N instruction encountered */
 329 #define DEBUGCAUSE_DI               BIT(5)      /* Debug Interrupt */
 330 #define DEBUGCAUSE_VALID            BIT(31)     /* Pseudo-value to trigger reread (NX only) */
 331
 332 /* TRAXID */
 333 #define TRAXID_PRODNO_TRAX          0           /* TRAXID.PRODNO value for TRAX module */
 334 #define TRAXID_PRODNO_SHIFT         28
 335 #define TRAXID_PRODNO_MASK          0xf
 336
 337 #define TRAXCTRL_TREN               BIT(0)      /* Trace enable. Tracing starts on 0->1 */
 338 #define TRAXCTRL_TRSTP              BIT(1)      /* Trace Stop. Make 1 to stop trace. */
 339 #define TRAXCTRL_PCMEN              BIT(2)      /* PC match enable */
 340 #define TRAXCTRL_PTIEN              BIT(4)      /* Processor-trigger enable */
 341 #define TRAXCTRL_CTIEN              BIT(5)      /* Cross-trigger enable */
 342 #define TRAXCTRL_TMEN               BIT(7)      /* Tracemem Enable. Always set. */
 343 #define TRAXCTRL_CNTU               BIT(9)      /* Post-stop-trigger countdown units; selects when DelayCount-- happens.
 344                                                                                          * 0 - every 32-bit word written to tracemem, 1 - every cpu instruction */
 345 #define TRAXCTRL_TSEN               BIT(11)     /* Undocumented/deprecated? */
 346 #define TRAXCTRL_SMPER_SHIFT        12          /* Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg */
 347 #define TRAXCTRL_SMPER_MASK         0x07        /* Synchronization message period */
 348 #define TRAXCTRL_PTOWT              BIT(16)     /* Processor Trigger Out (OCD halt) enabled when stop triggered */
 349 #define TRAXCTRL_PTOWS              BIT(17)     /* Processor Trigger Out (OCD halt) enabled when trace stop completes */
 350 #define TRAXCTRL_CTOWT              BIT(20)     /* Cross-trigger Out enabled when stop triggered */
 351 #define TRAXCTRL_CTOWS              BIT(21)     /* Cross-trigger Out enabled when trace stop completes */
 352 #define TRAXCTRL_ITCTO              BIT(22)     /* Integration mode: cross-trigger output */
 353 #define TRAXCTRL_ITCTIA             BIT(23)     /* Integration mode: cross-trigger ack */
 354 #define TRAXCTRL_ITATV              BIT(24)     /* replaces ATID when in integration mode: ATVALID output */
 355 #define TRAXCTRL_ATID_MASK          0x7F        /* ARB source ID */
 356 #define TRAXCTRL_ATID_SHIFT         24
 357 #define TRAXCTRL_ATEN               BIT(31)     /* ATB interface enable */
 358
 359 #define TRAXSTAT_TRACT              BIT(0)      /* Trace active flag. */
 360 #define TRAXSTAT_TRIG               BIT(1)      /* Trace stop trigger. Clears on TREN 1->0 */
 361 #define TRAXSTAT_PCMTG              BIT(2)      /* Stop trigger caused by PC match. Clears on TREN 1->0 */
 362 #define TRAXSTAT_PJTR               BIT(3)      /* JTAG transaction result. 1=err in preceding jtag transaction. */
 363 #define TRAXSTAT_PTITG              BIT(4)      /* Stop trigger caused by Processor Trigger Input.Clears on TREN 1->0 */
 364 #define TRAXSTAT_CTITG              BIT(5)      /* Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 */
 365 #define TRAXSTAT_MEMSZ_SHIFT        8           /* Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. */
 366 #define TRAXSTAT_MEMSZ_MASK         0x1F
 367 #define TRAXSTAT_PTO                BIT(16)     /* Processor Trigger Output: current value */
 368 #define TRAXSTAT_CTO                BIT(17)     /* Cross-Trigger Output: current value */
 369 #define TRAXSTAT_ITCTOA             BIT(22)     /* Cross-Trigger Out Ack: current value */
 370 #define TRAXSTAT_ITCTI              BIT(23)     /* Cross-Trigger Input: current value */
 371 #define TRAXSTAT_ITATR              BIT(24)     /* ATREADY Input: current value */
 372
 373 #define TRAXADDR_TADDR_SHIFT        0           /* Trax memory address, in 32-bit words. */
 374 #define TRAXADDR_TADDR_MASK         0x1FFFFF    /* Actually is only as big as the trace buffer size max addr. */
 375 #define TRAXADDR_TWRAP_SHIFT        21          /* Amount of times TADDR has overflown */
 376 #define TRAXADDR_TWRAP_MASK         0x3FF
 377 #define TRAXADDR_TWSAT              BIT(31)     /* 1 if TWRAP has overflown, clear by disabling tren.*/
 378
 379 #define PCMATCHCTRL_PCML_SHIFT      0           /* Amount of lower bits to ignore in pc trigger register */
 380 #define PCMATCHCTRL_PCML_MASK       0x1F
 381 #define PCMATCHCTRL_PCMS            BIT(31)     /* PC Match Sense, 0-match when procs PC is in-range, 1-match when
 382                                                                                          * out-of-range */
 383
 384 #define XTENSA_MAX_PERF_COUNTERS    2
 385 #define XTENSA_MAX_PERF_SELECT      32
 386 #define XTENSA_MAX_PERF_MASK        0xffff
 387
 388 #define XTENSA_STOPMASK_DISABLED    UINT32_MAX
 389
 390 struct xtensa_debug_module;
 391
 392 struct xtensa_debug_ops {
 393         /** enable operation */
 394         int (*queue_enable)(struct xtensa_debug_module *dm);
 395         /** register read. */
 396         int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *data);
 397         /** register write. */
 398         int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t data);
 399 };
 400
 401 /* Xtensa power registers are 8 bits wide on JTAG interfaces but 32 bits wide
 402  * when accessed via APB/DAP.  In order to use DAP queuing APIs (for optimal
 403  * performance), the XDM power register APIs take 32-bit register params.
 404  */
 405 struct xtensa_power_ops {
 406         /** register read. */
 407         int (*queue_reg_read)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint8_t *data,
 408                 uint32_t clear);
 409         /** register write. */
 410         int (*queue_reg_write)(struct xtensa_debug_module *dm, enum xtensa_dm_pwr_reg reg, uint32_t data);
 411 };
 412
 413 typedef uint32_t xtensa_pwrstat_t;
 414 typedef uint32_t xtensa_ocdid_t;
 415 typedef uint32_t xtensa_dsr_t;
 416 typedef uint32_t xtensa_traxstat_t;
 417
 418 struct xtensa_power_status {
 419         xtensa_pwrstat_t stat;
 420         xtensa_pwrstat_t stath;
 421         /* TODO: do not need to keep previous status to detect that core or debug module has been
 422          * reset, */
 423         /*       we can clear PWRSTAT_DEBUGWASRESET and PWRSTAT_COREWASRESET after reading will do
 424          * the job; */
 425         /*       upon next reet those bits will be set again. So we can get rid of
 426          *       xtensa_dm_power_status_cache_reset() and xtensa_dm_power_status_cache(). */
 427         xtensa_pwrstat_t prev_stat;
 428 };
 429
 430 struct xtensa_core_status {
 431         xtensa_dsr_t dsr;
 432 };
 433
 434 struct xtensa_trace_config {
 435         uint32_t ctrl;
 436         uint32_t memaddr_start;
 437         uint32_t memaddr_end;
 438         uint32_t addr;
 439 };
 440
 441 struct xtensa_trace_status {
 442         xtensa_traxstat_t stat;
 443 };
 444
 445 struct xtensa_trace_start_config {
 446         uint32_t stoppc;
 447         bool after_is_words;
 448         uint32_t after;
 449         uint32_t stopmask;      /* UINT32_MAX: disable PC match option */
 450 };
 451
 452 struct xtensa_perfmon_config {
 453         int select;
 454         uint32_t mask;
 455         int kernelcnt;
 456         int tracelevel;
 457 };
 458
 459 struct xtensa_perfmon_result {
 460         uint64_t value;
 461         bool overflow;
 462 };
 463
 464 struct xtensa_debug_module_config {
 465         const struct xtensa_power_ops *pwr_ops;
 466         const struct xtensa_debug_ops *dbg_ops;
 467
 468         /* Either JTAG or DAP structures will be populated */
 469         struct jtag_tap *tap;
 470         void (*queue_tdi_idle)(struct target *target);
 471         void *queue_tdi_idle_arg;
 472
 473         /* For targets conforming to ARM Debug Interface v5,
 474          * "dap" references the Debug Access Port (DAP)
 475          * used to make requests to the target;
 476          * "debug_ap" is AP instance connected to processor
 477          */
 478         struct adiv5_dap *dap;
 479         struct adiv5_ap *debug_ap;
 480         int debug_apsel;
 481         uint32_t ap_offset;
 482 };
 483
 484 struct xtensa_debug_module {
 485         const struct xtensa_power_ops *pwr_ops;
 486         const struct xtensa_debug_ops *dbg_ops;
 487
 488         /* Either JTAG or DAP structures will be populated */
 489         struct jtag_tap *tap;
 490         void (*queue_tdi_idle)(struct target *target);
 491         void *queue_tdi_idle_arg;
 492
 493         /* DAP struct; AP instance connected to processor */
 494         struct adiv5_dap *dap;
 495         struct adiv5_ap *debug_ap;
 496         int debug_apsel;
 497
 498         struct xtensa_power_status power_status;
 499         struct xtensa_core_status core_status;
 500         xtensa_ocdid_t device_id;
 501         uint32_t ap_offset;
 502 };
 503
 504 int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg);
 505 void xtensa_dm_deinit(struct xtensa_debug_module *dm);
 506 int xtensa_dm_poll(struct xtensa_debug_module *dm);
 507 int xtensa_dm_examine(struct xtensa_debug_module *dm);
 508 int xtensa_dm_queue_enable(struct xtensa_debug_module *dm);
 509 int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint8_t *value);
 510 int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, enum xtensa_dm_reg reg, uint32_t value);
 511 int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm,
 512         enum xtensa_dm_pwr_reg reg,
 513         uint8_t *data,
 514         uint32_t clear);
 515 int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm,
 516         enum xtensa_dm_pwr_reg reg,
 517         uint32_t data);
 518
 519 static inline int xtensa_dm_queue_execute(struct xtensa_debug_module *dm)
 520 {
 521         return dm->dap ? dap_run(dm->dap) : jtag_execute_queue();
 522 }
 523
 524 static inline void xtensa_dm_queue_tdi_idle(struct xtensa_debug_module *dm)
 525 {
 526         if (dm->queue_tdi_idle)
 527                 dm->queue_tdi_idle(dm->queue_tdi_idle_arg);
 528 }
 529
 530 int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear);
 531 static inline void xtensa_dm_power_status_cache_reset(struct xtensa_debug_module *dm)
 532 {
 533         dm->power_status.prev_stat = 0;
 534 }
 535 static inline void xtensa_dm_power_status_cache(struct xtensa_debug_module *dm)
 536 {
 537         dm->power_status.prev_stat = dm->power_status.stath;
 538 }
 539 static inline xtensa_pwrstat_t xtensa_dm_power_status_get(struct xtensa_debug_module *dm)
 540 {
 541         return dm->power_status.stat;
 542 }
 543
 544 int xtensa_dm_core_status_read(struct xtensa_debug_module *dm);
 545 int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits);
 546 int xtensa_dm_core_status_check(struct xtensa_debug_module *dm);
 547 static inline xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module *dm)
 548 {
 549         return dm->core_status.dsr;
 550 }
 551
 552 int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val);
 553 int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val);
 554
 555 int xtensa_dm_device_id_read(struct xtensa_debug_module *dm);
 556 static inline xtensa_ocdid_t xtensa_dm_device_id_get(struct xtensa_debug_module *dm)
 557 {
 558         return dm->device_id;
 559 }
 560
 561 int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg);
 562 int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable);
 563 int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_trace_config *config);
 564 int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_trace_status *status);
 565 int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size);
 566
 567 static inline bool xtensa_dm_is_online(struct xtensa_debug_module *dm)
 568 {
 569         int res = xtensa_dm_device_id_read(dm);
 570         if (res != ERROR_OK)
 571                 return false;
 572         return dm->device_id != 0xffffffff && dm->device_id != 0;
 573 }
 574
 575 static inline bool xtensa_dm_tap_was_reset(struct xtensa_debug_module *dm)
 576 {
 577         return !(dm->power_status.prev_stat & PWRSTAT_DEBUGWASRESET_DM(dm)) &&
 578                dm->power_status.stat & PWRSTAT_DEBUGWASRESET_DM(dm);
 579 }
 580
 581 static inline bool xtensa_dm_core_was_reset(struct xtensa_debug_module *dm)
 582 {
 583         return !(dm->power_status.prev_stat & PWRSTAT_COREWASRESET_DM(dm)) &&
 584                dm->power_status.stat & PWRSTAT_COREWASRESET_DM(dm);
 585 }
 586
 587 static inline bool xtensa_dm_core_is_stalled(struct xtensa_debug_module *dm)
 588 {
 589         return dm->core_status.dsr & OCDDSR_RUNSTALLSAMPLE;
 590 }
 591
 592 static inline bool xtensa_dm_is_powered(struct xtensa_debug_module *dm)
 593 {
 594         return dm->core_status.dsr & OCDDSR_DBGMODPOWERON;
 595 }
 596
 597 int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id,
 598         const struct xtensa_perfmon_config *config);
 599 int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id,
 600         struct xtensa_perfmon_result *out_result);
 601
 602 #endif  /* OPENOCD_TARGET_XTENSA_DEBUG_MODULE_H */