src/target/xtensa/xtensa_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Generic Xtensa target API for OpenOCD                                 *
   5  *   Copyright (C) 2016-2019 Espressif Systems Ltd.                        *
   6  *   Author: Angus Gratton gus@projectgus.com                              *
   7  ***************************************************************************/
   8
   9 #ifndef OPENOCD_TARGET_XTENSA_REGS_H
  10 #define OPENOCD_TARGET_XTENSA_REGS_H
  11
  12 struct reg_arch_type;
  13
  14 enum xtensa_reg_id {
  15         XT_REG_IDX_PC = 0,
  16         XT_REG_IDX_AR0,
  17         XT_REG_IDX_AR1,
  18         XT_REG_IDX_AR2,
  19         XT_REG_IDX_AR3,
  20         XT_REG_IDX_AR4,
  21         XT_REG_IDX_AR5,
  22         XT_REG_IDX_AR6,
  23         XT_REG_IDX_AR7,
  24         XT_REG_IDX_AR8,
  25         XT_REG_IDX_AR9,
  26         XT_REG_IDX_AR10,
  27         XT_REG_IDX_AR11,
  28         XT_REG_IDX_AR12,
  29         XT_REG_IDX_AR13,
  30         XT_REG_IDX_AR14,
  31         XT_REG_IDX_AR15,
  32         XT_REG_IDX_AR16,
  33         XT_REG_IDX_AR17,
  34         XT_REG_IDX_AR18,
  35         XT_REG_IDX_AR19,
  36         XT_REG_IDX_AR20,
  37         XT_REG_IDX_AR21,
  38         XT_REG_IDX_AR22,
  39         XT_REG_IDX_AR23,
  40         XT_REG_IDX_AR24,
  41         XT_REG_IDX_AR25,
  42         XT_REG_IDX_AR26,
  43         XT_REG_IDX_AR27,
  44         XT_REG_IDX_AR28,
  45         XT_REG_IDX_AR29,
  46         XT_REG_IDX_AR30,
  47         XT_REG_IDX_AR31,
  48         XT_REG_IDX_AR32,
  49         XT_REG_IDX_AR33,
  50         XT_REG_IDX_AR34,
  51         XT_REG_IDX_AR35,
  52         XT_REG_IDX_AR36,
  53         XT_REG_IDX_AR37,
  54         XT_REG_IDX_AR38,
  55         XT_REG_IDX_AR39,
  56         XT_REG_IDX_AR40,
  57         XT_REG_IDX_AR41,
  58         XT_REG_IDX_AR42,
  59         XT_REG_IDX_AR43,
  60         XT_REG_IDX_AR44,
  61         XT_REG_IDX_AR45,
  62         XT_REG_IDX_AR46,
  63         XT_REG_IDX_AR47,
  64         XT_REG_IDX_AR48,
  65         XT_REG_IDX_AR49,
  66         XT_REG_IDX_AR50,
  67         XT_REG_IDX_AR51,
  68         XT_REG_IDX_AR52,
  69         XT_REG_IDX_AR53,
  70         XT_REG_IDX_AR54,
  71         XT_REG_IDX_AR55,
  72         XT_REG_IDX_AR56,
  73         XT_REG_IDX_AR57,
  74         XT_REG_IDX_AR58,
  75         XT_REG_IDX_AR59,
  76         XT_REG_IDX_AR60,
  77         XT_REG_IDX_AR61,
  78         XT_REG_IDX_AR62,
  79         XT_REG_IDX_AR63,
  80         XT_REG_IDX_LBEG,
  81         XT_REG_IDX_LEND,
  82         XT_REG_IDX_LCOUNT,
  83         XT_REG_IDX_SAR,
  84         XT_REG_IDX_WINDOWBASE,
  85         XT_REG_IDX_WINDOWSTART,
  86         XT_REG_IDX_CONFIGID0,
  87         XT_REG_IDX_CONFIGID1,
  88         XT_REG_IDX_PS,
  89         XT_REG_IDX_THREADPTR,
  90         XT_REG_IDX_BR,
  91         XT_REG_IDX_SCOMPARE1,
  92         XT_REG_IDX_ACCLO,
  93         XT_REG_IDX_ACCHI,
  94         XT_REG_IDX_M0,
  95         XT_REG_IDX_M1,
  96         XT_REG_IDX_M2,
  97         XT_REG_IDX_M3,
  98         XT_REG_IDX_F0,
  99         XT_REG_IDX_F1,
 100         XT_REG_IDX_F2,
 101         XT_REG_IDX_F3,
 102         XT_REG_IDX_F4,
 103         XT_REG_IDX_F5,
 104         XT_REG_IDX_F6,
 105         XT_REG_IDX_F7,
 106         XT_REG_IDX_F8,
 107         XT_REG_IDX_F9,
 108         XT_REG_IDX_F10,
 109         XT_REG_IDX_F11,
 110         XT_REG_IDX_F12,
 111         XT_REG_IDX_F13,
 112         XT_REG_IDX_F14,
 113         XT_REG_IDX_F15,
 114         XT_REG_IDX_FCR,
 115         XT_REG_IDX_FSR,
 116         XT_REG_IDX_MMID,
 117         XT_REG_IDX_IBREAKENABLE,
 118         XT_REG_IDX_MEMCTL,
 119         XT_REG_IDX_ATOMCTL,
 120         XT_REG_IDX_IBREAKA0,
 121         XT_REG_IDX_IBREAKA1,
 122         XT_REG_IDX_DBREAKA0,
 123         XT_REG_IDX_DBREAKA1,
 124         XT_REG_IDX_DBREAKC0,
 125         XT_REG_IDX_DBREAKC1,
 126         XT_REG_IDX_EPC1,
 127         XT_REG_IDX_EPC2,
 128         XT_REG_IDX_EPC3,
 129         XT_REG_IDX_EPC4,
 130         XT_REG_IDX_EPC5,
 131         XT_REG_IDX_EPC6,
 132         XT_REG_IDX_EPC7,
 133         XT_REG_IDX_DEPC,
 134         XT_REG_IDX_EPS2,
 135         XT_REG_IDX_EPS3,
 136         XT_REG_IDX_EPS4,
 137         XT_REG_IDX_EPS5,
 138         XT_REG_IDX_EPS6,
 139         XT_REG_IDX_EPS7,
 140         XT_REG_IDX_EXCSAVE1,
 141         XT_REG_IDX_EXCSAVE2,
 142         XT_REG_IDX_EXCSAVE3,
 143         XT_REG_IDX_EXCSAVE4,
 144         XT_REG_IDX_EXCSAVE5,
 145         XT_REG_IDX_EXCSAVE6,
 146         XT_REG_IDX_EXCSAVE7,
 147         XT_REG_IDX_CPENABLE,
 148         XT_REG_IDX_INTERRUPT,
 149         XT_REG_IDX_INTSET,
 150         XT_REG_IDX_INTCLEAR,
 151         XT_REG_IDX_INTENABLE,
 152         XT_REG_IDX_VECBASE,
 153         XT_REG_IDX_EXCCAUSE,
 154         XT_REG_IDX_DEBUGCAUSE,
 155         XT_REG_IDX_CCOUNT,
 156         XT_REG_IDX_PRID,
 157         XT_REG_IDX_ICOUNT,
 158         XT_REG_IDX_ICOUNTLEVEL,
 159         XT_REG_IDX_EXCVADDR,
 160         XT_REG_IDX_CCOMPARE0,
 161         XT_REG_IDX_CCOMPARE1,
 162         XT_REG_IDX_CCOMPARE2,
 163         XT_REG_IDX_MISC0,
 164         XT_REG_IDX_MISC1,
 165         XT_REG_IDX_MISC2,
 166         XT_REG_IDX_MISC3,
 167         XT_REG_IDX_LITBASE,
 168         XT_REG_IDX_PTEVADDR,
 169         XT_REG_IDX_RASID,
 170         XT_REG_IDX_ITLBCFG,
 171         XT_REG_IDX_DTLBCFG,
 172         XT_REG_IDX_MEPC,
 173         XT_REG_IDX_MEPS,
 174         XT_REG_IDX_MESAVE,
 175         XT_REG_IDX_MESR,
 176         XT_REG_IDX_MECR,
 177         XT_REG_IDX_MEVADDR,
 178         XT_REG_IDX_A0,
 179         XT_REG_IDX_A1,
 180         XT_REG_IDX_A2,
 181         XT_REG_IDX_A3,
 182         XT_REG_IDX_A4,
 183         XT_REG_IDX_A5,
 184         XT_REG_IDX_A6,
 185         XT_REG_IDX_A7,
 186         XT_REG_IDX_A8,
 187         XT_REG_IDX_A9,
 188         XT_REG_IDX_A10,
 189         XT_REG_IDX_A11,
 190         XT_REG_IDX_A12,
 191         XT_REG_IDX_A13,
 192         XT_REG_IDX_A14,
 193         XT_REG_IDX_A15,
 194         XT_REG_IDX_PWRCTL,
 195         XT_REG_IDX_PWRSTAT,
 196         XT_REG_IDX_ERISTAT,
 197         XT_REG_IDX_CS_ITCTRL,
 198         XT_REG_IDX_CS_CLAIMSET,
 199         XT_REG_IDX_CS_CLAIMCLR,
 200         XT_REG_IDX_CS_LOCKACCESS,
 201         XT_REG_IDX_CS_LOCKSTATUS,
 202         XT_REG_IDX_CS_AUTHSTATUS,
 203         XT_REG_IDX_FAULT_INFO,
 204         XT_REG_IDX_TRAX_ID,
 205         XT_REG_IDX_TRAX_CTRL,
 206         XT_REG_IDX_TRAX_STAT,
 207         XT_REG_IDX_TRAX_DATA,
 208         XT_REG_IDX_TRAX_ADDR,
 209         XT_REG_IDX_TRAX_PCTRIGGER,
 210         XT_REG_IDX_TRAX_PCMATCH,
 211         XT_REG_IDX_TRAX_DELAY,
 212         XT_REG_IDX_TRAX_MEMSTART,
 213         XT_REG_IDX_TRAX_MEMEND,
 214         XT_REG_IDX_PMG,
 215         XT_REG_IDX_PMPC,
 216         XT_REG_IDX_PM0,
 217         XT_REG_IDX_PM1,
 218         XT_REG_IDX_PMCTRL0,
 219         XT_REG_IDX_PMCTRL1,
 220         XT_REG_IDX_PMSTAT0,
 221         XT_REG_IDX_PMSTAT1,
 222         XT_REG_IDX_OCD_ID,
 223         XT_REG_IDX_OCD_DCRCLR,
 224         XT_REG_IDX_OCD_DCRSET,
 225         XT_REG_IDX_OCD_DSR,
 226         XT_REG_IDX_OCD_DDR,
 227         XT_NUM_REGS,
 228         /* chip-specific user registers go after ISA-defined ones */
 229         XT_USR_REG_START = XT_NUM_REGS
 230 };
 231
 232 typedef uint32_t xtensa_reg_val_t;
 233
 234 enum xtensa_reg_type {
 235         XT_REG_GENERAL = 0,             /* General-purpose register; part of the windowed register set */
 236         XT_REG_USER = 1,                /* User register, needs RUR to read */
 237         XT_REG_SPECIAL = 2,             /* Special register, needs RSR to read */
 238         XT_REG_DEBUG = 3,               /* Register used for the debug interface. Don't mess with this. */
 239         XT_REG_RELGEN = 4,              /* Relative general address. Points to the absolute addresses plus the window
 240                                          *index */
 241         XT_REG_FR = 5,                  /* Floating-point register */
 242 };
 243
 244 enum xtensa_reg_flags {
 245         XT_REGF_NOREAD = 0x01,  /* Register is write-only */
 246         XT_REGF_COPROC0 = 0x02  /* Can't be read if coproc0 isn't enabled */
 247 };
 248
 249 struct xtensa_reg_desc {
 250         const char *name;
 251         unsigned int reg_num;                   /* ISA register num (meaning depends on register type) */
 252         enum xtensa_reg_type type;
 253         enum xtensa_reg_flags flags;
 254 };
 255
 256 struct xtensa_user_reg_desc {
 257         const char *name;
 258         /* ISA register num (meaning depends on register type) */
 259         unsigned int reg_num;
 260         enum xtensa_reg_flags flags;
 261         uint32_t size;
 262         const struct reg_arch_type *type;
 263 };
 264
 265 extern const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
 266
 267 #endif  /* OPENOCD_TARGET_XTENSA_REGS_H */