src/target/xtensa/xtensa_regs.h

   1 /***************************************************************************
   2  *   Generic Xtensa target API for OpenOCD                                 *
   3  *   Copyright (C) 2016-2019 Espressif Systems Ltd.                        *
   4  *   Author: Angus Gratton gus@projectgus.com                              *
   5  *   Author: Jeroen Domburg <jeroen@espressif.com>                         *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  19  ***************************************************************************/
  20 #ifndef OPENOCD_TARGET_XTENSA_REGS_H
  21 #define OPENOCD_TARGET_XTENSA_REGS_H
  22
  23 struct reg_arch_type;
  24
  25 enum xtensa_reg_id {
  26         XT_REG_IDX_PC = 0,
  27         XT_REG_IDX_AR0,
  28         XT_REG_IDX_AR1,
  29         XT_REG_IDX_AR2,
  30         XT_REG_IDX_AR3,
  31         XT_REG_IDX_AR4,
  32         XT_REG_IDX_AR5,
  33         XT_REG_IDX_AR6,
  34         XT_REG_IDX_AR7,
  35         XT_REG_IDX_AR8,
  36         XT_REG_IDX_AR9,
  37         XT_REG_IDX_AR10,
  38         XT_REG_IDX_AR11,
  39         XT_REG_IDX_AR12,
  40         XT_REG_IDX_AR13,
  41         XT_REG_IDX_AR14,
  42         XT_REG_IDX_AR15,
  43         XT_REG_IDX_AR16,
  44         XT_REG_IDX_AR17,
  45         XT_REG_IDX_AR18,
  46         XT_REG_IDX_AR19,
  47         XT_REG_IDX_AR20,
  48         XT_REG_IDX_AR21,
  49         XT_REG_IDX_AR22,
  50         XT_REG_IDX_AR23,
  51         XT_REG_IDX_AR24,
  52         XT_REG_IDX_AR25,
  53         XT_REG_IDX_AR26,
  54         XT_REG_IDX_AR27,
  55         XT_REG_IDX_AR28,
  56         XT_REG_IDX_AR29,
  57         XT_REG_IDX_AR30,
  58         XT_REG_IDX_AR31,
  59         XT_REG_IDX_AR32,
  60         XT_REG_IDX_AR33,
  61         XT_REG_IDX_AR34,
  62         XT_REG_IDX_AR35,
  63         XT_REG_IDX_AR36,
  64         XT_REG_IDX_AR37,
  65         XT_REG_IDX_AR38,
  66         XT_REG_IDX_AR39,
  67         XT_REG_IDX_AR40,
  68         XT_REG_IDX_AR41,
  69         XT_REG_IDX_AR42,
  70         XT_REG_IDX_AR43,
  71         XT_REG_IDX_AR44,
  72         XT_REG_IDX_AR45,
  73         XT_REG_IDX_AR46,
  74         XT_REG_IDX_AR47,
  75         XT_REG_IDX_AR48,
  76         XT_REG_IDX_AR49,
  77         XT_REG_IDX_AR50,
  78         XT_REG_IDX_AR51,
  79         XT_REG_IDX_AR52,
  80         XT_REG_IDX_AR53,
  81         XT_REG_IDX_AR54,
  82         XT_REG_IDX_AR55,
  83         XT_REG_IDX_AR56,
  84         XT_REG_IDX_AR57,
  85         XT_REG_IDX_AR58,
  86         XT_REG_IDX_AR59,
  87         XT_REG_IDX_AR60,
  88         XT_REG_IDX_AR61,
  89         XT_REG_IDX_AR62,
  90         XT_REG_IDX_AR63,
  91         XT_REG_IDX_LBEG,
  92         XT_REG_IDX_LEND,
  93         XT_REG_IDX_LCOUNT,
  94         XT_REG_IDX_SAR,
  95         XT_REG_IDX_WINDOWBASE,
  96         XT_REG_IDX_WINDOWSTART,
  97         XT_REG_IDX_CONFIGID0,
  98         XT_REG_IDX_CONFIGID1,
  99         XT_REG_IDX_PS,
 100         XT_REG_IDX_THREADPTR,
 101         XT_REG_IDX_BR,
 102         XT_REG_IDX_SCOMPARE1,
 103         XT_REG_IDX_ACCLO,
 104         XT_REG_IDX_ACCHI,
 105         XT_REG_IDX_M0,
 106         XT_REG_IDX_M1,
 107         XT_REG_IDX_M2,
 108         XT_REG_IDX_M3,
 109         XT_REG_IDX_F0,
 110         XT_REG_IDX_F1,
 111         XT_REG_IDX_F2,
 112         XT_REG_IDX_F3,
 113         XT_REG_IDX_F4,
 114         XT_REG_IDX_F5,
 115         XT_REG_IDX_F6,
 116         XT_REG_IDX_F7,
 117         XT_REG_IDX_F8,
 118         XT_REG_IDX_F9,
 119         XT_REG_IDX_F10,
 120         XT_REG_IDX_F11,
 121         XT_REG_IDX_F12,
 122         XT_REG_IDX_F13,
 123         XT_REG_IDX_F14,
 124         XT_REG_IDX_F15,
 125         XT_REG_IDX_FCR,
 126         XT_REG_IDX_FSR,
 127         XT_REG_IDX_MMID,
 128         XT_REG_IDX_IBREAKENABLE,
 129         XT_REG_IDX_MEMCTL,
 130         XT_REG_IDX_ATOMCTL,
 131         XT_REG_IDX_IBREAKA0,
 132         XT_REG_IDX_IBREAKA1,
 133         XT_REG_IDX_DBREAKA0,
 134         XT_REG_IDX_DBREAKA1,
 135         XT_REG_IDX_DBREAKC0,
 136         XT_REG_IDX_DBREAKC1,
 137         XT_REG_IDX_EPC1,
 138         XT_REG_IDX_EPC2,
 139         XT_REG_IDX_EPC3,
 140         XT_REG_IDX_EPC4,
 141         XT_REG_IDX_EPC5,
 142         XT_REG_IDX_EPC6,
 143         XT_REG_IDX_EPC7,
 144         XT_REG_IDX_DEPC,
 145         XT_REG_IDX_EPS2,
 146         XT_REG_IDX_EPS3,
 147         XT_REG_IDX_EPS4,
 148         XT_REG_IDX_EPS5,
 149         XT_REG_IDX_EPS6,
 150         XT_REG_IDX_EPS7,
 151         XT_REG_IDX_EXCSAVE1,
 152         XT_REG_IDX_EXCSAVE2,
 153         XT_REG_IDX_EXCSAVE3,
 154         XT_REG_IDX_EXCSAVE4,
 155         XT_REG_IDX_EXCSAVE5,
 156         XT_REG_IDX_EXCSAVE6,
 157         XT_REG_IDX_EXCSAVE7,
 158         XT_REG_IDX_CPENABLE,
 159         XT_REG_IDX_INTERRUPT,
 160         XT_REG_IDX_INTSET,
 161         XT_REG_IDX_INTCLEAR,
 162         XT_REG_IDX_INTENABLE,
 163         XT_REG_IDX_VECBASE,
 164         XT_REG_IDX_EXCCAUSE,
 165         XT_REG_IDX_DEBUGCAUSE,
 166         XT_REG_IDX_CCOUNT,
 167         XT_REG_IDX_PRID,
 168         XT_REG_IDX_ICOUNT,
 169         XT_REG_IDX_ICOUNTLEVEL,
 170         XT_REG_IDX_EXCVADDR,
 171         XT_REG_IDX_CCOMPARE0,
 172         XT_REG_IDX_CCOMPARE1,
 173         XT_REG_IDX_CCOMPARE2,
 174         XT_REG_IDX_MISC0,
 175         XT_REG_IDX_MISC1,
 176         XT_REG_IDX_MISC2,
 177         XT_REG_IDX_MISC3,
 178         XT_REG_IDX_LITBASE,
 179         XT_REG_IDX_PTEVADDR,
 180         XT_REG_IDX_RASID,
 181         XT_REG_IDX_ITLBCFG,
 182         XT_REG_IDX_DTLBCFG,
 183         XT_REG_IDX_MEPC,
 184         XT_REG_IDX_MEPS,
 185         XT_REG_IDX_MESAVE,
 186         XT_REG_IDX_MESR,
 187         XT_REG_IDX_MECR,
 188         XT_REG_IDX_MEVADDR,
 189         XT_REG_IDX_A0,
 190         XT_REG_IDX_A1,
 191         XT_REG_IDX_A2,
 192         XT_REG_IDX_A3,
 193         XT_REG_IDX_A4,
 194         XT_REG_IDX_A5,
 195         XT_REG_IDX_A6,
 196         XT_REG_IDX_A7,
 197         XT_REG_IDX_A8,
 198         XT_REG_IDX_A9,
 199         XT_REG_IDX_A10,
 200         XT_REG_IDX_A11,
 201         XT_REG_IDX_A12,
 202         XT_REG_IDX_A13,
 203         XT_REG_IDX_A14,
 204         XT_REG_IDX_A15,
 205         XT_REG_IDX_PWRCTL,
 206         XT_REG_IDX_PWRSTAT,
 207         XT_REG_IDX_ERISTAT,
 208         XT_REG_IDX_CS_ITCTRL,
 209         XT_REG_IDX_CS_CLAIMSET,
 210         XT_REG_IDX_CS_CLAIMCLR,
 211         XT_REG_IDX_CS_LOCKACCESS,
 212         XT_REG_IDX_CS_LOCKSTATUS,
 213         XT_REG_IDX_CS_AUTHSTATUS,
 214         XT_REG_IDX_FAULT_INFO,
 215         XT_REG_IDX_TRAX_ID,
 216         XT_REG_IDX_TRAX_CTRL,
 217         XT_REG_IDX_TRAX_STAT,
 218         XT_REG_IDX_TRAX_DATA,
 219         XT_REG_IDX_TRAX_ADDR,
 220         XT_REG_IDX_TRAX_PCTRIGGER,
 221         XT_REG_IDX_TRAX_PCMATCH,
 222         XT_REG_IDX_TRAX_DELAY,
 223         XT_REG_IDX_TRAX_MEMSTART,
 224         XT_REG_IDX_TRAX_MEMEND,
 225         XT_REG_IDX_PMG,
 226         XT_REG_IDX_PMPC,
 227         XT_REG_IDX_PM0,
 228         XT_REG_IDX_PM1,
 229         XT_REG_IDX_PMCTRL0,
 230         XT_REG_IDX_PMCTRL1,
 231         XT_REG_IDX_PMSTAT0,
 232         XT_REG_IDX_PMSTAT1,
 233         XT_REG_IDX_OCD_ID,
 234         XT_REG_IDX_OCD_DCRCLR,
 235         XT_REG_IDX_OCD_DCRSET,
 236         XT_REG_IDX_OCD_DSR,
 237         XT_REG_IDX_OCD_DDR,
 238         XT_NUM_REGS,
 239         /* chip-specific user registers go after ISA-defined ones */
 240         XT_USR_REG_START = XT_NUM_REGS
 241 };
 242
 243 typedef uint32_t xtensa_reg_val_t;
 244
 245 enum xtensa_reg_type {
 246         XT_REG_GENERAL = 0,             /* General-purpose register; part of the windowed register set */
 247         XT_REG_USER = 1,                /* User register, needs RUR to read */
 248         XT_REG_SPECIAL = 2,             /* Special register, needs RSR to read */
 249         XT_REG_DEBUG = 3,               /* Register used for the debug interface. Don't mess with this. */
 250         XT_REG_RELGEN = 4,              /* Relative general address. Points to the absolute addresses plus the window
 251                                          *index */
 252         XT_REG_FR = 5,                  /* Floating-point register */
 253 };
 254
 255 enum xtensa_reg_flags {
 256         XT_REGF_NOREAD = 0x01,  /* Register is write-only */
 257         XT_REGF_COPROC0 = 0x02  /* Can't be read if coproc0 isn't enabled */
 258 };
 259
 260 struct xtensa_reg_desc {
 261         const char *name;
 262         unsigned int reg_num;                   /* ISA register num (meaning depends on register type) */
 263         enum xtensa_reg_type type;
 264         enum xtensa_reg_flags flags;
 265 };
 266
 267 struct xtensa_user_reg_desc {
 268         const char *name;
 269         /* ISA register num (meaning depends on register type) */
 270         unsigned int reg_num;
 271         enum xtensa_reg_flags flags;
 272         uint32_t size;
 273         const struct reg_arch_type *type;
 274 };
 275
 276 extern const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
 277
 278 #endif  /* OPENOCD_TARGET_XTENSA_REGS_H */