tcl/board/alphascale_asm9260_ek.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 source [find target/alphascale_asm9260t.cfg]
   4
   5 reset_config trst_and_srst
   6
   7 $_TARGETNAME configure -event reset-init {
   8         echo "Configure clock"
   9         # Enable SRAM clk
  10         mww 0x80040024 0x4
  11         # Enable IRQ clk
  12         mww 0x80040034 0x100
  13         # Enable DMA0,1 clk
  14         mww 0x80040024 0x600
  15         # Make sysre syspll is enabled
  16         mww 0x80040238 0x750
  17         #CPU = PLLCLK/2
  18         mww 0x8004017C 0x2
  19         #SYSAHBCLK = CPUCLK/2
  20         mww 0x80040180 0x2
  21         # Set PLL freq to 480MHz
  22         mww 0x80040100 480
  23         # normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
  24         sleep 100
  25
  26         # select PLL as main source
  27         mww 0x80040120 0x1
  28         # disable and enable main clk to update changes?
  29         mww 0x80040124 0x0
  30         mww 0x80040124 0x1
  31
  32         echo "Configure memory"
  33         #enable EMI CLK
  34         mww 0x80040024 0x40
  35
  36         # configure memory controller for internal SRAM
  37         mww 0x80700000 0x1188
  38         # change default emi clk delay
  39         mww 0x8004034C 0xA0503
  40         # make sure chip_select_register2_low has correct value (why?)
  41         mww 0x8070001c 0x20000000
  42         # set type to sdram and size to 32MB
  43         mww 0x8070005c 0xa
  44         # configure internal SDRAM timing
  45         mww 0x80700004 0x024996d9
  46         # configure Static Memory timing
  47         mww 0x80700094 0x00542b4f
  48
  49         echo "Configure uart4"
  50         # enable pinctrl clk
  51         mww 0x80040024 0x2000000
  52         # mux GPIO3_0 and GPIO3_1 to UART4
  53         mww 0x80044060 0x2
  54         mww 0x80044064 0x2
  55         # configure UART4CLKDIV
  56         mww 0x800401a8 0x1
  57         # enable uart4 clk
  58         mww 0x80040024 0x8000
  59         # clear softrst and clkgate on uart4
  60         mww 0x80010008 0xC0000000
  61         # set bandrate 115200 12M
  62         mww 0x80010030 0x00062070
  63         # enable Rx&Tx
  64         mww 0x80010024 0x301
  65         # clear hw control
  66         mww 0x80010028 0xc000
  67 }
  68
  69 $_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
  70 $_TARGETNAME arm7_9 fast_memory_access enable
  71 $_TARGETNAME arm7_9 dcc_downloads enable