tcl/board/at91cap7a-stk-sdram.cfg

   1 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
   2 #
   3 # use combined on interfaces or targets that can't set TRST/SRST separately
   4 reset_config trst_and_srst srst_pulls_trst
   5
   6 if { [info exists CHIPNAME] } {
   7    set  _CHIPNAME $CHIPNAME
   8 } else {
   9    set  _CHIPNAME cap7
  10 }
  11
  12 if { [info exists ENDIAN] } {
  13    set  _ENDIAN $ENDIAN
  14 } else {
  15    set  _ENDIAN little
  16 }
  17
  18 if { [info exists CPUTAPID] } {
  19    set _CPUTAPID $CPUTAPID
  20 } else {
  21    set _CPUTAPID 0x40700f0f
  22 }
  23
  24 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  25
  26 set _TARGETNAME $_CHIPNAME.cpu
  27 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
  28
  29 $_TARGETNAME configure -event reset-start {
  30         # start off real slow when we're running off internal RC oscillator
  31         adapter speed 32
  32 }
  33
  34 proc peek32 {address} {
  35         return [read_memory $address 32 1]
  36 }
  37
  38 # Wait for an expression to be true with a timeout
  39 proc wait_state {expression} {
  40         for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
  41                 if {[uplevel 1 $expression] == 0} {
  42                         return
  43                 }
  44         }
  45         return -code 1 "Timed out"
  46 }
  47
  48 # Use a global variable here to be able to tinker interactively with
  49 # post reset jtag frequency.
  50 global post_reset_khz
  51 # Danger!!!! Even 16MHz kinda works with this target, but
  52 # it needs to be as low as 2000kHz to be stable.
  53 set post_reset_khz 2000
  54
  55 $_TARGETNAME configure -event reset-init {
  56         echo "Configuring master clock"
  57         # disable watchdog
  58         mww 0xfffffd44 0xff008000
  59         # enable user reset
  60         mww 0xfffffd08 0xa5000001
  61         # Enable main oscillator
  62         mww 0xFFFFFc20  0x00000f01
  63         wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
  64
  65         # Set PLLA to 96MHz
  66         mww 0xFFFFFc28 0x20072801
  67         wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
  68
  69         # Select prescaler
  70         mww 0xFFFFFC30 0x00000004
  71         wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  72
  73         # Select master clock to 48MHz
  74         mww 0xFFFFFC30 0x00000006
  75         wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  76
  77         echo "Master clock ok."
  78
  79         # Now that we're up and running, crank up speed!
  80         global post_reset_khz ; adapter speed $post_reset_khz
  81
  82         echo "Configuring the SDRAM controller..."
  83
  84         # Configure EBI Chip select for SDRAM
  85         mww 0xFFFFEF30 0x00000102
  86
  87         # Enable clock on EBI PIOs
  88         mww 0xFFFFFC10 0x00000004
  89
  90         # Configure PIO for SDRAM
  91         mww 0xFFFFF470 0xFFFF0000
  92         mww 0xFFFFF474 0x00000000
  93         mww 0xFFFFF404 0xFFFF0000
  94
  95         # Configure SDRAMC CR
  96         mww 0xFFFFEA08 0xA63392F9
  97
  98         # NOP command
  99         mww 0xFFFFEA00 0x1
 100         mww 0x20000000 0
 101
 102         # Precharge All Banks command
 103         mww 0xFFFFEA00 0x2
 104         mww 0x20000000 0
 105
 106         # Set 1st CBR
 107         mww 0xFFFFEA00 0x00000004
 108         mww 0x20000010 0x00000001
 109
 110         # Set 2nd CBR
 111         mww 0xFFFFEA00 0x00000004
 112         mww 0x20000020 0x00000002
 113
 114         # Set 3rd CBR
 115         mww 0xFFFFEA00 0x00000004
 116         mww 0x20000030 0x00000003
 117
 118         # Set 4th CBR
 119         mww 0xFFFFEA00 0x00000004
 120         mww 0x20000040 0x00000004
 121
 122         # Set 5th CBR
 123         mww 0xFFFFEA00 0x00000004
 124         mww 0x20000050 0x00000005
 125
 126         # Set 6th CBR
 127         mww 0xFFFFEA00 0x00000004
 128         mww 0x20000060 0x00000006
 129
 130         # Set 7th CBR
 131         mww 0xFFFFEA00 0x00000004
 132         mww 0x20000070 0x00000007
 133
 134         # Set 8th CBR
 135         mww 0xFFFFEA00 0x00000004
 136         mww 0x20000080 0x00000008
 137
 138         # Set LMR operation
 139         mww 0xFFFFEA00 0x00000003
 140
 141         # Perform LMR burst=1, lat=2
 142         mww 0x20000020 0xCAFEDEDE
 143
 144         # Set Refresh Timer
 145         mww 0xFFFFEA04 0x00000203
 146
 147         # Set Normal mode
 148         mww 0xFFFFEA00 0x00000000
 149         mww 0x20000000 0x00000000
 150
 151         #remap internal memory at address 0x0
 152         mww 0xffffef00 0x3
 153
 154         echo "SDRAM configuration ok."
 155 }
 156
 157 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 158
 159 arm7_9 dcc_downloads enable
 160 arm7_9 fast_memory_access enable
 161
 162 #set _FLASHNAME $_CHIPNAME.flash
 163 #flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432