tcl/board/at91rm9200-ek.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   5 #
   6 # under GPLv2 Only
   7 #
   8 # This is for the "at91rm9200-ek" eval board.
   9 #
  10 #
  11 # It has atmel at91rm9200 chip.
  12 source [find target/at91rm9200.cfg]
  13
  14 reset_config trst_and_srst
  15
  16 $_TARGETNAME configure -event gdb-attach { reset init }
  17 $_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
  18
  19 ## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
  20 set _FLASHNAME $_CHIPNAME.flash
  21 flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
  22
  23 # The chip may run @ 32khz, so set a really low JTAG speed
  24 adapter speed 8
  25
  26 proc at91rm9200_ek_init { } {
  27         # Try to run at 1khz... Yea, that slow!
  28         # Chip is really running @ 32khz
  29         adapter speed 8
  30
  31         mww 0xfffffc64 0xffffffff
  32         ## disable all clocks but system clock
  33         mww 0xfffffc04 0xfffffffe
  34         ## disable all clocks to pioa and piob
  35         mww 0xfffffc14 0xffffffc3
  36         ## master clock = slow cpu = slow
  37         ## (means the CPU is running at 32khz!)
  38         mww 0xfffffc30 0
  39         ## main osc enable
  40         mww 0xfffffc20 0x0000ff01
  41         ## MC_PUP
  42         mww 0xFFFFFF50 0x00000000
  43         ## MC_PUER: Memory controller protection unit disable
  44         mww 0xFFFFFF54 0x00000000
  45         ## EBI_CFGR
  46         mww 0xFFFFFF64 0x00000000
  47         ## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
  48         mww 0xFFFFFF70 0x00003284
  49
  50         ## Init Clocks
  51         ## CKGR_PLLAR
  52         mww 0xFFFFFC28 0x2000BF05
  53         ## PLLAR: 179,712000 MHz for PCK
  54         mww 0xFFFFFC28 0x20263E04
  55         sleep 100
  56         ## PMC_MCKR
  57         mww 0xFFFFFC30 0x00000100
  58         sleep 100
  59         ## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
  60         mww 0xFFFFFC30 0x00000202
  61         sleep 100
  62
  63         #========================================
  64         # CPU now runs at 180mhz
  65         # SYS runs at 60mhz.
  66         adapter speed 40000
  67         #========================================
  68
  69         ## Init SDRAM
  70         ## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
  71         mww 0xFFFFF870 0xFFFF0000
  72         ## PIOC_BSR:
  73         mww 0xFFFFF874 0x00000000
  74         ## PIOC_PDR:
  75         mww 0xFFFFF804 0xFFFF0000
  76         ## EBI_CSA : CS1=SDRAM
  77         mww 0xFFFFFF60 0x00000002
  78         ## EBI_CFGR:
  79         mww 0xFFFFFF64 0x00000000
  80         ## SDRC_CR :
  81         mww 0xFFFFFF98 0x2188c155
  82         ## SDRC_MR : Precharge All
  83         mww 0xFFFFFF90 0x00000002
  84         ## access SDRAM
  85         mww 0x20000000 0x00000000
  86         ## SDRC_MR : Refresh
  87         mww 0xFFFFFF90 0x00000004
  88         ## access SDRAM
  89         mww 0x20000000 0x00000000
  90         ## access SDRAM
  91         mww 0x20000000 0x00000000
  92         ## access SDRAM
  93         mww 0x20000000 0x00000000
  94         ## access SDRAM
  95         mww 0x20000000 0x00000000
  96         ## access SDRAM
  97         mww 0x20000000 0x00000000
  98         ## access SDRAM
  99         mww 0x20000000 0x00000000
 100         ## access SDRAM
 101         mww 0x20000000 0x00000000
 102         ## access SDRAM
 103         mww 0x20000000 0x00000000
 104         ## SDRC_MR : Load Mode Register
 105         mww 0xFFFFFF90 0x00000003
 106         ## access SDRAM
 107         mww 0x20000080 0x00000000
 108         ## SDRC_TR : Write refresh rate
 109         mww 0xFFFFFF94 0x000002E0
 110         ## access SDRAM
 111         mww 0x20000000 0x00000000
 112         ## SDRC_MR : Normal Mode
 113         mww 0xFFFFFF90 0x00000000
 114         ## access SDRAM
 115         mww 0x20000000 0x00000000
 116 }