tcl/board/at91sam9g20-ek.cfg

   1 #################################################################################################
   2 #                                                                                               #
   3 # Author: Gary Carlson (gcarlson@carlson-minot.com)                                             #
   4 # Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8.   #
   5 #                                                                                               #
   6 #################################################################################################
   7
   8 # FIXME use some standard target config, maybe create one from this
   9 #
  10 #       source [find target/...cfg]
  11
  12 source [find target/at91sam9g20.cfg]
  13
  14 set _FLASHTYPE nandflash_cs3
  15
  16 # Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  Therefore
  17 # the reset needs to be configured for "srst_only".  If for some reason, a zero-ohm jumper is
  18 # added to the board to connect the trst signal, then this parameter may need to be changed.
  19
  20 reset_config srst_only
  21
  22 adapter srst delay 200
  23 jtag_ntrst_delay 200
  24
  25 # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
  26 # AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
  27 # some powerful features, we want to have a special function that handles "reset init".  To do this we declare
  28 # an event handler where these special activities can take place.
  29
  30 scan_chain
  31 $_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
  32 $_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
  33
  34 # NandFlash configuration and definition
  35
  36 nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
  37 at91sam9 cle 0 22
  38 at91sam9 ale 0 21
  39 at91sam9 rdy_busy 0 0xfffff800 13
  40 at91sam9 ce 0 0xfffff800 14
  41
  42 proc read_register {register} {
  43         return [read_memory $register 32 1]
  44 }
  45
  46 proc at91sam9g20_reset_start { } {
  47
  48         # Make sure that the the jtag is running slow, since there are a number of different ways the board
  49         # can be configured coming into this state that can cause communication problems with the jtag
  50         # adapter.  Also since this call can be made following a "reset init" where fast memory accesses
  51         # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
  52         # jtag speed without causing GDB keep alive problem.
  53
  54         arm7_9 fast_memory_access disable
  55         adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
  56         halt                            ;# Make sure processor is halted, or error will result in following steps.
  57         wait_halt 10000
  58         mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
  59 }
  60
  61 proc at91sam9g20_reset_init { } {
  62
  63         # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
  64         # a number of steps that must be carefully performed.  The process outline below follows the
  65         # recommended procedure outlined in the AT91SAM9G20 technical manual.
  66         #
  67         # Several key and very important things to keep in mind:
  68         # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
  69         # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
  70         # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
  71
  72         mww 0xfffffd44 0x00008000       ;# WDT_MR : disable watchdog.
  73
  74         # Enable the main 18.432 MHz oscillator in CKGR_MOR register.
  75         # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
  76
  77         mww 0xfffffc20 0x00004001
  78         while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
  79
  80         # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
  81         # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
  82
  83         mww 0xfffffc28 0x202a3f01
  84         while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
  85
  86         # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
  87         # Wait for MCKRDY signal from PMC_SR to assert.
  88
  89         mww 0xfffffc30 0x00000101
  90         while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
  91
  92         # Now change PMC_MCKR register to select PLLA.
  93         # Wait for MCKRDY signal from PMC_SR to assert.
  94
  95         mww 0xfffffc30 0x00001302
  96         while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
  97
  98         # Processor and master clocks are now operating and stable at maximum frequency possible:
  99         #       -> MCLK = 132.096 MHz
 100         #       -> PCLK = 396.288 MHz
 101
 102         # Switch over to adaptive clocking.
 103
 104         adapter speed 0
 105
 106         # Enable faster DCC downloads and memory accesses.
 107
 108         arm7_9 dcc_downloads enable
 109         arm7_9 fast_memory_access enable
 110
 111         # To be able to use external SDRAM, several peripheral configuration registers must
 112         # be modified.  The first change is made to PIO_ASR to select peripheral functions
 113         # for D15 through D31.  The second change is made to the PIO_PDR register to disable
 114         # this for D15 through D31.
 115
 116         mww 0xfffff870 0xffff0000
 117         mww 0xfffff804 0xffff0000
 118
 119         # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
 120         # using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
 121         # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
 122
 123         mww 0xffffef1c 0x000100a
 124
 125         # The AT91SAM9G20-EK evaluation board has built-in NandFlash.  The exact physical timing characteristics
 126         # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
 127         # a number of registers.  The first step involves setting up the general I/O pins on the processor
 128         # to be able to interface and support the external memory.
 129
 130         mww 0xfffffc10 0x00000010       ;# PMC_PCER : enable PIOC clock
 131         mww 0xfffff800 0x00006000       ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
 132         mww 0xfffff810 0x00004000       ;# PIOC_OER : enable output on 14
 133         mww 0xfffff814 0x00002000       ;# PIOC_ODR : disable output on 13
 134         mww 0xfffff830 0x00004000       ;# PIOC_SODR : set 14 to disable NAND
 135
 136         # The exact physical timing characteristics for the memory type used on the current board
 137         # (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
 138         # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
 139         # is a little tedious to do here.  If you have questions about how to do this, Atmel has
 140         # a decent application note #6255B that covers this process.
 141
 142         mww 0xffffec30 0x00020002       ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
 143         mww 0xffffec34 0x04040404       ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
 144         mww 0xffffec38 0x00070006       ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
 145         mww 0xffffec3C 0x00020003       ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
 146
 147         mww 0xffffe800 0x00000001       ;# ECC_CR : reset the ECC parity registers
 148         mww 0xffffe804 0x00000002       ;# ECC_MR : page size is 2112 words (word is 8 bits)
 149
 150         # Identify NandFlash bank 0.
 151
 152         nand probe nandflash_cs3
 153
 154         # The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
 155
 156         # Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
 157         # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
 158         # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
 159         # into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
 160         # of 132.096 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
 161         #
 162         #       CAS latency = 3 cycles
 163         #       TXSR = 10 cycles
 164         #       TRAS = 6 cycles
 165         #       TRCD = 3 cycles
 166         #       TRP = 3 cycles
 167         #       TRC = 9 cycles
 168         #       TWR = 2 cycles
 169         #       9 column, 13 row, 4 banks
 170         #       refresh equal to or less then 7.8 us for commercial/industrial rated devices
 171         #
 172         #       Thus SDRAM_CR = 0xa6339279
 173
 174         mww 0xffffea08 0xa6339279
 175
 176         # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
 177         # the starting memory location for the SDRAM.
 178
 179         mww 0xffffea00 0x00000001
 180         mww 0x20000000 0
 181
 182         # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
 183         # value into the starting memory location for the SDRAM.
 184
 185         mww 0xffffea00 0x00000002
 186         mww 0x20000000 0
 187
 188         # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
 189         # zero values eight times into the starting memory location for the SDRAM.
 190
 191         mww 0xffffea00 0x4
 192         mww 0x20000000 0
 193         mww 0x20000000 0
 194         mww 0x20000000 0
 195         mww 0x20000000 0
 196         mww 0x20000000 0
 197         mww 0x20000000 0
 198         mww 0x20000000 0
 199         mww 0x20000000 0
 200
 201         # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
 202         # the starting memory location for the SDRAM.
 203
 204         mww 0xffffea00 0x3
 205         mww 0x20000000 0
 206
 207         # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
 208         # memory location for the SDRAM.
 209
 210         mww 0xffffea00 0x0
 211         mww 0x20000000 0
 212
 213         # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
 214
 215         mww 0xffffea04 0x0000039c
 216 }