tcl/board/csb337.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # Cogent CSB337
   4 #   http://cogcomp.com/csb_csb337.htm
   5
   6 source [find target/at91rm9200.cfg]
   7
   8 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
   9 set _FLASHNAME $_CHIPNAME.flash
  10 flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
  11
  12 # ETM9 trace port connector present on this board, 16 data pins.
  13 if { [info exists ETM_DRIVER] } {
  14         etm config $_TARGETNAME 16 normal half $ETM_DRIVER
  15         # OpenOCD may someday support a real trace port driver...
  16         # system config file would need to configure it.
  17 } else {
  18         etm config $_TARGETNAME 16 normal half dummy
  19         etm_dummy config $_TARGETNAME
  20 }
  21
  22 proc csb337_clk_init { } {
  23         # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
  24         adapter speed 8
  25
  26         # CKGR_MOR:  start main oscillator (3.6864 MHz)
  27         mww 0xfffffc20 0xff01
  28         sleep 10
  29
  30         # CKGR_PLLAR:  start PLL A for CPU and peripherals (184.32 MHz)
  31         mww 0xfffffc28 0x20313e01
  32         # CKGR_PLLBR:  start PLL B for USB timing (96 MHz, with div2)
  33         mww 0xfffffc2c 0x12703e18
  34         # let PLLs lock
  35         sleep 10
  36
  37         # PMC_MCKR:  switch to CPU clock = PLLA, master clock = CPU/4
  38         mww 0xfffffc30 0x0302
  39         sleep 20
  40
  41         # CPU is in Normal Mode ... allows faster JTAG clock speed
  42         adapter speed 40000
  43 }
  44
  45 proc csb337_nor_init { } {
  46         # SMC_CSR0:  adjust timings (10 wait states)
  47         mww 0xffffff70 0x1100318a
  48
  49         flash probe 0
  50 }
  51
  52 proc csb337_sdram_init { } {
  53         # enable PIOC clock
  54         mww 0xfffffc10 0x0010
  55         # PC31..PC16 are D31..D16, with internal pullups like D15..D0
  56         mww 0xfffff870 0xffff0000
  57         mww 0xfffff874 0x0
  58         mww 0xfffff804 0xffff0000
  59
  60         # SDRC_CR: set timings
  61         mww 0xffffff98 0x2188b0d5
  62
  63         # SDRC_MR: issue all banks precharge to SDRAM
  64         mww 0xffffff90 2
  65         mww 0x20000000 0
  66
  67         # SDRC_MR: 8 autorefresh cycles
  68         mww 0xffffff90 4
  69         mww 0x20000000 0
  70         mww 0x20000000 0
  71         mww 0x20000000 0
  72         mww 0x20000000 0
  73         mww 0x20000000 0
  74         mww 0x20000000 0
  75         mww 0x20000000 0
  76         mww 0x20000000 0
  77
  78         # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
  79         mww 0xffffff90 3
  80         mww 0x20000080 0
  81
  82         # SDRC_TR: set refresh rate
  83         mww 0xffffff94 0x200
  84         mww 0x20000000 0
  85
  86         # SDRC_MR: normal mode, 32 bit bus
  87         mww 0xffffff90 0
  88         mww 0x20000000 0
  89 }
  90
  91 # The rm9200 chip has just been reset.  Bring it up far enough
  92 # that we can write flash or run code from SDRAM.
  93 proc csb337_reset_init { } {
  94         csb337_clk_init
  95
  96         # EBI_CSA:  CS0 = NOR, CS1 = SDRAM
  97         mww 0xffffff60 0x02
  98
  99         csb337_nor_init
 100         csb337_sdram_init
 101
 102         # Update CP15 control register ... we don't seem to be able to
 103         # read/modify/write its value through a TCL variable, so just
 104         # write it.  Fields are zero unless listed here ... and note
 105         # that OpenOCD numbers this register "2", not "1" (!).
 106         #
 107         #  - Core to use Async Clocking mode (so it uses 184 MHz most
 108         #    of the time instead of limiting to the master clock rate):
 109         #       iA(31) = 1, nF(30) = 1
 110         #  - Icache on (it's disabled now, slowing i-fetches)
 111         #       I(12) = 1
 112         #  - Reserved/ones
 113         #       6:3 = 1
 114         arm920t cp15 2 0xc0001078
 115 }
 116
 117 $_TARGETNAME configure -event reset-init {csb337_reset_init}
 118
 119 arm7_9 fast_memory_access enable