1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # The Cogent CSB732 board has a single i.MX35 chip
4 source [find target/imx35.cfg]
6 # Determined by trial and error
7 reset_config trst_and_srst combined
11 $_TARGETNAME configure -event gdb-attach { reset init }
12 $_TARGETNAME configure -event reset-init { csb732_init }
14 # Bare-bones initialization of core clocks and SDRAM
15 proc csb732_init { } {
17 # Disable fast writing only for init
18 memwrite burst disable
20 # All delay loops are omitted.
21 # We assume the interpreter latency is enough.
23 # Allow access to all coprocessors
24 arm mcr 15 0 15 1 0 0x2001
26 # Disable MMU, caches, write buffer
27 arm mcr 15 0 1 0 0 0x78
29 # Grant manager access to all domains
30 arm mcr 15 0 3 0 0 0xFFFFFFFF
32 # Set ARM clock to 532 MHz, AHB to 133 MHz
35 # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
36 mww 0x53F8001C 0xB2C01
38 set ESDMISC 0xB8001010
39 set ESDCFG0 0xB8001004
40 set ESDCTL0 0xB8001000
46 mww $ESDCFG0 0x007fff3f
49 mww $ESDCTL0 0x92120080
51 # Precharge all dummy write
54 # Enable CS) auto-refresh
55 mww $ESDCTL0 0xA2120080
57 # Refresh twice (dummy writes)
61 # Enable CS0 load mode register
62 mww $ESDCTL0 0xB2120080
68 mww $ESDCTL0 0x82226080
71 # Re-enable fast writing
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