tcl/board/imx53loco.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 ##################################################################################
   4 # Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> #
   5 # Kiwigrid GmbH                                                                  #
   6 ##################################################################################
   7
   8 # The IMX53LOCO (QSB) board has a single IMX53 chip
   9 source [find target/imx53.cfg]
  10 # Helper for common memory read/modify/write procedures
  11 source [find mem_helper.tcl]
  12
  13 echo "iMX53 Loco board lodaded."
  14
  15 # Set reset type
  16 #reset_config srst_only
  17
  18 adapter speed 3000
  19
  20 # Slow speed to be sure it will work
  21 jtag_rclk 1000
  22 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
  23
  24 #adapter srst delay 200
  25 #jtag_ntrst_delay 200
  26
  27 $_TARGETNAME configure -event "reset-assert" {
  28         echo "Resetting ...."
  29         #cortex_a dbginit
  30 }
  31
  32 $_TARGETNAME configure -event reset-init { loco_init }
  33
  34 global AIPS1_BASE_ADDR
  35 set AIPS1_BASE_ADDR     0x53F00000
  36 global AIPS2_BASE_ADDR
  37 set AIPS2_BASE_ADDR     0x63F00000
  38
  39 proc loco_init { } {
  40         echo "Reset-init..."
  41         ; # halt the CPU
  42         halt
  43
  44         echo "HW version [format %x [mrw 0x48]]"
  45
  46         dap apsel 1
  47         DCD
  48
  49         ; # ARM errata ID #468414
  50         set tR [arm mrc 15 0 1 0 1]
  51         arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]        ; # enable L1NEON bit
  52
  53         init_l2cc
  54         init_aips
  55         init_clock
  56
  57         dap apsel 0
  58
  59         ; # Force ARM state
  60         ; #reg cpsr 0x000001D3
  61         arm core_state arm
  62
  63         jtag_rclk 3000
  64 #       adapter speed 3000
  65 }
  66
  67
  68 # L2CC Cache setup/invalidation/disable
  69 proc init_l2cc { } {
  70         ; #/* explicitly disable L2 cache */
  71         ; #mrc 15, 0, r0, c1, c0, 1
  72         set tR [arm mrc 15 0 1 0 1]
  73         ; #bic r0, r0, #0x2
  74         ; #mcr 15, 0, r0, c1, c0, 1
  75         arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
  76
  77         ; #/* reconfigure L2 cache aux control reg */
  78         ; #mov r0, #0xC0                   /* tag RAM */
  79         ; #add r0, r0, #0x4                /* data RAM */
  80         ; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */
  81         ; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */
  82         ; #orr r0, r0, #(1 << 22)          /* disable write allocate */
  83
  84         ; #mcr 15, 1, r0, c9, c0, 2
  85         arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
  86 }
  87
  88
  89 # AIPS setup - Only setup MPROTx registers.
  90 # The PACR default values are good.
  91 proc init_aips { } {
  92         ; # Set all MPROTx to be non-bufferable, trusted for R/W,
  93         ; # not forced to user-mode.
  94         global AIPS1_BASE_ADDR
  95         global AIPS2_BASE_ADDR
  96         set VAL                 0x77777777
  97
  98 #       dap apsel 1
  99         mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
 100         mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
 101         mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
 102         mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
 103 #       dap apsel 0
 104 }
 105
 106
 107 proc init_clock { } {
 108         global AIPS1_BASE_ADDR
 109         global AIPS2_BASE_ADDR
 110         set CCM_BASE_ADDR       [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
 111         set CLKCTL_CCSR         0x0C
 112         set CLKCTL_CBCDR        0x14
 113         set CLKCTL_CBCMR        0x18
 114         set PLL1_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x00080000}]
 115         set PLL2_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x00084000}]
 116         set PLL3_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x00088000}]
 117         set PLL4_BASE_ADDR      [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
 118         set CLKCTL_CSCMR1       0x1C
 119         set CLKCTL_CDHIPR       0x48
 120         set PLATFORM_BASE_ADDR  [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
 121         set CLKCTL_CSCDR1       0x24
 122         set CLKCTL_CCDR         0x04
 123
 124         ; # Switch ARM to step clock
 125         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
 126
 127         return
 128         echo "not returned"
 129         setup_pll $PLL1_BASE_ADDR 800
 130         setup_pll $PLL3_BASE_ADDR 400
 131
 132         ; # Switch peripheral to PLL3
 133         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
 134         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
 135         while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 136
 137         setup_pll $PLL2_BASE_ADDR 400
 138
 139         ; # Switch peripheral to PLL2
 140         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
 141
 142         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
 143
 144         ; # change uart clk parent to pll2
 145         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
 146
 147         ; # make sure change is effective
 148         while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
 149
 150         setup_pll $PLL3_BASE_ADDR 216
 151
 152         setup_pll $PLL4_BASE_ADDR 455
 153
 154         ; # Set the platform clock dividers
 155         mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
 156
 157         mww [expr {$CCM_BASE_ADDR + 0x10}] 0
 158
 159         ; # Switch ARM back to PLL 1.
 160         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
 161
 162         ; # make uart div=6
 163         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
 164
 165         ; # Restore the default values in the Gate registers
 166         mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
 167         mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
 168         mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
 169         mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
 170         mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
 171         mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
 172         mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
 173         mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
 174
 175         mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
 176
 177         ; # for cko - for ARM div by 8
 178         mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
 179 }
 180
 181
 182 proc setup_pll { PLL_ADDR CLK } {
 183         set PLL_DP_CTL          0x00
 184         set PLL_DP_CONFIG       0x04
 185         set PLL_DP_OP           0x08
 186         set PLL_DP_HFS_OP       0x1C
 187         set PLL_DP_MFD          0x0C
 188         set PLL_DP_HFS_MFD      0x20
 189         set PLL_DP_MFN          0x10
 190         set PLL_DP_HFS_MFN      0x24
 191
 192         if {$CLK == 1000} {
 193                 set DP_OP       [expr {(10 << 4) + ((1 - 1) << 0)}]
 194                 set DP_MFD      [expr {12 - 1}]
 195                 set DP_MFN      5
 196         } elseif {$CLK == 850} {
 197                 set DP_OP       [expr {(8 << 4) + ((1 - 1)  << 0)}]
 198                 set DP_MFD      [expr {48 - 1}]
 199                 set DP_MFN      41
 200         } elseif {$CLK == 800} {
 201                 set DP_OP       [expr {(8 << 4) + ((1 - 1)  << 0)}]
 202                 set DP_MFD      [expr {3 - 1}]
 203                 set DP_MFN      1
 204         } elseif {$CLK == 700} {
 205                 set DP_OP       [expr {(7 << 4) + ((1 - 1)  << 0)}]
 206                 set DP_MFD      [expr {24 - 1}]
 207                 set DP_MFN      7
 208         } elseif {$CLK == 600} {
 209                 set DP_OP       [expr {(6 << 4) + ((1 - 1)  << 0)}]
 210                 set DP_MFD      [expr {4 - 1}]
 211                 set DP_MFN      1
 212         } elseif {$CLK == 665} {
 213                 set DP_OP       [expr {(6 << 4) + ((1 - 1)  << 0)}]
 214                 set DP_MFD      [expr {96 - 1}]
 215                 set DP_MFN      89
 216         } elseif {$CLK == 532} {
 217                 set DP_OP       [expr {(5 << 4) + ((1 - 1)  << 0)}]
 218                 set DP_MFD      [expr {24 - 1}]
 219                 set DP_MFN      13
 220         } elseif {$CLK == 455} {
 221                 set DP_OP       [expr {(8 << 4) + ((2 - 1)  << 0)}]
 222                 set DP_MFD      [expr {48 - 1}]
 223                 set DP_MFN      71
 224         } elseif {$CLK == 400} {
 225                 set DP_OP       [expr {(8 << 4) + ((2 - 1)  << 0)}]
 226                 set DP_MFD      [expr {3 - 1}]
 227                 set DP_MFN      1
 228         } elseif {$CLK == 216} {
 229                 set DP_OP       [expr {(6 << 4) + ((3 - 1)  << 0)}]
 230                 set DP_MFD      [expr {4 - 1}]
 231                 set DP_MFN      3
 232         } else {
 233                 error "Error (setup_dll): clock not found!"
 234         }
 235
 236         mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
 237         mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
 238
 239         mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
 240         mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
 241
 242         mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
 243         mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
 244
 245         mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
 246         mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
 247
 248         mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
 249         while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
 250 }
 251
 252
 253 proc CPU_2_BE_32 { L } {
 254         return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]
 255 }
 256
 257
 258 # Device Configuration Data
 259 proc DCD { } {
 260 #       dap apsel 1
 261         mww 0x53FA8554 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
 262         mww 0x53FA8558 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
 263         mww 0x53FA8560 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
 264         mww 0x53FA8564 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT
 265         mww 0x53FA8568 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
 266         mww 0x53FA8570 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
 267         mww 0x53FA8574 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
 268         mww 0x53FA8578 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
 269         mww 0x53FA857c 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
 270         mww 0x53FA8580 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
 271         mww 0x53FA8584 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
 272         mww 0x53FA8588 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
 273         mww 0x53FA8590 0x00300040       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
 274         mww 0x53FA8594 0x00300000       ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
 275         mww 0x53FA86f0 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_ADDDS
 276         mww 0x53FA86f4 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
 277         mww 0x53FA86fc 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
 278         mww 0x53FA8714 0x00000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode
 279         mww 0x53FA8718 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B0DS
 280         mww 0x53FA871c 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B1DS
 281         mww 0x53FA8720 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_CTLDS
 282         mww 0x53FA8724 0x04000000       ;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=
 283         mww 0x53FA8728 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B2DS
 284         mww 0x53FA872c 0x00300000       ;# IOMUXC_SW_PAD_CTL_GRP_B3DS
 285
 286         # Initialize DDR2 memory
 287         mww 0x63FD9088 0x35343535       ;# ESDCTL_RDDLCTL
 288         mww 0x63FD9090 0x4d444c44       ;# ESDCTL_WRDLCTL
 289         mww 0x63FD907c 0x01370138       ;# ESDCTL_DGCTRL0
 290         mww 0x63FD9080 0x013b013c       ;# ESDCTL_DGCTRL1
 291         mww 0x63FD9018 0x00011740       ;# ESDCTL_ESDMISC
 292         mww 0x63FD9000 0xc3190000       ;# ESDCTL_ESDCTL
 293         mww 0x63FD900c 0x9f5152e3       ;# ESDCTL_ESDCFG0
 294         mww 0x63FD9010 0xb68e8a63       ;# ESDCTL_ESDCFG1
 295         mww 0x63FD9014 0x01ff00db       ;# ESDCTL_ESDCFG2
 296         mww 0x63FD902c 0x000026d2       ;# ESDCTL_ESDRWD
 297         mww 0x63FD9030 0x009f0e21       ;# ESDCTL_ESDOR
 298         mww 0x63FD9008 0x12273030       ;# ESDCTL_ESDOTC
 299         mww 0x63FD9004 0x0002002d       ;# ESDCTL_ESDPDC
 300         mww 0x63FD901c 0x00008032       ;# ESDCTL_ESDSCR
 301         mww 0x63FD901c 0x00008033       ;# ESDCTL_ESDSCR
 302         mww 0x63FD901c 0x00028031       ;# ESDCTL_ESDSCR
 303         mww 0x63FD901c 0x052080b0       ;# ESDCTL_ESDSCR
 304         mww 0x63FD901c 0x04008040       ;# ESDCTL_ESDSCR
 305         mww 0x63FD901c 0x0000803a       ;# ESDCTL_ESDSCR
 306         mww 0x63FD901c 0x0000803b       ;# ESDCTL_ESDSCR
 307         mww 0x63FD901c 0x00028039       ;# ESDCTL_ESDSCR
 308         mww 0x63FD901c 0x05208138       ;# ESDCTL_ESDSCR
 309         mww 0x63FD901c 0x04008048       ;# ESDCTL_ESDSCR
 310         mww 0x63FD9020 0x00005800       ;# ESDCTL_ESDREF
 311         mww 0x63FD9040 0x04b80003       ;# ESDCTL_ZQHWCTRL
 312         mww 0x63FD9058 0x00022227       ;# ESDCTL_ODTCTRL
 313         mww 0x63FD901C 0x00000000       ;# ESDCTL_ESDSCR
 314 #       dap apsel 0
 315 }
 316
 317 # vim:filetype=tcl