tcl/board/spear320cpu.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # Configuration for the ST SPEAr320 CPU board
   4 # EVAL_SPEAr320CPU Rev. 2.0
   5 # http://www.st.com/spear
   6 #
   7 # Date:      2011-11-18
   8 # Author:    Antonio Borneo <borneo.antonio@gmail.com>
   9
  10 # The standard board has JTAG SRST not connected.
  11 # This script targets such boards using quirky code to bypass the issue.
  12
  13
  14 source [find mem_helper.tcl]
  15 source [find target/spear3xx.cfg]
  16 source [find chip/st/spear/spear3xx_ddr.tcl]
  17 source [find chip/st/spear/spear3xx.tcl]
  18
  19 arm7_9 dcc_downloads enable
  20 arm7_9 fast_memory_access enable
  21
  22
  23 # Serial NOR on SMI CS0. 8Mbyte.
  24 set _FLASHNAME1 $_CHIPNAME.snor
  25 flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
  26
  27 if { [info exists BOARD_HAS_SRST] } {
  28         # Modified board has SRST on JTAG connector
  29         reset_config trst_and_srst separate srst_gates_jtag \
  30                 trst_push_pull srst_open_drain
  31 } else {
  32         # Standard board has no SRST on JTAG connector
  33         reset_config trst_only separate srst_gates_jtag trst_push_pull
  34         source [find chip/st/spear/quirk_no_srst.tcl]
  35 }
  36
  37 $_TARGETNAME configure -event reset-init { spear320cpu_init }
  38
  39 if { [info exists DDR_CHIPS] } {
  40         set _DDR_CHIPS $DDR_CHIPS
  41 } else {
  42         set _DDR_CHIPS 1
  43 }
  44
  45 proc spear320cpu_init {} {
  46         global _DDR_CHIPS
  47         reg pc 0xffff0020;      # loop forever
  48
  49         sp3xx_clock_default
  50         sp3xx_common_init
  51         sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" $_DDR_CHIPS
  52         sp320_init
  53 }