tcl/board/stm32l4r9i-disco.cfg

   1 # This is a STM32L4R9I discovery board with a single STM32L4R9AII6 chip.
   2 # http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html
   3
   4 # This is for using the onboard STLINK
   5 source [find interface/stlink.cfg]
   6
   7 transport select hla_swd
   8
   9 # increase working area to 96KB
  10 set WORKAREASIZE 0x18000
  11
  12 # enable stmqspi
  13 set OCTOSPI1 1
  14 set OCTOSPI2 0
  15
  16 source [find target/stm32l4x.cfg]
  17
  18 # OCTOSPI initialization
  19 # octo: 8-line mode
  20 proc octospi_init { octo } {
  21         global a b
  22         mmw 0x4002104C 0x001001FF 0                             ;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
  23         mmw 0x40021050 0x00000300 0                             ;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
  24         mmw 0x40021058 0x10000000 0                             ;# RCC_APB1ENR1 |= PWREN (enable clock)
  25         sleep 1                                                                 ;# Wait for clock startup
  26
  27         mmw 0x40007004 0x00000200 0                             ;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
  28
  29         mww 0x50061C04 0x00000000                               ;# OCTOSPIM_P1CR: disable Port 1
  30         mww 0x50061C08 0x03010111                               ;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
  31
  32         # PG12: P2_NCS, PI06: P2_CLK, PG15: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PH10: P2_IO5,
  33         # PH09: P2_IO4, PH08: P2_IO3, PI09: P2_IO2, PI10: P2_IO1, PI11: P2_IO0
  34
  35         # PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PH10:AF05:V, PH09:AF05:V
  36         # PH08:AF05:V, PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
  37
  38         # Port G: PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V
  39         mmw 0x48001800 0x82280000 0x41140000    ;# MODER
  40         mmw 0x48001808 0xC33C0000 0x00000000    ;# OSPEEDR
  41         mmw 0x48001824 0x50050550 0xA00A0AA0    ;# AFRH
  42
  43         # Port H: PH10:AF05:V, PH09:AF05:V, PH08:AF05:V
  44         mmw 0x48001C00 0x002A0000 0x00150000    ;# MODER
  45         mmw 0x48001C08 0x003F0000 0x00000000    ;# OSPEEDR
  46         mmw 0x48001C24 0x00000555 0x00000AAA    ;# AFRH
  47
  48         # Port I: PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
  49         mmw 0x48002000 0x00A82000 0x00541000    ;# MODER
  50         mmw 0x48002008 0x00FC3000 0x00000000    ;# OSPEEDR
  51         mmw 0x48002020 0x05000000 0x0A000000    ;# AFRL
  52         mmw 0x48002024 0x00005550 0x0000AAA0    ;# AFRH
  53
  54         # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
  55         mww 0xA0001130 0x00001000                               ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  56         mww 0xA0001000 0x3040000B                               ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
  57         mww 0xA0001008 0x01190100                               ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
  58         mww 0xA000100C 0x00000001                               ;# OCTOSPI_DCR2: PRESCALER=1
  59
  60         mww 0xA0001108 0x00000000                               ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
  61         mww 0xA0001100 0x01003101                               ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
  62         mww 0xA0001110 0x00000013                               ;# OCTOSPI_IR: INSTR=READ4B
  63
  64         if { $octo == 1 } {
  65                 stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00                       ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
  66                 stmqspi cmd $a 0 0x06                                                           ;# Write Enable
  67                 stmqspi cmd $a 1 0x05                                                           ;# Read Status Register
  68                 stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02          ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
  69
  70                 # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
  71                 mww 0xA0001000 0x3040000B                               ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
  72                 mww 0xA0001108 0x10000006                               ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
  73                 mww 0xA0001100 0x2C003C1C                               ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
  74                 mww 0xA0001110 0x0000EE11                               ;# OCTOSPI_IR: INSTR=OCTA DTR Read
  75
  76                 flash probe $a                                                  ;# reload configuration from CR, TCR, CCR, IR register values
  77
  78                 stmqspi cmd $a 0 0x06                                                           ;# Write Enable
  79                 stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00                       ;# Read Status Register (note dummy address in 8-line mode)
  80                 stmqspi cmd $a 0 0x04                                                           ;# Write Disable
  81                 stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00                       ;# Read Status Register (note dummy address in 8-line mode)
  82                 stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00                       ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
  83         }
  84 }
  85
  86 $_TARGETNAME configure -event reset-init {
  87         mmw 0x40022000 0x00000003 0x0000000C    ;# 3 WS for 72 MHz HCLK
  88         sleep 1
  89         mmw 0x40021000 0x00000100 0x00000000    ;# HSI on
  90         mww 0x4002100C 0x01002432                               ;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
  91         mww 0x40021008 0x00008001                               ;# always HSI, APB1: /1, APB2: /1
  92         mmw 0x40021000 0x01000000 0x00000000    ;# PLL on
  93         sleep 1
  94         mmw 0x40021008 0x00000003 0x00000000    ;# switch to PLL
  95         sleep 1
  96
  97         adapter speed 4000
  98
  99         octospi_init 1
 100 }