tcl/board/topasa900.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # Thanks to Pieter Conradie for this script!
   4 # Target:    Toshiba TOPAS900 -- TMPA900 Starterkit
   5 ######################################
   6
   7 # We add to the minimal configuration.
   8 source [find target/tmpa900.cfg]
   9
  10 ######################
  11 # Target configuration
  12 ######################
  13
  14 #$_TARGETNAME configure -event gdb-attach { reset init }
  15 $_TARGETNAME configure -event reset-init { topasa900_init }
  16
  17 proc topasa900_init { } {
  18 # Init PLL
  19 # my settings
  20         mww 0xf005000c 0x00000007
  21         mww 0xf0050010 0x00000065
  22         mww 0xf005000c 0x000000a7
  23         sleep 10
  24         mdw 0xf0050008
  25         mww 0xf0050008 0x00000002
  26         mww 0xf0050004 0x00000000
  27 # NEW: set CLKCR5
  28         mww 0xf0050054 0x00000040
  29 #
  30 # bplan settings
  31 #       mww 0xf0050004 0x00000000
  32 #       mww 0xf005000c 0x000000a7
  33 #       sleep 10
  34 #       mdw 0xf0050008
  35 #       mww 0xf0050008 0x00000002
  36 #       mww 0xf0050010 0x00000065
  37 #       mww 0xf0050054 0x00000040
  38         sleep 10
  39 # Init SDRAM
  40 #  _PMCDRV          = 0x00000071;
  41 #  //
  42 #  // Initialize SDRAM timing parameter
  43 #  //
  44 #  _DMC_CAS_LATENCY = 0x00000006;
  45 #  _DMC_T_DQSS      = 0x00000000;
  46 #  _DMC_T_MRD       = 0x00000002;
  47 #  _DMC_T_RAS       = 0x00000007;
  48 #
  49 #  _DMC_T_RC        = 0x0000000A;
  50 #  _DMC_T_RCD       = 0x00000013;
  51 #
  52 #  _DMC_T_RFC       = 0x0000010A;
  53 #
  54 #  _DMC_T_RP        = 0x00000013;
  55 #  _DMC_T_RRD       = 0x00000002;
  56 #  _DMC_T_WR        = 0x00000002;
  57 #  _DMC_T_WTR       = 0x00000001;
  58 #  _DMC_T_XP        = 0x0000000A;
  59 #  _DMC_T_XSR       = 0x0000000B;
  60 #  _DMC_T_ESR       = 0x00000014;
  61 #
  62 #  //
  63 #  // Configure SDRAM type parameter
  64 #  _DMC_MEMORY_CFG  = 0x00008011;
  65 #  _DMC_USER_CONFIG = 0x00000011;   // 32 bit memory interface
  66 #
  67 #
  68 #  _DMC_REFRESH_PRD = 0x00000A60;
  69 #  _DMC_CHIP_0_CFG  = 0x000140FC;
  70 #
  71 #  _DMC_DIRECT_CMD  = 0x000C0000;
  72 #  _DMC_DIRECT_CMD  = 0x00000000;
  73 #
  74 #  _DMC_DIRECT_CMD  = 0x00040000;
  75 #  _DMC_DIRECT_CMD  = 0x00040000;
  76 #  _DMC_DIRECT_CMD  = 0x00080031;
  77 #  //
  78 #  // Finally start SDRAM
  79 #  //
  80 #  _DMC_MEMC_CMD    = MEMC_CMD_GO;
  81 #  */
  82
  83         mww 0xf0020260 0x00000071
  84         mww 0xf4300014 0x00000006
  85         mww 0xf4300018 0x00000000
  86         mww 0xf430001C 0x00000002
  87         mww 0xf4300020 0x00000007
  88         mww 0xf4300024 0x0000000A
  89         mww 0xf4300028 0x00000013
  90         mww 0xf430002C 0x0000010A
  91         mww 0xf4300030 0x00000013
  92         mww 0xf4300034 0x00000002
  93         mww 0xf4300038 0x00000002
  94         mww 0xf430003C 0x00000001
  95         mww 0xf4300040 0x0000000A
  96         mww 0xf4300044 0x0000000B
  97         mww 0xf4300048 0x00000014
  98         mww 0xf430000C 0x00008011
  99         mww 0xf4300304 0x00000011
 100         mww 0xf4300010 0x00000A60
 101         mww 0xf4300200 0x000140FC
 102         mww 0xf4300008 0x000C0000
 103         mww 0xf4300008 0x00000000
 104         mww 0xf4300008 0x00040000
 105         mww 0xf4300008 0x00040000
 106         mww 0xf4300008 0x00080031
 107         mww 0xf4300004 0x00000000
 108
 109         sleep 10
 110 #       adapter speed NNNN
 111
 112 # remap off in case of IROM boot
 113         mww 0xf0000004 0x00000001
 114
 115 }
 116
 117 # comment the following out if usinf J-Link, it soes not support DCC
 118 arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
 119
 120
 121 #####################
 122 # Flash configuration
 123 #####################
 124
 125 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 126 set _FLASHNAME $_CHIPNAME.flash
 127 flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME